Loading...
Note: File does not exist in v3.1.
1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _MACB_H
11#define _MACB_H
12
13#define MACB_GREGS_NBR 16
14#define MACB_GREGS_VERSION 1
15
16/* MACB register offsets */
17#define MACB_NCR 0x0000
18#define MACB_NCFGR 0x0004
19#define MACB_NSR 0x0008
20#define MACB_TAR 0x000c /* AT91RM9200 only */
21#define MACB_TCR 0x0010 /* AT91RM9200 only */
22#define MACB_TSR 0x0014
23#define MACB_RBQP 0x0018
24#define MACB_TBQP 0x001c
25#define MACB_RSR 0x0020
26#define MACB_ISR 0x0024
27#define MACB_IER 0x0028
28#define MACB_IDR 0x002c
29#define MACB_IMR 0x0030
30#define MACB_MAN 0x0034
31#define MACB_PTR 0x0038
32#define MACB_PFR 0x003c
33#define MACB_FTO 0x0040
34#define MACB_SCF 0x0044
35#define MACB_MCF 0x0048
36#define MACB_FRO 0x004c
37#define MACB_FCSE 0x0050
38#define MACB_ALE 0x0054
39#define MACB_DTF 0x0058
40#define MACB_LCOL 0x005c
41#define MACB_EXCOL 0x0060
42#define MACB_TUND 0x0064
43#define MACB_CSE 0x0068
44#define MACB_RRE 0x006c
45#define MACB_ROVR 0x0070
46#define MACB_RSE 0x0074
47#define MACB_ELE 0x0078
48#define MACB_RJA 0x007c
49#define MACB_USF 0x0080
50#define MACB_STE 0x0084
51#define MACB_RLE 0x0088
52#define MACB_TPF 0x008c
53#define MACB_HRB 0x0090
54#define MACB_HRT 0x0094
55#define MACB_SA1B 0x0098
56#define MACB_SA1T 0x009c
57#define MACB_SA2B 0x00a0
58#define MACB_SA2T 0x00a4
59#define MACB_SA3B 0x00a8
60#define MACB_SA3T 0x00ac
61#define MACB_SA4B 0x00b0
62#define MACB_SA4T 0x00b4
63#define MACB_TID 0x00b8
64#define MACB_TPQ 0x00bc
65#define MACB_USRIO 0x00c0
66#define MACB_WOL 0x00c4
67#define MACB_MID 0x00fc
68
69/* GEM register offsets. */
70#define GEM_NCFGR 0x0004
71#define GEM_USRIO 0x000c
72#define GEM_DMACFG 0x0010
73#define GEM_HRB 0x0080
74#define GEM_HRT 0x0084
75#define GEM_SA1B 0x0088
76#define GEM_SA1T 0x008C
77#define GEM_SA2B 0x0090
78#define GEM_SA2T 0x0094
79#define GEM_SA3B 0x0098
80#define GEM_SA3T 0x009C
81#define GEM_SA4B 0x00A0
82#define GEM_SA4T 0x00A4
83#define GEM_OTX 0x0100
84#define GEM_DCFG1 0x0280
85#define GEM_DCFG2 0x0284
86#define GEM_DCFG3 0x0288
87#define GEM_DCFG4 0x028c
88#define GEM_DCFG5 0x0290
89#define GEM_DCFG6 0x0294
90#define GEM_DCFG7 0x0298
91
92/* Bitfields in NCR */
93#define MACB_LB_OFFSET 0
94#define MACB_LB_SIZE 1
95#define MACB_LLB_OFFSET 1
96#define MACB_LLB_SIZE 1
97#define MACB_RE_OFFSET 2
98#define MACB_RE_SIZE 1
99#define MACB_TE_OFFSET 3
100#define MACB_TE_SIZE 1
101#define MACB_MPE_OFFSET 4
102#define MACB_MPE_SIZE 1
103#define MACB_CLRSTAT_OFFSET 5
104#define MACB_CLRSTAT_SIZE 1
105#define MACB_INCSTAT_OFFSET 6
106#define MACB_INCSTAT_SIZE 1
107#define MACB_WESTAT_OFFSET 7
108#define MACB_WESTAT_SIZE 1
109#define MACB_BP_OFFSET 8
110#define MACB_BP_SIZE 1
111#define MACB_TSTART_OFFSET 9
112#define MACB_TSTART_SIZE 1
113#define MACB_THALT_OFFSET 10
114#define MACB_THALT_SIZE 1
115#define MACB_NCR_TPF_OFFSET 11
116#define MACB_NCR_TPF_SIZE 1
117#define MACB_TZQ_OFFSET 12
118#define MACB_TZQ_SIZE 1
119
120/* Bitfields in NCFGR */
121#define MACB_SPD_OFFSET 0
122#define MACB_SPD_SIZE 1
123#define MACB_FD_OFFSET 1
124#define MACB_FD_SIZE 1
125#define MACB_BIT_RATE_OFFSET 2
126#define MACB_BIT_RATE_SIZE 1
127#define MACB_JFRAME_OFFSET 3
128#define MACB_JFRAME_SIZE 1
129#define MACB_CAF_OFFSET 4
130#define MACB_CAF_SIZE 1
131#define MACB_NBC_OFFSET 5
132#define MACB_NBC_SIZE 1
133#define MACB_NCFGR_MTI_OFFSET 6
134#define MACB_NCFGR_MTI_SIZE 1
135#define MACB_UNI_OFFSET 7
136#define MACB_UNI_SIZE 1
137#define MACB_BIG_OFFSET 8
138#define MACB_BIG_SIZE 1
139#define MACB_EAE_OFFSET 9
140#define MACB_EAE_SIZE 1
141#define MACB_CLK_OFFSET 10
142#define MACB_CLK_SIZE 2
143#define MACB_RTY_OFFSET 12
144#define MACB_RTY_SIZE 1
145#define MACB_PAE_OFFSET 13
146#define MACB_PAE_SIZE 1
147#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
148#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
149#define MACB_RBOF_OFFSET 14
150#define MACB_RBOF_SIZE 2
151#define MACB_RLCE_OFFSET 16
152#define MACB_RLCE_SIZE 1
153#define MACB_DRFCS_OFFSET 17
154#define MACB_DRFCS_SIZE 1
155#define MACB_EFRHD_OFFSET 18
156#define MACB_EFRHD_SIZE 1
157#define MACB_IRXFCS_OFFSET 19
158#define MACB_IRXFCS_SIZE 1
159
160/* GEM specific NCFGR bitfields. */
161#define GEM_GBE_OFFSET 10
162#define GEM_GBE_SIZE 1
163#define GEM_CLK_OFFSET 18
164#define GEM_CLK_SIZE 3
165#define GEM_DBW_OFFSET 21
166#define GEM_DBW_SIZE 2
167
168/* Constants for data bus width. */
169#define GEM_DBW32 0
170#define GEM_DBW64 1
171#define GEM_DBW128 2
172
173/* Bitfields in DMACFG. */
174#define GEM_FBLDO_OFFSET 0
175#define GEM_FBLDO_SIZE 5
176#define GEM_ENDIA_OFFSET 7
177#define GEM_ENDIA_SIZE 1
178#define GEM_RXBMS_OFFSET 8
179#define GEM_RXBMS_SIZE 2
180#define GEM_TXPBMS_OFFSET 10
181#define GEM_TXPBMS_SIZE 1
182#define GEM_TXCOEN_OFFSET 11
183#define GEM_TXCOEN_SIZE 1
184#define GEM_RXBS_OFFSET 16
185#define GEM_RXBS_SIZE 8
186#define GEM_DDRP_OFFSET 24
187#define GEM_DDRP_SIZE 1
188
189
190/* Bitfields in NSR */
191#define MACB_NSR_LINK_OFFSET 0
192#define MACB_NSR_LINK_SIZE 1
193#define MACB_MDIO_OFFSET 1
194#define MACB_MDIO_SIZE 1
195#define MACB_IDLE_OFFSET 2
196#define MACB_IDLE_SIZE 1
197
198/* Bitfields in TSR */
199#define MACB_UBR_OFFSET 0
200#define MACB_UBR_SIZE 1
201#define MACB_COL_OFFSET 1
202#define MACB_COL_SIZE 1
203#define MACB_TSR_RLE_OFFSET 2
204#define MACB_TSR_RLE_SIZE 1
205#define MACB_TGO_OFFSET 3
206#define MACB_TGO_SIZE 1
207#define MACB_BEX_OFFSET 4
208#define MACB_BEX_SIZE 1
209#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
210#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
211#define MACB_COMP_OFFSET 5
212#define MACB_COMP_SIZE 1
213#define MACB_UND_OFFSET 6
214#define MACB_UND_SIZE 1
215
216/* Bitfields in RSR */
217#define MACB_BNA_OFFSET 0
218#define MACB_BNA_SIZE 1
219#define MACB_REC_OFFSET 1
220#define MACB_REC_SIZE 1
221#define MACB_OVR_OFFSET 2
222#define MACB_OVR_SIZE 1
223
224/* Bitfields in ISR/IER/IDR/IMR */
225#define MACB_MFD_OFFSET 0
226#define MACB_MFD_SIZE 1
227#define MACB_RCOMP_OFFSET 1
228#define MACB_RCOMP_SIZE 1
229#define MACB_RXUBR_OFFSET 2
230#define MACB_RXUBR_SIZE 1
231#define MACB_TXUBR_OFFSET 3
232#define MACB_TXUBR_SIZE 1
233#define MACB_ISR_TUND_OFFSET 4
234#define MACB_ISR_TUND_SIZE 1
235#define MACB_ISR_RLE_OFFSET 5
236#define MACB_ISR_RLE_SIZE 1
237#define MACB_TXERR_OFFSET 6
238#define MACB_TXERR_SIZE 1
239#define MACB_TCOMP_OFFSET 7
240#define MACB_TCOMP_SIZE 1
241#define MACB_ISR_LINK_OFFSET 9
242#define MACB_ISR_LINK_SIZE 1
243#define MACB_ISR_ROVR_OFFSET 10
244#define MACB_ISR_ROVR_SIZE 1
245#define MACB_HRESP_OFFSET 11
246#define MACB_HRESP_SIZE 1
247#define MACB_PFR_OFFSET 12
248#define MACB_PFR_SIZE 1
249#define MACB_PTZ_OFFSET 13
250#define MACB_PTZ_SIZE 1
251
252/* Bitfields in MAN */
253#define MACB_DATA_OFFSET 0
254#define MACB_DATA_SIZE 16
255#define MACB_CODE_OFFSET 16
256#define MACB_CODE_SIZE 2
257#define MACB_REGA_OFFSET 18
258#define MACB_REGA_SIZE 5
259#define MACB_PHYA_OFFSET 23
260#define MACB_PHYA_SIZE 5
261#define MACB_RW_OFFSET 28
262#define MACB_RW_SIZE 2
263#define MACB_SOF_OFFSET 30
264#define MACB_SOF_SIZE 2
265
266/* Bitfields in USRIO (AVR32) */
267#define MACB_MII_OFFSET 0
268#define MACB_MII_SIZE 1
269#define MACB_EAM_OFFSET 1
270#define MACB_EAM_SIZE 1
271#define MACB_TX_PAUSE_OFFSET 2
272#define MACB_TX_PAUSE_SIZE 1
273#define MACB_TX_PAUSE_ZERO_OFFSET 3
274#define MACB_TX_PAUSE_ZERO_SIZE 1
275
276/* Bitfields in USRIO (AT91) */
277#define MACB_RMII_OFFSET 0
278#define MACB_RMII_SIZE 1
279#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
280#define GEM_RGMII_SIZE 1
281#define MACB_CLKEN_OFFSET 1
282#define MACB_CLKEN_SIZE 1
283
284/* Bitfields in WOL */
285#define MACB_IP_OFFSET 0
286#define MACB_IP_SIZE 16
287#define MACB_MAG_OFFSET 16
288#define MACB_MAG_SIZE 1
289#define MACB_ARP_OFFSET 17
290#define MACB_ARP_SIZE 1
291#define MACB_SA1_OFFSET 18
292#define MACB_SA1_SIZE 1
293#define MACB_WOL_MTI_OFFSET 19
294#define MACB_WOL_MTI_SIZE 1
295
296/* Bitfields in MID */
297#define MACB_IDNUM_OFFSET 16
298#define MACB_IDNUM_SIZE 16
299#define MACB_REV_OFFSET 0
300#define MACB_REV_SIZE 16
301
302/* Bitfields in DCFG1. */
303#define GEM_IRQCOR_OFFSET 23
304#define GEM_IRQCOR_SIZE 1
305#define GEM_DBWDEF_OFFSET 25
306#define GEM_DBWDEF_SIZE 3
307
308/* Constants for CLK */
309#define MACB_CLK_DIV8 0
310#define MACB_CLK_DIV16 1
311#define MACB_CLK_DIV32 2
312#define MACB_CLK_DIV64 3
313
314/* GEM specific constants for CLK. */
315#define GEM_CLK_DIV8 0
316#define GEM_CLK_DIV16 1
317#define GEM_CLK_DIV32 2
318#define GEM_CLK_DIV48 3
319#define GEM_CLK_DIV64 4
320#define GEM_CLK_DIV96 5
321
322/* Constants for MAN register */
323#define MACB_MAN_SOF 1
324#define MACB_MAN_WRITE 1
325#define MACB_MAN_READ 2
326#define MACB_MAN_CODE 2
327
328/* Capability mask bits */
329#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x1
330
331/* Bit manipulation macros */
332#define MACB_BIT(name) \
333 (1 << MACB_##name##_OFFSET)
334#define MACB_BF(name,value) \
335 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
336 << MACB_##name##_OFFSET)
337#define MACB_BFEXT(name,value)\
338 (((value) >> MACB_##name##_OFFSET) \
339 & ((1 << MACB_##name##_SIZE) - 1))
340#define MACB_BFINS(name,value,old) \
341 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
342 << MACB_##name##_OFFSET)) \
343 | MACB_BF(name,value))
344
345#define GEM_BIT(name) \
346 (1 << GEM_##name##_OFFSET)
347#define GEM_BF(name, value) \
348 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
349 << GEM_##name##_OFFSET)
350#define GEM_BFEXT(name, value)\
351 (((value) >> GEM_##name##_OFFSET) \
352 & ((1 << GEM_##name##_SIZE) - 1))
353#define GEM_BFINS(name, value, old) \
354 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
355 << GEM_##name##_OFFSET)) \
356 | GEM_BF(name, value))
357
358/* Register access macros */
359#define macb_readl(port,reg) \
360 __raw_readl((port)->regs + MACB_##reg)
361#define macb_writel(port,reg,value) \
362 __raw_writel((value), (port)->regs + MACB_##reg)
363#define gem_readl(port, reg) \
364 __raw_readl((port)->regs + GEM_##reg)
365#define gem_writel(port, reg, value) \
366 __raw_writel((value), (port)->regs + GEM_##reg)
367
368/*
369 * Conditional GEM/MACB macros. These perform the operation to the correct
370 * register dependent on whether the device is a GEM or a MACB. For registers
371 * and bitfields that are common across both devices, use macb_{read,write}l
372 * to avoid the cost of the conditional.
373 */
374#define macb_or_gem_writel(__bp, __reg, __value) \
375 ({ \
376 if (macb_is_gem((__bp))) \
377 gem_writel((__bp), __reg, __value); \
378 else \
379 macb_writel((__bp), __reg, __value); \
380 })
381
382#define macb_or_gem_readl(__bp, __reg) \
383 ({ \
384 u32 __v; \
385 if (macb_is_gem((__bp))) \
386 __v = gem_readl((__bp), __reg); \
387 else \
388 __v = macb_readl((__bp), __reg); \
389 __v; \
390 })
391
392/**
393 * struct macb_dma_desc - Hardware DMA descriptor
394 * @addr: DMA address of data buffer
395 * @ctrl: Control and status bits
396 */
397struct macb_dma_desc {
398 u32 addr;
399 u32 ctrl;
400};
401
402/* DMA descriptor bitfields */
403#define MACB_RX_USED_OFFSET 0
404#define MACB_RX_USED_SIZE 1
405#define MACB_RX_WRAP_OFFSET 1
406#define MACB_RX_WRAP_SIZE 1
407#define MACB_RX_WADDR_OFFSET 2
408#define MACB_RX_WADDR_SIZE 30
409
410#define MACB_RX_FRMLEN_OFFSET 0
411#define MACB_RX_FRMLEN_SIZE 12
412#define MACB_RX_OFFSET_OFFSET 12
413#define MACB_RX_OFFSET_SIZE 2
414#define MACB_RX_SOF_OFFSET 14
415#define MACB_RX_SOF_SIZE 1
416#define MACB_RX_EOF_OFFSET 15
417#define MACB_RX_EOF_SIZE 1
418#define MACB_RX_CFI_OFFSET 16
419#define MACB_RX_CFI_SIZE 1
420#define MACB_RX_VLAN_PRI_OFFSET 17
421#define MACB_RX_VLAN_PRI_SIZE 3
422#define MACB_RX_PRI_TAG_OFFSET 20
423#define MACB_RX_PRI_TAG_SIZE 1
424#define MACB_RX_VLAN_TAG_OFFSET 21
425#define MACB_RX_VLAN_TAG_SIZE 1
426#define MACB_RX_TYPEID_MATCH_OFFSET 22
427#define MACB_RX_TYPEID_MATCH_SIZE 1
428#define MACB_RX_SA4_MATCH_OFFSET 23
429#define MACB_RX_SA4_MATCH_SIZE 1
430#define MACB_RX_SA3_MATCH_OFFSET 24
431#define MACB_RX_SA3_MATCH_SIZE 1
432#define MACB_RX_SA2_MATCH_OFFSET 25
433#define MACB_RX_SA2_MATCH_SIZE 1
434#define MACB_RX_SA1_MATCH_OFFSET 26
435#define MACB_RX_SA1_MATCH_SIZE 1
436#define MACB_RX_EXT_MATCH_OFFSET 28
437#define MACB_RX_EXT_MATCH_SIZE 1
438#define MACB_RX_UHASH_MATCH_OFFSET 29
439#define MACB_RX_UHASH_MATCH_SIZE 1
440#define MACB_RX_MHASH_MATCH_OFFSET 30
441#define MACB_RX_MHASH_MATCH_SIZE 1
442#define MACB_RX_BROADCAST_OFFSET 31
443#define MACB_RX_BROADCAST_SIZE 1
444
445#define MACB_TX_FRMLEN_OFFSET 0
446#define MACB_TX_FRMLEN_SIZE 11
447#define MACB_TX_LAST_OFFSET 15
448#define MACB_TX_LAST_SIZE 1
449#define MACB_TX_NOCRC_OFFSET 16
450#define MACB_TX_NOCRC_SIZE 1
451#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
452#define MACB_TX_BUF_EXHAUSTED_SIZE 1
453#define MACB_TX_UNDERRUN_OFFSET 28
454#define MACB_TX_UNDERRUN_SIZE 1
455#define MACB_TX_ERROR_OFFSET 29
456#define MACB_TX_ERROR_SIZE 1
457#define MACB_TX_WRAP_OFFSET 30
458#define MACB_TX_WRAP_SIZE 1
459#define MACB_TX_USED_OFFSET 31
460#define MACB_TX_USED_SIZE 1
461
462/**
463 * struct macb_tx_skb - data about an skb which is being transmitted
464 * @skb: skb currently being transmitted
465 * @mapping: DMA address of the skb's data buffer
466 */
467struct macb_tx_skb {
468 struct sk_buff *skb;
469 dma_addr_t mapping;
470};
471
472/*
473 * Hardware-collected statistics. Used when updating the network
474 * device stats by a periodic timer.
475 */
476struct macb_stats {
477 u32 rx_pause_frames;
478 u32 tx_ok;
479 u32 tx_single_cols;
480 u32 tx_multiple_cols;
481 u32 rx_ok;
482 u32 rx_fcs_errors;
483 u32 rx_align_errors;
484 u32 tx_deferred;
485 u32 tx_late_cols;
486 u32 tx_excessive_cols;
487 u32 tx_underruns;
488 u32 tx_carrier_errors;
489 u32 rx_resource_errors;
490 u32 rx_overruns;
491 u32 rx_symbol_errors;
492 u32 rx_oversize_pkts;
493 u32 rx_jabbers;
494 u32 rx_undersize_pkts;
495 u32 sqe_test_errors;
496 u32 rx_length_mismatch;
497 u32 tx_pause_frames;
498};
499
500struct gem_stats {
501 u32 tx_octets_31_0;
502 u32 tx_octets_47_32;
503 u32 tx_frames;
504 u32 tx_broadcast_frames;
505 u32 tx_multicast_frames;
506 u32 tx_pause_frames;
507 u32 tx_64_byte_frames;
508 u32 tx_65_127_byte_frames;
509 u32 tx_128_255_byte_frames;
510 u32 tx_256_511_byte_frames;
511 u32 tx_512_1023_byte_frames;
512 u32 tx_1024_1518_byte_frames;
513 u32 tx_greater_than_1518_byte_frames;
514 u32 tx_underrun;
515 u32 tx_single_collision_frames;
516 u32 tx_multiple_collision_frames;
517 u32 tx_excessive_collisions;
518 u32 tx_late_collisions;
519 u32 tx_deferred_frames;
520 u32 tx_carrier_sense_errors;
521 u32 rx_octets_31_0;
522 u32 rx_octets_47_32;
523 u32 rx_frames;
524 u32 rx_broadcast_frames;
525 u32 rx_multicast_frames;
526 u32 rx_pause_frames;
527 u32 rx_64_byte_frames;
528 u32 rx_65_127_byte_frames;
529 u32 rx_128_255_byte_frames;
530 u32 rx_256_511_byte_frames;
531 u32 rx_512_1023_byte_frames;
532 u32 rx_1024_1518_byte_frames;
533 u32 rx_greater_than_1518_byte_frames;
534 u32 rx_undersized_frames;
535 u32 rx_oversize_frames;
536 u32 rx_jabbers;
537 u32 rx_frame_check_sequence_errors;
538 u32 rx_length_field_frame_errors;
539 u32 rx_symbol_errors;
540 u32 rx_alignment_errors;
541 u32 rx_resource_errors;
542 u32 rx_overruns;
543 u32 rx_ip_header_checksum_errors;
544 u32 rx_tcp_checksum_errors;
545 u32 rx_udp_checksum_errors;
546};
547
548struct macb;
549
550struct macb_or_gem_ops {
551 int (*mog_alloc_rx_buffers)(struct macb *bp);
552 void (*mog_free_rx_buffers)(struct macb *bp);
553 void (*mog_init_rings)(struct macb *bp);
554 int (*mog_rx)(struct macb *bp, int budget);
555};
556
557struct macb {
558 void __iomem *regs;
559
560 unsigned int rx_tail;
561 unsigned int rx_prepared_head;
562 struct macb_dma_desc *rx_ring;
563 struct sk_buff **rx_skbuff;
564 void *rx_buffers;
565 size_t rx_buffer_size;
566
567 unsigned int tx_head, tx_tail;
568 struct macb_dma_desc *tx_ring;
569 struct macb_tx_skb *tx_skb;
570
571 spinlock_t lock;
572 struct platform_device *pdev;
573 struct clk *pclk;
574 struct clk *hclk;
575 struct clk *tx_clk;
576 struct net_device *dev;
577 struct napi_struct napi;
578 struct work_struct tx_error_task;
579 struct net_device_stats stats;
580 union {
581 struct macb_stats macb;
582 struct gem_stats gem;
583 } hw_stats;
584
585 dma_addr_t rx_ring_dma;
586 dma_addr_t tx_ring_dma;
587 dma_addr_t rx_buffers_dma;
588
589 struct macb_or_gem_ops macbgem_ops;
590
591 struct mii_bus *mii_bus;
592 struct phy_device *phy_dev;
593 unsigned int link;
594 unsigned int speed;
595 unsigned int duplex;
596
597 u32 caps;
598
599 phy_interface_t phy_interface;
600
601 /* AT91RM9200 transmit */
602 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
603 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
604 int skb_length; /* saved skb length for pci_unmap_single */
605};
606
607extern const struct ethtool_ops macb_ethtool_ops;
608
609int macb_mii_init(struct macb *bp);
610int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
611struct net_device_stats *macb_get_stats(struct net_device *dev);
612void macb_set_rx_mode(struct net_device *dev);
613void macb_set_hwaddr(struct macb *bp);
614void macb_get_hwaddr(struct macb *bp);
615
616static inline bool macb_is_gem(struct macb *bp)
617{
618 return MACB_BFEXT(IDNUM, macb_readl(bp, MID)) == 0x2;
619}
620
621#endif /* _MACB_H */