1/*
  2 * Marvell EBU SoC Device Bus Controller
  3 * (memory controller for NOR/NAND/SRAM/FPGA devices)
  4 *
  5 * Copyright (C) 2013 Marvell
  6 *
  7 * This program is free software: you can redistribute it and/or modify
  8 * it under the terms of the GNU General Public License as published by
  9 * the Free Software Foundation version 2 of the License.
 10 *
 11 * This program is distributed in the hope that it will be useful,
 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 14 * GNU General Public License for more details.
 15 *
 16 * You should have received a copy of the GNU General Public License
 17 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 18 *
 19 */
 20
 21#include <linux/kernel.h>
 22#include <linux/module.h>
 23#include <linux/slab.h>
 24#include <linux/err.h>
 25#include <linux/io.h>
 26#include <linux/clk.h>
 27#include <linux/mbus.h>
 28#include <linux/of_platform.h>
 29#include <linux/of_address.h>
 30#include <linux/platform_device.h>
 31
 32/* Register definitions */
 33#define DEV_WIDTH_BIT		30
 34#define BADR_SKEW_BIT		28
 35#define RD_HOLD_BIT		23
 36#define ACC_NEXT_BIT		17
 37#define RD_SETUP_BIT		12
 38#define ACC_FIRST_BIT		6
 39
 40#define SYNC_ENABLE_BIT		24
 41#define WR_HIGH_BIT		16
 42#define WR_LOW_BIT		8
 43
 44#define READ_PARAM_OFFSET	0x0
 45#define WRITE_PARAM_OFFSET	0x4
 46
 47struct devbus_read_params {
 48	u32 bus_width;
 49	u32 badr_skew;
 50	u32 turn_off;
 51	u32 acc_first;
 52	u32 acc_next;
 53	u32 rd_setup;
 54	u32 rd_hold;
 55};
 56
 57struct devbus_write_params {
 58	u32 sync_enable;
 59	u32 wr_high;
 60	u32 wr_low;
 61	u32 ale_wr;
 62};
 63
 64struct devbus {
 65	struct device *dev;
 66	void __iomem *base;
 67	unsigned long tick_ps;
 68};
 69
 70static int get_timing_param_ps(struct devbus *devbus,
 71			       struct device_node *node,
 72			       const char *name,
 73			       u32 *ticks)
 74{
 75	u32 time_ps;
 76	int err;
 77
 78	err = of_property_read_u32(node, name, &time_ps);
 79	if (err < 0) {
 80		dev_err(devbus->dev, "%s has no '%s' property\n",
 81			name, node->full_name);
 82		return err;
 83	}
 84
 85	*ticks = (time_ps + devbus->tick_ps - 1) / devbus->tick_ps;
 86
 87	dev_dbg(devbus->dev, "%s: %u ps -> 0x%x\n",
 88		name, time_ps, *ticks);
 89	return 0;
 90}
 91
 92static int devbus_set_timing_params(struct devbus *devbus,
 93				    struct device_node *node)
 94{
 95	struct devbus_read_params r;
 96	struct devbus_write_params w;
 97	u32 value;
 98	int err;
 99
100	dev_dbg(devbus->dev, "Setting timing parameter, tick is %lu ps\n",
101		devbus->tick_ps);
102
103	/* Get read timings */
104	err = of_property_read_u32(node, "devbus,bus-width", &r.bus_width);
105	if (err < 0) {
106		dev_err(devbus->dev,
107			"%s has no 'devbus,bus-width' property\n",
108			node->full_name);
109		return err;
110	}
111
112	/*
113	 * The bus width is encoded into the register as 0 for 8 bits,
114	 * and 1 for 16 bits, so we do the necessary conversion here.
115	 */
116	if (r.bus_width == 8)
117		r.bus_width = 0;
118	else if (r.bus_width == 16)
119		r.bus_width = 1;
120	else {
121		dev_err(devbus->dev, "invalid bus width %d\n", r.bus_width);
122		return -EINVAL;
123	}
124
125	err = get_timing_param_ps(devbus, node, "devbus,badr-skew-ps",
126				 &r.badr_skew);
127	if (err < 0)
128		return err;
129
130	err = get_timing_param_ps(devbus, node, "devbus,turn-off-ps",
131				 &r.turn_off);
132	if (err < 0)
133		return err;
134
135	err = get_timing_param_ps(devbus, node, "devbus,acc-first-ps",
136				 &r.acc_first);
137	if (err < 0)
138		return err;
139
140	err = get_timing_param_ps(devbus, node, "devbus,acc-next-ps",
141				 &r.acc_next);
142	if (err < 0)
143		return err;
144
145	err = get_timing_param_ps(devbus, node, "devbus,rd-setup-ps",
146				 &r.rd_setup);
147	if (err < 0)
148		return err;
149
150	err = get_timing_param_ps(devbus, node, "devbus,rd-hold-ps",
151				 &r.rd_hold);
152	if (err < 0)
153		return err;
154
155	/* Get write timings */
156	err = of_property_read_u32(node, "devbus,sync-enable",
157				  &w.sync_enable);
158	if (err < 0) {
159		dev_err(devbus->dev,
160			"%s has no 'devbus,sync-enable' property\n",
161			node->full_name);
162		return err;
163	}
164
165	err = get_timing_param_ps(devbus, node, "devbus,ale-wr-ps",
166				 &w.ale_wr);
167	if (err < 0)
168		return err;
169
170	err = get_timing_param_ps(devbus, node, "devbus,wr-low-ps",
171				 &w.wr_low);
172	if (err < 0)
173		return err;
174
175	err = get_timing_param_ps(devbus, node, "devbus,wr-high-ps",
176				 &w.wr_high);
177	if (err < 0)
178		return err;
179
180	/* Set read timings */
181	value = r.bus_width << DEV_WIDTH_BIT |
182		r.badr_skew << BADR_SKEW_BIT |
183		r.rd_hold   << RD_HOLD_BIT   |
184		r.acc_next  << ACC_NEXT_BIT  |
185		r.rd_setup  << RD_SETUP_BIT  |
186		r.acc_first << ACC_FIRST_BIT |
187		r.turn_off;
188
189	dev_dbg(devbus->dev, "read parameters register 0x%p = 0x%x\n",
190		devbus->base + READ_PARAM_OFFSET,
191		value);
192
193	writel(value, devbus->base + READ_PARAM_OFFSET);
194
195	/* Set write timings */
196	value = w.sync_enable  << SYNC_ENABLE_BIT |
197		w.wr_low       << WR_LOW_BIT      |
198		w.wr_high      << WR_HIGH_BIT     |
199		w.ale_wr;
200
201	dev_dbg(devbus->dev, "write parameters register: 0x%p = 0x%x\n",
202		devbus->base + WRITE_PARAM_OFFSET,
203		value);
204
205	writel(value, devbus->base + WRITE_PARAM_OFFSET);
206
207	return 0;
208}
209
210static int mvebu_devbus_probe(struct platform_device *pdev)
211{
212	struct device *dev = &pdev->dev;
213	struct device_node *node = pdev->dev.of_node;
214	struct devbus *devbus;
215	struct resource *res;
216	struct clk *clk;
217	unsigned long rate;
218	int err;
219
220	devbus = devm_kzalloc(&pdev->dev, sizeof(struct devbus), GFP_KERNEL);
221	if (!devbus)
222		return -ENOMEM;
223
224	devbus->dev = dev;
225	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
226	devbus->base = devm_ioremap_resource(&pdev->dev, res);
227	if (IS_ERR(devbus->base))
228		return PTR_ERR(devbus->base);
229
230	clk = devm_clk_get(&pdev->dev, NULL);
231	if (IS_ERR(clk))
232		return PTR_ERR(clk);
233	clk_prepare_enable(clk);
234
235	/*
236	 * Obtain clock period in picoseconds,
237	 * we need this in order to convert timing
238	 * parameters from cycles to picoseconds.
239	 */
240	rate = clk_get_rate(clk) / 1000;
241	devbus->tick_ps = 1000000000 / rate;
242
243	/* Read the device tree node and set the new timing parameters */
244	err = devbus_set_timing_params(devbus, node);
245	if (err < 0)
246		return err;
247
248	/*
249	 * We need to create a child device explicitly from here to
250	 * guarantee that the child will be probed after the timing
251	 * parameters for the bus are written.
252	 */
253	err = of_platform_populate(node, NULL, NULL, dev);
254	if (err < 0)
255		return err;
256
257	return 0;
258}
259
260static const struct of_device_id mvebu_devbus_of_match[] = {
261	{ .compatible = "marvell,mvebu-devbus" },
262	{},
263};
264MODULE_DEVICE_TABLE(of, mvebu_devbus_of_match);
265
266static struct platform_driver mvebu_devbus_driver = {
267	.probe		= mvebu_devbus_probe,
268	.driver		= {
269		.name	= "mvebu-devbus",
270		.owner	= THIS_MODULE,
271		.of_match_table = mvebu_devbus_of_match,
272	},
273};
274
275static int __init mvebu_devbus_init(void)
276{
277	return platform_driver_register(&mvebu_devbus_driver);
278}
279module_init(mvebu_devbus_init);
280
281MODULE_LICENSE("GPL v2");
282MODULE_AUTHOR("Ezequiel Garcia <ezequiel.garcia@free-electrons.com>");
283MODULE_DESCRIPTION("Marvell EBU SoC Device Bus controller");