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1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
39#include <linux/io.h>
40#include <linux/slab.h>
41#include <linux/i2c-omap.h>
42#include <linux/pm_runtime.h>
43
44/* I2C controller revisions */
45#define OMAP_I2C_REV_2 0x20
46
47/* I2C controller revisions present on specific hardware */
48#define OMAP_I2C_REV_ON_2430 0x36
49#define OMAP_I2C_REV_ON_3430 0x3C
50#define OMAP_I2C_REV_ON_4430 0x40
51
52/* timeout waiting for the controller to respond */
53#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
54
55/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
56enum {
57 OMAP_I2C_REV_REG = 0,
58 OMAP_I2C_IE_REG,
59 OMAP_I2C_STAT_REG,
60 OMAP_I2C_IV_REG,
61 OMAP_I2C_WE_REG,
62 OMAP_I2C_SYSS_REG,
63 OMAP_I2C_BUF_REG,
64 OMAP_I2C_CNT_REG,
65 OMAP_I2C_DATA_REG,
66 OMAP_I2C_SYSC_REG,
67 OMAP_I2C_CON_REG,
68 OMAP_I2C_OA_REG,
69 OMAP_I2C_SA_REG,
70 OMAP_I2C_PSC_REG,
71 OMAP_I2C_SCLL_REG,
72 OMAP_I2C_SCLH_REG,
73 OMAP_I2C_SYSTEST_REG,
74 OMAP_I2C_BUFSTAT_REG,
75 OMAP_I2C_REVNB_LO,
76 OMAP_I2C_REVNB_HI,
77 OMAP_I2C_IRQSTATUS_RAW,
78 OMAP_I2C_IRQENABLE_SET,
79 OMAP_I2C_IRQENABLE_CLR,
80};
81
82/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
83#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
84#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
85#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
86#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
87#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
88#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
89#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
90
91/* I2C Status Register (OMAP_I2C_STAT): */
92#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
93#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
94#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
95#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
96#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
97#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
98#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
99#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
100#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
101#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
102#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
103#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
104
105/* I2C WE wakeup enable register */
106#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
107#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
108#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
109#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
110#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
111#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
112#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
113#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
114#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
115#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
116
117#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
118 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
119 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
120 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
121 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
122
123/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
124#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
125#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
126#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
127#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
128
129/* I2C Configuration Register (OMAP_I2C_CON): */
130#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
131#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
132#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
133#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
134#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
135#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
136#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
137#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
138#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
139#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
140
141/* I2C SCL time value when Master */
142#define OMAP_I2C_SCLL_HSSCLL 8
143#define OMAP_I2C_SCLH_HSSCLH 8
144
145/* I2C System Test Register (OMAP_I2C_SYSTEST): */
146#ifdef DEBUG
147#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
148#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
149#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
150#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
151#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
152#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
153#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
154#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
155#endif
156
157/* OCP_SYSSTATUS bit definitions */
158#define SYSS_RESETDONE_MASK (1 << 0)
159
160/* OCP_SYSCONFIG bit definitions */
161#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
162#define SYSC_SIDLEMODE_MASK (0x3 << 3)
163#define SYSC_ENAWAKEUP_MASK (1 << 2)
164#define SYSC_SOFTRESET_MASK (1 << 1)
165#define SYSC_AUTOIDLE_MASK (1 << 0)
166
167#define SYSC_IDLEMODE_SMART 0x2
168#define SYSC_CLOCKACTIVITY_FCLK 0x2
169
170/* Errata definitions */
171#define I2C_OMAP_ERRATA_I207 (1 << 0)
172#define I2C_OMAP3_1P153 (1 << 1)
173
174struct omap_i2c_dev {
175 struct device *dev;
176 void __iomem *base; /* virtual */
177 int irq;
178 int reg_shift; /* bit shift for I2C register addresses */
179 struct completion cmd_complete;
180 struct resource *ioarea;
181 u32 latency; /* maximum mpu wkup latency */
182 void (*set_mpu_wkup_lat)(struct device *dev,
183 long latency);
184 u32 speed; /* Speed of bus in Khz */
185 u16 cmd_err;
186 u8 *buf;
187 u8 *regs;
188 size_t buf_len;
189 struct i2c_adapter adapter;
190 u8 fifo_size; /* use as flag and value
191 * fifo_size==0 implies no fifo
192 * if set, should be trsh+1
193 */
194 u8 rev;
195 unsigned b_hw:1; /* bad h/w fixes */
196 unsigned idle:1;
197 u16 iestate; /* Saved interrupt register */
198 u16 pscstate;
199 u16 scllstate;
200 u16 sclhstate;
201 u16 bufstate;
202 u16 syscstate;
203 u16 westate;
204 u16 errata;
205};
206
207static const u8 reg_map[] = {
208 [OMAP_I2C_REV_REG] = 0x00,
209 [OMAP_I2C_IE_REG] = 0x01,
210 [OMAP_I2C_STAT_REG] = 0x02,
211 [OMAP_I2C_IV_REG] = 0x03,
212 [OMAP_I2C_WE_REG] = 0x03,
213 [OMAP_I2C_SYSS_REG] = 0x04,
214 [OMAP_I2C_BUF_REG] = 0x05,
215 [OMAP_I2C_CNT_REG] = 0x06,
216 [OMAP_I2C_DATA_REG] = 0x07,
217 [OMAP_I2C_SYSC_REG] = 0x08,
218 [OMAP_I2C_CON_REG] = 0x09,
219 [OMAP_I2C_OA_REG] = 0x0a,
220 [OMAP_I2C_SA_REG] = 0x0b,
221 [OMAP_I2C_PSC_REG] = 0x0c,
222 [OMAP_I2C_SCLL_REG] = 0x0d,
223 [OMAP_I2C_SCLH_REG] = 0x0e,
224 [OMAP_I2C_SYSTEST_REG] = 0x0f,
225 [OMAP_I2C_BUFSTAT_REG] = 0x10,
226};
227
228static const u8 omap4_reg_map[] = {
229 [OMAP_I2C_REV_REG] = 0x04,
230 [OMAP_I2C_IE_REG] = 0x2c,
231 [OMAP_I2C_STAT_REG] = 0x28,
232 [OMAP_I2C_IV_REG] = 0x34,
233 [OMAP_I2C_WE_REG] = 0x34,
234 [OMAP_I2C_SYSS_REG] = 0x90,
235 [OMAP_I2C_BUF_REG] = 0x94,
236 [OMAP_I2C_CNT_REG] = 0x98,
237 [OMAP_I2C_DATA_REG] = 0x9c,
238 [OMAP_I2C_SYSC_REG] = 0x20,
239 [OMAP_I2C_CON_REG] = 0xa4,
240 [OMAP_I2C_OA_REG] = 0xa8,
241 [OMAP_I2C_SA_REG] = 0xac,
242 [OMAP_I2C_PSC_REG] = 0xb0,
243 [OMAP_I2C_SCLL_REG] = 0xb4,
244 [OMAP_I2C_SCLH_REG] = 0xb8,
245 [OMAP_I2C_SYSTEST_REG] = 0xbC,
246 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
247 [OMAP_I2C_REVNB_LO] = 0x00,
248 [OMAP_I2C_REVNB_HI] = 0x04,
249 [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
250 [OMAP_I2C_IRQENABLE_SET] = 0x2c,
251 [OMAP_I2C_IRQENABLE_CLR] = 0x30,
252};
253
254static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
255 int reg, u16 val)
256{
257 __raw_writew(val, i2c_dev->base +
258 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
259}
260
261static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
262{
263 return __raw_readw(i2c_dev->base +
264 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
265}
266
267static void omap_i2c_unidle(struct omap_i2c_dev *dev)
268{
269 struct platform_device *pdev;
270 struct omap_i2c_bus_platform_data *pdata;
271
272 WARN_ON(!dev->idle);
273
274 pdev = to_platform_device(dev->dev);
275 pdata = pdev->dev.platform_data;
276
277 pm_runtime_get_sync(&pdev->dev);
278
279 if (cpu_is_omap34xx()) {
280 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
281 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
282 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
287 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
288 }
289 dev->idle = 0;
290
291 /*
292 * Don't write to this register if the IE state is 0 as it can
293 * cause deadlock.
294 */
295 if (dev->iestate)
296 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
297}
298
299static void omap_i2c_idle(struct omap_i2c_dev *dev)
300{
301 struct platform_device *pdev;
302 struct omap_i2c_bus_platform_data *pdata;
303 u16 iv;
304
305 WARN_ON(dev->idle);
306
307 pdev = to_platform_device(dev->dev);
308 pdata = pdev->dev.platform_data;
309
310 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
311 if (dev->rev >= OMAP_I2C_REV_ON_4430)
312 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
313 else
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
315
316 if (dev->rev < OMAP_I2C_REV_2) {
317 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
318 } else {
319 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
320
321 /* Flush posted write before the dev->idle store occurs */
322 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
323 }
324 dev->idle = 1;
325
326 pm_runtime_put_sync(&pdev->dev);
327}
328
329static int omap_i2c_init(struct omap_i2c_dev *dev)
330{
331 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
332 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
333 unsigned long fclk_rate = 12000000;
334 unsigned long timeout;
335 unsigned long internal_clk = 0;
336 struct clk *fclk;
337
338 if (dev->rev >= OMAP_I2C_REV_2) {
339 /* Disable I2C controller before soft reset */
340 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
341 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
342 ~(OMAP_I2C_CON_EN));
343
344 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
345 /* For some reason we need to set the EN bit before the
346 * reset done bit gets set. */
347 timeout = jiffies + OMAP_I2C_TIMEOUT;
348 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
349 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
350 SYSS_RESETDONE_MASK)) {
351 if (time_after(jiffies, timeout)) {
352 dev_warn(dev->dev, "timeout waiting "
353 "for controller reset\n");
354 return -ETIMEDOUT;
355 }
356 msleep(1);
357 }
358
359 /* SYSC register is cleared by the reset; rewrite it */
360 if (dev->rev == OMAP_I2C_REV_ON_2430) {
361
362 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
363 SYSC_AUTOIDLE_MASK);
364
365 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
366 dev->syscstate = SYSC_AUTOIDLE_MASK;
367 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
368 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
369 __ffs(SYSC_SIDLEMODE_MASK));
370 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
371 __ffs(SYSC_CLOCKACTIVITY_MASK));
372
373 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
374 dev->syscstate);
375 /*
376 * Enabling all wakup sources to stop I2C freezing on
377 * WFI instruction.
378 * REVISIT: Some wkup sources might not be needed.
379 */
380 dev->westate = OMAP_I2C_WE_ALL;
381 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
382 }
383 }
384 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
385
386 if (cpu_class_is_omap1()) {
387 /*
388 * The I2C functional clock is the armxor_ck, so there's
389 * no need to get "armxor_ck" separately. Now, if OMAP2420
390 * always returns 12MHz for the functional clock, we can
391 * do this bit unconditionally.
392 */
393 fclk = clk_get(dev->dev, "fck");
394 fclk_rate = clk_get_rate(fclk);
395 clk_put(fclk);
396
397 /* TRM for 5912 says the I2C clock must be prescaled to be
398 * between 7 - 12 MHz. The XOR input clock is typically
399 * 12, 13 or 19.2 MHz. So we should have code that produces:
400 *
401 * XOR MHz Divider Prescaler
402 * 12 1 0
403 * 13 2 1
404 * 19.2 2 1
405 */
406 if (fclk_rate > 12000000)
407 psc = fclk_rate / 12000000;
408 }
409
410 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
411
412 /*
413 * HSI2C controller internal clk rate should be 19.2 Mhz for
414 * HS and for all modes on 2430. On 34xx we can use lower rate
415 * to get longer filter period for better noise suppression.
416 * The filter is iclk (fclk for HS) period.
417 */
418 if (dev->speed > 400 || cpu_is_omap2430())
419 internal_clk = 19200;
420 else if (dev->speed > 100)
421 internal_clk = 9600;
422 else
423 internal_clk = 4000;
424 fclk = clk_get(dev->dev, "fck");
425 fclk_rate = clk_get_rate(fclk) / 1000;
426 clk_put(fclk);
427
428 /* Compute prescaler divisor */
429 psc = fclk_rate / internal_clk;
430 psc = psc - 1;
431
432 /* If configured for High Speed */
433 if (dev->speed > 400) {
434 unsigned long scl;
435
436 /* For first phase of HS mode */
437 scl = internal_clk / 400;
438 fsscll = scl - (scl / 3) - 7;
439 fssclh = (scl / 3) - 5;
440
441 /* For second phase of HS mode */
442 scl = fclk_rate / dev->speed;
443 hsscll = scl - (scl / 3) - 7;
444 hssclh = (scl / 3) - 5;
445 } else if (dev->speed > 100) {
446 unsigned long scl;
447
448 /* Fast mode */
449 scl = internal_clk / dev->speed;
450 fsscll = scl - (scl / 3) - 7;
451 fssclh = (scl / 3) - 5;
452 } else {
453 /* Standard mode */
454 fsscll = internal_clk / (dev->speed * 2) - 7;
455 fssclh = internal_clk / (dev->speed * 2) - 5;
456 }
457 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
458 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
459 } else {
460 /* Program desired operating rate */
461 fclk_rate /= (psc + 1) * 1000;
462 if (psc > 2)
463 psc = 2;
464 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
465 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
466 }
467
468 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
469 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
470
471 /* SCL low and high time values */
472 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
473 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
474
475 if (dev->fifo_size) {
476 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
477 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
478 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
479 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
480 }
481
482 /* Take the I2C module out of reset: */
483 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
484
485 dev->errata = 0;
486
487 if (cpu_is_omap2430() || cpu_is_omap34xx())
488 dev->errata |= I2C_OMAP_ERRATA_I207;
489
490 /* Enable interrupts */
491 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
492 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
493 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
494 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
495 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
496 if (cpu_is_omap34xx()) {
497 dev->pscstate = psc;
498 dev->scllstate = scll;
499 dev->sclhstate = sclh;
500 dev->bufstate = buf;
501 }
502 return 0;
503}
504
505/*
506 * Waiting on Bus Busy
507 */
508static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
509{
510 unsigned long timeout;
511
512 timeout = jiffies + OMAP_I2C_TIMEOUT;
513 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
514 if (time_after(jiffies, timeout)) {
515 dev_warn(dev->dev, "timeout waiting for bus ready\n");
516 return -ETIMEDOUT;
517 }
518 msleep(1);
519 }
520
521 return 0;
522}
523
524/*
525 * Low level master read/write transaction.
526 */
527static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
528 struct i2c_msg *msg, int stop)
529{
530 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
531 int r;
532 u16 w;
533
534 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
535 msg->addr, msg->len, msg->flags, stop);
536
537 if (msg->len == 0)
538 return -EINVAL;
539
540 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
541
542 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
543 dev->buf = msg->buf;
544 dev->buf_len = msg->len;
545
546 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
547
548 /* Clear the FIFO Buffers */
549 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
550 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
551 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
552
553 init_completion(&dev->cmd_complete);
554 dev->cmd_err = 0;
555
556 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
557
558 /* High speed configuration */
559 if (dev->speed > 400)
560 w |= OMAP_I2C_CON_OPMODE_HS;
561
562 if (msg->flags & I2C_M_TEN)
563 w |= OMAP_I2C_CON_XA;
564 if (!(msg->flags & I2C_M_RD))
565 w |= OMAP_I2C_CON_TRX;
566
567 if (!dev->b_hw && stop)
568 w |= OMAP_I2C_CON_STP;
569
570 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
571
572 /*
573 * Don't write stt and stp together on some hardware.
574 */
575 if (dev->b_hw && stop) {
576 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
577 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
578 while (con & OMAP_I2C_CON_STT) {
579 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
580
581 /* Let the user know if i2c is in a bad state */
582 if (time_after(jiffies, delay)) {
583 dev_err(dev->dev, "controller timed out "
584 "waiting for start condition to finish\n");
585 return -ETIMEDOUT;
586 }
587 cpu_relax();
588 }
589
590 w |= OMAP_I2C_CON_STP;
591 w &= ~OMAP_I2C_CON_STT;
592 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
593 }
594
595 /*
596 * REVISIT: We should abort the transfer on signals, but the bus goes
597 * into arbitration and we're currently unable to recover from it.
598 */
599 r = wait_for_completion_timeout(&dev->cmd_complete,
600 OMAP_I2C_TIMEOUT);
601 dev->buf_len = 0;
602 if (r < 0)
603 return r;
604 if (r == 0) {
605 dev_err(dev->dev, "controller timed out\n");
606 omap_i2c_init(dev);
607 return -ETIMEDOUT;
608 }
609
610 if (likely(!dev->cmd_err))
611 return 0;
612
613 /* We have an error */
614 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
615 OMAP_I2C_STAT_XUDF)) {
616 omap_i2c_init(dev);
617 return -EIO;
618 }
619
620 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
621 if (msg->flags & I2C_M_IGNORE_NAK)
622 return 0;
623 if (stop) {
624 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
625 w |= OMAP_I2C_CON_STP;
626 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
627 }
628 return -EREMOTEIO;
629 }
630 return -EIO;
631}
632
633
634/*
635 * Prepare controller for a transaction and call omap_i2c_xfer_msg
636 * to do the work during IRQ processing.
637 */
638static int
639omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
640{
641 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
642 int i;
643 int r;
644
645 omap_i2c_unidle(dev);
646
647 r = omap_i2c_wait_for_bb(dev);
648 if (r < 0)
649 goto out;
650
651 if (dev->set_mpu_wkup_lat != NULL)
652 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
653
654 for (i = 0; i < num; i++) {
655 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
656 if (r != 0)
657 break;
658 }
659
660 if (dev->set_mpu_wkup_lat != NULL)
661 dev->set_mpu_wkup_lat(dev->dev, -1);
662
663 if (r == 0)
664 r = num;
665
666 omap_i2c_wait_for_bb(dev);
667out:
668 omap_i2c_idle(dev);
669 return r;
670}
671
672static u32
673omap_i2c_func(struct i2c_adapter *adap)
674{
675 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
676}
677
678static inline void
679omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
680{
681 dev->cmd_err |= err;
682 complete(&dev->cmd_complete);
683}
684
685static inline void
686omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
687{
688 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
689}
690
691static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
692{
693 /*
694 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
695 * Not applicable for OMAP4.
696 * Under certain rare conditions, RDR could be set again
697 * when the bus is busy, then ignore the interrupt and
698 * clear the interrupt.
699 */
700 if (stat & OMAP_I2C_STAT_RDR) {
701 /* Step 1: If RDR is set, clear it */
702 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
703
704 /* Step 2: */
705 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
706 & OMAP_I2C_STAT_BB)) {
707
708 /* Step 3: */
709 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
710 & OMAP_I2C_STAT_RDR) {
711 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
712 dev_dbg(dev->dev, "RDR when bus is busy.\n");
713 }
714
715 }
716 }
717}
718
719/* rev1 devices are apparently only on some 15xx */
720#ifdef CONFIG_ARCH_OMAP15XX
721
722static irqreturn_t
723omap_i2c_rev1_isr(int this_irq, void *dev_id)
724{
725 struct omap_i2c_dev *dev = dev_id;
726 u16 iv, w;
727
728 if (dev->idle)
729 return IRQ_NONE;
730
731 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
732 switch (iv) {
733 case 0x00: /* None */
734 break;
735 case 0x01: /* Arbitration lost */
736 dev_err(dev->dev, "Arbitration lost\n");
737 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
738 break;
739 case 0x02: /* No acknowledgement */
740 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
741 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
742 break;
743 case 0x03: /* Register access ready */
744 omap_i2c_complete_cmd(dev, 0);
745 break;
746 case 0x04: /* Receive data ready */
747 if (dev->buf_len) {
748 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
749 *dev->buf++ = w;
750 dev->buf_len--;
751 if (dev->buf_len) {
752 *dev->buf++ = w >> 8;
753 dev->buf_len--;
754 }
755 } else
756 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
757 break;
758 case 0x05: /* Transmit data ready */
759 if (dev->buf_len) {
760 w = *dev->buf++;
761 dev->buf_len--;
762 if (dev->buf_len) {
763 w |= *dev->buf++ << 8;
764 dev->buf_len--;
765 }
766 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
767 } else
768 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
769 break;
770 default:
771 return IRQ_NONE;
772 }
773
774 return IRQ_HANDLED;
775}
776#else
777#define omap_i2c_rev1_isr NULL
778#endif
779
780/*
781 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
782 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
783 * them from the memory to the I2C interface.
784 */
785static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
786{
787 unsigned long timeout = 10000;
788
789 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
790 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
791 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
792 OMAP_I2C_STAT_XDR));
793 *err |= OMAP_I2C_STAT_XUDF;
794 return -ETIMEDOUT;
795 }
796
797 cpu_relax();
798 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
799 }
800
801 if (!timeout) {
802 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
803 return 0;
804 }
805
806 return 0;
807}
808
809static irqreturn_t
810omap_i2c_isr(int this_irq, void *dev_id)
811{
812 struct omap_i2c_dev *dev = dev_id;
813 u16 bits;
814 u16 stat, w;
815 int err, count = 0;
816
817 if (dev->idle)
818 return IRQ_NONE;
819
820 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
821 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
822 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
823 if (count++ == 100) {
824 dev_warn(dev->dev, "Too much work in one IRQ\n");
825 break;
826 }
827
828 err = 0;
829complete:
830 /*
831 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
832 * acked after the data operation is complete.
833 * Ref: TRM SWPU114Q Figure 18-31
834 */
835 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
836 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
837 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
838
839 if (stat & OMAP_I2C_STAT_NACK) {
840 err |= OMAP_I2C_STAT_NACK;
841 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
842 OMAP_I2C_CON_STP);
843 }
844 if (stat & OMAP_I2C_STAT_AL) {
845 dev_err(dev->dev, "Arbitration lost\n");
846 err |= OMAP_I2C_STAT_AL;
847 }
848 /*
849 * ProDB0017052: Clear ARDY bit twice
850 */
851 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
852 OMAP_I2C_STAT_AL)) {
853 omap_i2c_ack_stat(dev, stat &
854 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
855 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
856 OMAP_I2C_STAT_ARDY));
857 omap_i2c_complete_cmd(dev, err);
858 return IRQ_HANDLED;
859 }
860 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
861 u8 num_bytes = 1;
862
863 if (dev->errata & I2C_OMAP_ERRATA_I207)
864 i2c_omap_errata_i207(dev, stat);
865
866 if (dev->fifo_size) {
867 if (stat & OMAP_I2C_STAT_RRDY)
868 num_bytes = dev->fifo_size;
869 else /* read RXSTAT on RDR interrupt */
870 num_bytes = (omap_i2c_read_reg(dev,
871 OMAP_I2C_BUFSTAT_REG)
872 >> 8) & 0x3F;
873 }
874 while (num_bytes) {
875 num_bytes--;
876 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
877 if (dev->buf_len) {
878 *dev->buf++ = w;
879 dev->buf_len--;
880 /*
881 * Data reg in 2430, omap3 and
882 * omap4 is 8 bit wide
883 */
884 if (cpu_class_is_omap1() ||
885 cpu_is_omap2420()) {
886 if (dev->buf_len) {
887 *dev->buf++ = w >> 8;
888 dev->buf_len--;
889 }
890 }
891 } else {
892 if (stat & OMAP_I2C_STAT_RRDY)
893 dev_err(dev->dev,
894 "RRDY IRQ while no data"
895 " requested\n");
896 if (stat & OMAP_I2C_STAT_RDR)
897 dev_err(dev->dev,
898 "RDR IRQ while no data"
899 " requested\n");
900 break;
901 }
902 }
903 omap_i2c_ack_stat(dev,
904 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
905 continue;
906 }
907 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
908 u8 num_bytes = 1;
909 if (dev->fifo_size) {
910 if (stat & OMAP_I2C_STAT_XRDY)
911 num_bytes = dev->fifo_size;
912 else /* read TXSTAT on XDR interrupt */
913 num_bytes = omap_i2c_read_reg(dev,
914 OMAP_I2C_BUFSTAT_REG)
915 & 0x3F;
916 }
917 while (num_bytes) {
918 num_bytes--;
919 w = 0;
920 if (dev->buf_len) {
921 w = *dev->buf++;
922 dev->buf_len--;
923 /*
924 * Data reg in 2430, omap3 and
925 * omap4 is 8 bit wide
926 */
927 if (cpu_class_is_omap1() ||
928 cpu_is_omap2420()) {
929 if (dev->buf_len) {
930 w |= *dev->buf++ << 8;
931 dev->buf_len--;
932 }
933 }
934 } else {
935 if (stat & OMAP_I2C_STAT_XRDY)
936 dev_err(dev->dev,
937 "XRDY IRQ while no "
938 "data to send\n");
939 if (stat & OMAP_I2C_STAT_XDR)
940 dev_err(dev->dev,
941 "XDR IRQ while no "
942 "data to send\n");
943 break;
944 }
945
946 if ((dev->errata & I2C_OMAP3_1P153) &&
947 errata_omap3_1p153(dev, &stat, &err))
948 goto complete;
949
950 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
951 }
952 omap_i2c_ack_stat(dev,
953 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
954 continue;
955 }
956 if (stat & OMAP_I2C_STAT_ROVR) {
957 dev_err(dev->dev, "Receive overrun\n");
958 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
959 }
960 if (stat & OMAP_I2C_STAT_XUDF) {
961 dev_err(dev->dev, "Transmit underflow\n");
962 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
963 }
964 }
965
966 return count ? IRQ_HANDLED : IRQ_NONE;
967}
968
969static const struct i2c_algorithm omap_i2c_algo = {
970 .master_xfer = omap_i2c_xfer,
971 .functionality = omap_i2c_func,
972};
973
974static int __devinit
975omap_i2c_probe(struct platform_device *pdev)
976{
977 struct omap_i2c_dev *dev;
978 struct i2c_adapter *adap;
979 struct resource *mem, *irq, *ioarea;
980 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
981 irq_handler_t isr;
982 int r;
983 u32 speed = 0;
984
985 /* NOTE: driver uses the static register mapping */
986 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
987 if (!mem) {
988 dev_err(&pdev->dev, "no mem resource?\n");
989 return -ENODEV;
990 }
991 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
992 if (!irq) {
993 dev_err(&pdev->dev, "no irq resource?\n");
994 return -ENODEV;
995 }
996
997 ioarea = request_mem_region(mem->start, resource_size(mem),
998 pdev->name);
999 if (!ioarea) {
1000 dev_err(&pdev->dev, "I2C region already claimed\n");
1001 return -EBUSY;
1002 }
1003
1004 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1005 if (!dev) {
1006 r = -ENOMEM;
1007 goto err_release_region;
1008 }
1009
1010 if (pdata != NULL) {
1011 speed = pdata->clkrate;
1012 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1013 } else {
1014 speed = 100; /* Default speed */
1015 dev->set_mpu_wkup_lat = NULL;
1016 }
1017
1018 dev->speed = speed;
1019 dev->idle = 1;
1020 dev->dev = &pdev->dev;
1021 dev->irq = irq->start;
1022 dev->base = ioremap(mem->start, resource_size(mem));
1023 if (!dev->base) {
1024 r = -ENOMEM;
1025 goto err_free_mem;
1026 }
1027
1028 platform_set_drvdata(pdev, dev);
1029
1030 if (cpu_is_omap7xx())
1031 dev->reg_shift = 1;
1032 else if (cpu_is_omap44xx())
1033 dev->reg_shift = 0;
1034 else
1035 dev->reg_shift = 2;
1036
1037 if (cpu_is_omap44xx())
1038 dev->regs = (u8 *) omap4_reg_map;
1039 else
1040 dev->regs = (u8 *) reg_map;
1041
1042 pm_runtime_enable(&pdev->dev);
1043 omap_i2c_unidle(dev);
1044
1045 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1046
1047 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1048 dev->errata |= I2C_OMAP3_1P153;
1049
1050 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1051 u16 s;
1052
1053 /* Set up the fifo size - Get total size */
1054 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1055 dev->fifo_size = 0x8 << s;
1056
1057 /*
1058 * Set up notification threshold as half the total available
1059 * size. This is to ensure that we can handle the status on int
1060 * call back latencies.
1061 */
1062 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1063 dev->fifo_size = 0;
1064 dev->b_hw = 0; /* Disable hardware fixes */
1065 } else {
1066 dev->fifo_size = (dev->fifo_size / 2);
1067 dev->b_hw = 1; /* Enable hardware fixes */
1068 }
1069 /* calculate wakeup latency constraint for MPU */
1070 if (dev->set_mpu_wkup_lat != NULL)
1071 dev->latency = (1000000 * dev->fifo_size) /
1072 (1000 * speed / 8);
1073 }
1074
1075 /* reset ASAP, clearing any IRQs */
1076 omap_i2c_init(dev);
1077
1078 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1079 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1080
1081 if (r) {
1082 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1083 goto err_unuse_clocks;
1084 }
1085
1086 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1087 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1088
1089 omap_i2c_idle(dev);
1090
1091 adap = &dev->adapter;
1092 i2c_set_adapdata(adap, dev);
1093 adap->owner = THIS_MODULE;
1094 adap->class = I2C_CLASS_HWMON;
1095 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1096 adap->algo = &omap_i2c_algo;
1097 adap->dev.parent = &pdev->dev;
1098
1099 /* i2c device drivers may be active on return from add_adapter() */
1100 adap->nr = pdev->id;
1101 r = i2c_add_numbered_adapter(adap);
1102 if (r) {
1103 dev_err(dev->dev, "failure adding adapter\n");
1104 goto err_free_irq;
1105 }
1106
1107 return 0;
1108
1109err_free_irq:
1110 free_irq(dev->irq, dev);
1111err_unuse_clocks:
1112 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1113 omap_i2c_idle(dev);
1114 iounmap(dev->base);
1115err_free_mem:
1116 platform_set_drvdata(pdev, NULL);
1117 kfree(dev);
1118err_release_region:
1119 release_mem_region(mem->start, resource_size(mem));
1120
1121 return r;
1122}
1123
1124static int
1125omap_i2c_remove(struct platform_device *pdev)
1126{
1127 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1128 struct resource *mem;
1129
1130 platform_set_drvdata(pdev, NULL);
1131
1132 free_irq(dev->irq, dev);
1133 i2c_del_adapter(&dev->adapter);
1134 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1135 iounmap(dev->base);
1136 kfree(dev);
1137 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1138 release_mem_region(mem->start, resource_size(mem));
1139 return 0;
1140}
1141
1142static struct platform_driver omap_i2c_driver = {
1143 .probe = omap_i2c_probe,
1144 .remove = omap_i2c_remove,
1145 .driver = {
1146 .name = "omap_i2c",
1147 .owner = THIS_MODULE,
1148 },
1149};
1150
1151/* I2C may be needed to bring up other drivers */
1152static int __init
1153omap_i2c_init_driver(void)
1154{
1155 return platform_driver_register(&omap_i2c_driver);
1156}
1157subsys_initcall(omap_i2c_init_driver);
1158
1159static void __exit omap_i2c_exit_driver(void)
1160{
1161 platform_driver_unregister(&omap_i2c_driver);
1162}
1163module_exit(omap_i2c_exit_driver);
1164
1165MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1166MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1167MODULE_LICENSE("GPL");
1168MODULE_ALIAS("platform:omap_i2c");
1/*
2 * TI OMAP I2C master mode driver
3 *
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
7 *
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 */
30
31#include <linux/module.h>
32#include <linux/delay.h>
33#include <linux/i2c.h>
34#include <linux/err.h>
35#include <linux/interrupt.h>
36#include <linux/completion.h>
37#include <linux/platform_device.h>
38#include <linux/clk.h>
39#include <linux/io.h>
40#include <linux/of.h>
41#include <linux/of_device.h>
42#include <linux/slab.h>
43#include <linux/i2c-omap.h>
44#include <linux/pm_runtime.h>
45
46/* I2C controller revisions */
47#define OMAP_I2C_OMAP1_REV_2 0x20
48
49/* I2C controller revisions present on specific hardware */
50#define OMAP_I2C_REV_ON_2430 0x00000036
51#define OMAP_I2C_REV_ON_3430_3530 0x0000003C
52#define OMAP_I2C_REV_ON_3630 0x00000040
53#define OMAP_I2C_REV_ON_4430_PLUS 0x50400002
54
55/* timeout waiting for the controller to respond */
56#define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
57
58/* timeout for pm runtime autosuspend */
59#define OMAP_I2C_PM_TIMEOUT 1000 /* ms */
60
61/* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
62enum {
63 OMAP_I2C_REV_REG = 0,
64 OMAP_I2C_IE_REG,
65 OMAP_I2C_STAT_REG,
66 OMAP_I2C_IV_REG,
67 OMAP_I2C_WE_REG,
68 OMAP_I2C_SYSS_REG,
69 OMAP_I2C_BUF_REG,
70 OMAP_I2C_CNT_REG,
71 OMAP_I2C_DATA_REG,
72 OMAP_I2C_SYSC_REG,
73 OMAP_I2C_CON_REG,
74 OMAP_I2C_OA_REG,
75 OMAP_I2C_SA_REG,
76 OMAP_I2C_PSC_REG,
77 OMAP_I2C_SCLL_REG,
78 OMAP_I2C_SCLH_REG,
79 OMAP_I2C_SYSTEST_REG,
80 OMAP_I2C_BUFSTAT_REG,
81 /* only on OMAP4430 */
82 OMAP_I2C_IP_V2_REVNB_LO,
83 OMAP_I2C_IP_V2_REVNB_HI,
84 OMAP_I2C_IP_V2_IRQSTATUS_RAW,
85 OMAP_I2C_IP_V2_IRQENABLE_SET,
86 OMAP_I2C_IP_V2_IRQENABLE_CLR,
87};
88
89/* I2C Interrupt Enable Register (OMAP_I2C_IE): */
90#define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
91#define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
92#define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
93#define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
94#define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
95#define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
96#define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
97
98/* I2C Status Register (OMAP_I2C_STAT): */
99#define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
100#define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
101#define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
102#define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
103#define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
104#define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
105#define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
106#define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
107#define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
108#define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
109#define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
110#define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
111
112/* I2C WE wakeup enable register */
113#define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
114#define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
115#define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
116#define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
117#define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
118#define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
119#define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
120#define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
121#define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
122#define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
123
124#define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
125 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
126 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
127 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
128 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
129
130/* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
131#define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
132#define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
133#define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
134#define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
135
136/* I2C Configuration Register (OMAP_I2C_CON): */
137#define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
138#define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
139#define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
140#define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
141#define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
142#define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
143#define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
144#define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
145#define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
146#define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
147
148/* I2C SCL time value when Master */
149#define OMAP_I2C_SCLL_HSSCLL 8
150#define OMAP_I2C_SCLH_HSSCLH 8
151
152/* I2C System Test Register (OMAP_I2C_SYSTEST): */
153#ifdef DEBUG
154#define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
155#define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
156#define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
157#define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
158#define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
159#define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
160#define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
161#define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
162#endif
163
164/* OCP_SYSSTATUS bit definitions */
165#define SYSS_RESETDONE_MASK (1 << 0)
166
167/* OCP_SYSCONFIG bit definitions */
168#define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
169#define SYSC_SIDLEMODE_MASK (0x3 << 3)
170#define SYSC_ENAWAKEUP_MASK (1 << 2)
171#define SYSC_SOFTRESET_MASK (1 << 1)
172#define SYSC_AUTOIDLE_MASK (1 << 0)
173
174#define SYSC_IDLEMODE_SMART 0x2
175#define SYSC_CLOCKACTIVITY_FCLK 0x2
176
177/* Errata definitions */
178#define I2C_OMAP_ERRATA_I207 (1 << 0)
179#define I2C_OMAP_ERRATA_I462 (1 << 1)
180
181#define OMAP_I2C_IP_V2_INTERRUPTS_MASK 0x6FFF
182
183struct omap_i2c_dev {
184 spinlock_t lock; /* IRQ synchronization */
185 struct device *dev;
186 void __iomem *base; /* virtual */
187 int irq;
188 int reg_shift; /* bit shift for I2C register addresses */
189 struct completion cmd_complete;
190 struct resource *ioarea;
191 u32 latency; /* maximum mpu wkup latency */
192 void (*set_mpu_wkup_lat)(struct device *dev,
193 long latency);
194 u32 speed; /* Speed of bus in kHz */
195 u32 flags;
196 u16 scheme;
197 u16 cmd_err;
198 u8 *buf;
199 u8 *regs;
200 size_t buf_len;
201 struct i2c_adapter adapter;
202 u8 threshold;
203 u8 fifo_size; /* use as flag and value
204 * fifo_size==0 implies no fifo
205 * if set, should be trsh+1
206 */
207 u32 rev;
208 unsigned b_hw:1; /* bad h/w fixes */
209 unsigned receiver:1; /* true when we're in receiver mode */
210 u16 iestate; /* Saved interrupt register */
211 u16 pscstate;
212 u16 scllstate;
213 u16 sclhstate;
214 u16 syscstate;
215 u16 westate;
216 u16 errata;
217};
218
219static const u8 reg_map_ip_v1[] = {
220 [OMAP_I2C_REV_REG] = 0x00,
221 [OMAP_I2C_IE_REG] = 0x01,
222 [OMAP_I2C_STAT_REG] = 0x02,
223 [OMAP_I2C_IV_REG] = 0x03,
224 [OMAP_I2C_WE_REG] = 0x03,
225 [OMAP_I2C_SYSS_REG] = 0x04,
226 [OMAP_I2C_BUF_REG] = 0x05,
227 [OMAP_I2C_CNT_REG] = 0x06,
228 [OMAP_I2C_DATA_REG] = 0x07,
229 [OMAP_I2C_SYSC_REG] = 0x08,
230 [OMAP_I2C_CON_REG] = 0x09,
231 [OMAP_I2C_OA_REG] = 0x0a,
232 [OMAP_I2C_SA_REG] = 0x0b,
233 [OMAP_I2C_PSC_REG] = 0x0c,
234 [OMAP_I2C_SCLL_REG] = 0x0d,
235 [OMAP_I2C_SCLH_REG] = 0x0e,
236 [OMAP_I2C_SYSTEST_REG] = 0x0f,
237 [OMAP_I2C_BUFSTAT_REG] = 0x10,
238};
239
240static const u8 reg_map_ip_v2[] = {
241 [OMAP_I2C_REV_REG] = 0x04,
242 [OMAP_I2C_IE_REG] = 0x2c,
243 [OMAP_I2C_STAT_REG] = 0x28,
244 [OMAP_I2C_IV_REG] = 0x34,
245 [OMAP_I2C_WE_REG] = 0x34,
246 [OMAP_I2C_SYSS_REG] = 0x90,
247 [OMAP_I2C_BUF_REG] = 0x94,
248 [OMAP_I2C_CNT_REG] = 0x98,
249 [OMAP_I2C_DATA_REG] = 0x9c,
250 [OMAP_I2C_SYSC_REG] = 0x10,
251 [OMAP_I2C_CON_REG] = 0xa4,
252 [OMAP_I2C_OA_REG] = 0xa8,
253 [OMAP_I2C_SA_REG] = 0xac,
254 [OMAP_I2C_PSC_REG] = 0xb0,
255 [OMAP_I2C_SCLL_REG] = 0xb4,
256 [OMAP_I2C_SCLH_REG] = 0xb8,
257 [OMAP_I2C_SYSTEST_REG] = 0xbC,
258 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
259 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00,
260 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04,
261 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24,
262 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c,
263 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30,
264};
265
266static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
267 int reg, u16 val)
268{
269 writew_relaxed(val, i2c_dev->base +
270 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
271}
272
273static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
274{
275 return readw_relaxed(i2c_dev->base +
276 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
277}
278
279static void __omap_i2c_init(struct omap_i2c_dev *dev)
280{
281
282 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
283
284 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
285 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
286
287 /* SCL low and high time values */
288 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
289 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
290 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530)
291 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
292
293 /* Take the I2C module out of reset: */
294 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
295
296 /*
297 * Don't write to this register if the IE state is 0 as it can
298 * cause deadlock.
299 */
300 if (dev->iestate)
301 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
302}
303
304static int omap_i2c_reset(struct omap_i2c_dev *dev)
305{
306 unsigned long timeout;
307 u16 sysc;
308
309 if (dev->rev >= OMAP_I2C_OMAP1_REV_2) {
310 sysc = omap_i2c_read_reg(dev, OMAP_I2C_SYSC_REG);
311
312 /* Disable I2C controller before soft reset */
313 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
314 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
315 ~(OMAP_I2C_CON_EN));
316
317 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
318 /* For some reason we need to set the EN bit before the
319 * reset done bit gets set. */
320 timeout = jiffies + OMAP_I2C_TIMEOUT;
321 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
322 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
323 SYSS_RESETDONE_MASK)) {
324 if (time_after(jiffies, timeout)) {
325 dev_warn(dev->dev, "timeout waiting "
326 "for controller reset\n");
327 return -ETIMEDOUT;
328 }
329 msleep(1);
330 }
331
332 /* SYSC register is cleared by the reset; rewrite it */
333 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, sysc);
334
335 }
336 return 0;
337}
338
339static int omap_i2c_init(struct omap_i2c_dev *dev)
340{
341 u16 psc = 0, scll = 0, sclh = 0;
342 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
343 unsigned long fclk_rate = 12000000;
344 unsigned long internal_clk = 0;
345 struct clk *fclk;
346
347 if (dev->rev >= OMAP_I2C_REV_ON_3430_3530) {
348 /*
349 * Enabling all wakup sources to stop I2C freezing on
350 * WFI instruction.
351 * REVISIT: Some wkup sources might not be needed.
352 */
353 dev->westate = OMAP_I2C_WE_ALL;
354 }
355
356 if (dev->flags & OMAP_I2C_FLAG_ALWAYS_ARMXOR_CLK) {
357 /*
358 * The I2C functional clock is the armxor_ck, so there's
359 * no need to get "armxor_ck" separately. Now, if OMAP2420
360 * always returns 12MHz for the functional clock, we can
361 * do this bit unconditionally.
362 */
363 fclk = clk_get(dev->dev, "fck");
364 fclk_rate = clk_get_rate(fclk);
365 clk_put(fclk);
366
367 /* TRM for 5912 says the I2C clock must be prescaled to be
368 * between 7 - 12 MHz. The XOR input clock is typically
369 * 12, 13 or 19.2 MHz. So we should have code that produces:
370 *
371 * XOR MHz Divider Prescaler
372 * 12 1 0
373 * 13 2 1
374 * 19.2 2 1
375 */
376 if (fclk_rate > 12000000)
377 psc = fclk_rate / 12000000;
378 }
379
380 if (!(dev->flags & OMAP_I2C_FLAG_SIMPLE_CLOCK)) {
381
382 /*
383 * HSI2C controller internal clk rate should be 19.2 Mhz for
384 * HS and for all modes on 2430. On 34xx we can use lower rate
385 * to get longer filter period for better noise suppression.
386 * The filter is iclk (fclk for HS) period.
387 */
388 if (dev->speed > 400 ||
389 dev->flags & OMAP_I2C_FLAG_FORCE_19200_INT_CLK)
390 internal_clk = 19200;
391 else if (dev->speed > 100)
392 internal_clk = 9600;
393 else
394 internal_clk = 4000;
395 fclk = clk_get(dev->dev, "fck");
396 fclk_rate = clk_get_rate(fclk) / 1000;
397 clk_put(fclk);
398
399 /* Compute prescaler divisor */
400 psc = fclk_rate / internal_clk;
401 psc = psc - 1;
402
403 /* If configured for High Speed */
404 if (dev->speed > 400) {
405 unsigned long scl;
406
407 /* For first phase of HS mode */
408 scl = internal_clk / 400;
409 fsscll = scl - (scl / 3) - 7;
410 fssclh = (scl / 3) - 5;
411
412 /* For second phase of HS mode */
413 scl = fclk_rate / dev->speed;
414 hsscll = scl - (scl / 3) - 7;
415 hssclh = (scl / 3) - 5;
416 } else if (dev->speed > 100) {
417 unsigned long scl;
418
419 /* Fast mode */
420 scl = internal_clk / dev->speed;
421 fsscll = scl - (scl / 3) - 7;
422 fssclh = (scl / 3) - 5;
423 } else {
424 /* Standard mode */
425 fsscll = internal_clk / (dev->speed * 2) - 7;
426 fssclh = internal_clk / (dev->speed * 2) - 5;
427 }
428 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
429 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
430 } else {
431 /* Program desired operating rate */
432 fclk_rate /= (psc + 1) * 1000;
433 if (psc > 2)
434 psc = 2;
435 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
436 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
437 }
438
439 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
440 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
441 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
442 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
443
444 dev->pscstate = psc;
445 dev->scllstate = scll;
446 dev->sclhstate = sclh;
447
448 __omap_i2c_init(dev);
449
450 return 0;
451}
452
453/*
454 * Waiting on Bus Busy
455 */
456static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
457{
458 unsigned long timeout;
459
460 timeout = jiffies + OMAP_I2C_TIMEOUT;
461 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
462 if (time_after(jiffies, timeout)) {
463 dev_warn(dev->dev, "timeout waiting for bus ready\n");
464 return -ETIMEDOUT;
465 }
466 msleep(1);
467 }
468
469 return 0;
470}
471
472static void omap_i2c_resize_fifo(struct omap_i2c_dev *dev, u8 size, bool is_rx)
473{
474 u16 buf;
475
476 if (dev->flags & OMAP_I2C_FLAG_NO_FIFO)
477 return;
478
479 /*
480 * Set up notification threshold based on message size. We're doing
481 * this to try and avoid draining feature as much as possible. Whenever
482 * we have big messages to transfer (bigger than our total fifo size)
483 * then we might use draining feature to transfer the remaining bytes.
484 */
485
486 dev->threshold = clamp(size, (u8) 1, dev->fifo_size);
487
488 buf = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
489
490 if (is_rx) {
491 /* Clear RX Threshold */
492 buf &= ~(0x3f << 8);
493 buf |= ((dev->threshold - 1) << 8) | OMAP_I2C_BUF_RXFIF_CLR;
494 } else {
495 /* Clear TX Threshold */
496 buf &= ~0x3f;
497 buf |= (dev->threshold - 1) | OMAP_I2C_BUF_TXFIF_CLR;
498 }
499
500 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
501
502 if (dev->rev < OMAP_I2C_REV_ON_3630)
503 dev->b_hw = 1; /* Enable hardware fixes */
504
505 /* calculate wakeup latency constraint for MPU */
506 if (dev->set_mpu_wkup_lat != NULL)
507 dev->latency = (1000000 * dev->threshold) /
508 (1000 * dev->speed / 8);
509}
510
511/*
512 * Low level master read/write transaction.
513 */
514static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
515 struct i2c_msg *msg, int stop)
516{
517 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
518 unsigned long timeout;
519 u16 w;
520
521 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
522 msg->addr, msg->len, msg->flags, stop);
523
524 if (msg->len == 0)
525 return -EINVAL;
526
527 dev->receiver = !!(msg->flags & I2C_M_RD);
528 omap_i2c_resize_fifo(dev, msg->len, dev->receiver);
529
530 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
531
532 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
533 dev->buf = msg->buf;
534 dev->buf_len = msg->len;
535
536 /* make sure writes to dev->buf_len are ordered */
537 barrier();
538
539 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
540
541 /* Clear the FIFO Buffers */
542 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
543 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
544 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
545
546 reinit_completion(&dev->cmd_complete);
547 dev->cmd_err = 0;
548
549 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
550
551 /* High speed configuration */
552 if (dev->speed > 400)
553 w |= OMAP_I2C_CON_OPMODE_HS;
554
555 if (msg->flags & I2C_M_STOP)
556 stop = 1;
557 if (msg->flags & I2C_M_TEN)
558 w |= OMAP_I2C_CON_XA;
559 if (!(msg->flags & I2C_M_RD))
560 w |= OMAP_I2C_CON_TRX;
561
562 if (!dev->b_hw && stop)
563 w |= OMAP_I2C_CON_STP;
564
565 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
566
567 /*
568 * Don't write stt and stp together on some hardware.
569 */
570 if (dev->b_hw && stop) {
571 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
572 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
573 while (con & OMAP_I2C_CON_STT) {
574 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
575
576 /* Let the user know if i2c is in a bad state */
577 if (time_after(jiffies, delay)) {
578 dev_err(dev->dev, "controller timed out "
579 "waiting for start condition to finish\n");
580 return -ETIMEDOUT;
581 }
582 cpu_relax();
583 }
584
585 w |= OMAP_I2C_CON_STP;
586 w &= ~OMAP_I2C_CON_STT;
587 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
588 }
589
590 /*
591 * REVISIT: We should abort the transfer on signals, but the bus goes
592 * into arbitration and we're currently unable to recover from it.
593 */
594 timeout = wait_for_completion_timeout(&dev->cmd_complete,
595 OMAP_I2C_TIMEOUT);
596 if (timeout == 0) {
597 dev_err(dev->dev, "controller timed out\n");
598 omap_i2c_reset(dev);
599 __omap_i2c_init(dev);
600 return -ETIMEDOUT;
601 }
602
603 if (likely(!dev->cmd_err))
604 return 0;
605
606 /* We have an error */
607 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
608 OMAP_I2C_STAT_XUDF)) {
609 omap_i2c_reset(dev);
610 __omap_i2c_init(dev);
611 return -EIO;
612 }
613
614 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
615 if (msg->flags & I2C_M_IGNORE_NAK)
616 return 0;
617
618 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
619 w |= OMAP_I2C_CON_STP;
620 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
621 return -EREMOTEIO;
622 }
623 return -EIO;
624}
625
626
627/*
628 * Prepare controller for a transaction and call omap_i2c_xfer_msg
629 * to do the work during IRQ processing.
630 */
631static int
632omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
633{
634 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
635 int i;
636 int r;
637
638 r = pm_runtime_get_sync(dev->dev);
639 if (r < 0)
640 goto out;
641
642 r = omap_i2c_wait_for_bb(dev);
643 if (r < 0)
644 goto out;
645
646 if (dev->set_mpu_wkup_lat != NULL)
647 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
648
649 for (i = 0; i < num; i++) {
650 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
651 if (r != 0)
652 break;
653 }
654
655 if (r == 0)
656 r = num;
657
658 omap_i2c_wait_for_bb(dev);
659
660 if (dev->set_mpu_wkup_lat != NULL)
661 dev->set_mpu_wkup_lat(dev->dev, -1);
662
663out:
664 pm_runtime_mark_last_busy(dev->dev);
665 pm_runtime_put_autosuspend(dev->dev);
666 return r;
667}
668
669static u32
670omap_i2c_func(struct i2c_adapter *adap)
671{
672 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
673 I2C_FUNC_PROTOCOL_MANGLING;
674}
675
676static inline void
677omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
678{
679 dev->cmd_err |= err;
680 complete(&dev->cmd_complete);
681}
682
683static inline void
684omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
685{
686 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
687}
688
689static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
690{
691 /*
692 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
693 * Not applicable for OMAP4.
694 * Under certain rare conditions, RDR could be set again
695 * when the bus is busy, then ignore the interrupt and
696 * clear the interrupt.
697 */
698 if (stat & OMAP_I2C_STAT_RDR) {
699 /* Step 1: If RDR is set, clear it */
700 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
701
702 /* Step 2: */
703 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
704 & OMAP_I2C_STAT_BB)) {
705
706 /* Step 3: */
707 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
708 & OMAP_I2C_STAT_RDR) {
709 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
710 dev_dbg(dev->dev, "RDR when bus is busy.\n");
711 }
712
713 }
714 }
715}
716
717/* rev1 devices are apparently only on some 15xx */
718#ifdef CONFIG_ARCH_OMAP15XX
719
720static irqreturn_t
721omap_i2c_omap1_isr(int this_irq, void *dev_id)
722{
723 struct omap_i2c_dev *dev = dev_id;
724 u16 iv, w;
725
726 if (pm_runtime_suspended(dev->dev))
727 return IRQ_NONE;
728
729 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
730 switch (iv) {
731 case 0x00: /* None */
732 break;
733 case 0x01: /* Arbitration lost */
734 dev_err(dev->dev, "Arbitration lost\n");
735 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
736 break;
737 case 0x02: /* No acknowledgement */
738 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
739 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
740 break;
741 case 0x03: /* Register access ready */
742 omap_i2c_complete_cmd(dev, 0);
743 break;
744 case 0x04: /* Receive data ready */
745 if (dev->buf_len) {
746 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
747 *dev->buf++ = w;
748 dev->buf_len--;
749 if (dev->buf_len) {
750 *dev->buf++ = w >> 8;
751 dev->buf_len--;
752 }
753 } else
754 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
755 break;
756 case 0x05: /* Transmit data ready */
757 if (dev->buf_len) {
758 w = *dev->buf++;
759 dev->buf_len--;
760 if (dev->buf_len) {
761 w |= *dev->buf++ << 8;
762 dev->buf_len--;
763 }
764 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
765 } else
766 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
767 break;
768 default:
769 return IRQ_NONE;
770 }
771
772 return IRQ_HANDLED;
773}
774#else
775#define omap_i2c_omap1_isr NULL
776#endif
777
778/*
779 * OMAP3430 Errata i462: When an XRDY/XDR is hit, wait for XUDF before writing
780 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
781 * them from the memory to the I2C interface.
782 */
783static int errata_omap3_i462(struct omap_i2c_dev *dev)
784{
785 unsigned long timeout = 10000;
786 u16 stat;
787
788 do {
789 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
790 if (stat & OMAP_I2C_STAT_XUDF)
791 break;
792
793 if (stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
794 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_XRDY |
795 OMAP_I2C_STAT_XDR));
796 if (stat & OMAP_I2C_STAT_NACK) {
797 dev->cmd_err |= OMAP_I2C_STAT_NACK;
798 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
799 }
800
801 if (stat & OMAP_I2C_STAT_AL) {
802 dev_err(dev->dev, "Arbitration lost\n");
803 dev->cmd_err |= OMAP_I2C_STAT_AL;
804 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
805 }
806
807 return -EIO;
808 }
809
810 cpu_relax();
811 } while (--timeout);
812
813 if (!timeout) {
814 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
815 return 0;
816 }
817
818 return 0;
819}
820
821static void omap_i2c_receive_data(struct omap_i2c_dev *dev, u8 num_bytes,
822 bool is_rdr)
823{
824 u16 w;
825
826 while (num_bytes--) {
827 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
828 *dev->buf++ = w;
829 dev->buf_len--;
830
831 /*
832 * Data reg in 2430, omap3 and
833 * omap4 is 8 bit wide
834 */
835 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
836 *dev->buf++ = w >> 8;
837 dev->buf_len--;
838 }
839 }
840}
841
842static int omap_i2c_transmit_data(struct omap_i2c_dev *dev, u8 num_bytes,
843 bool is_xdr)
844{
845 u16 w;
846
847 while (num_bytes--) {
848 w = *dev->buf++;
849 dev->buf_len--;
850
851 /*
852 * Data reg in 2430, omap3 and
853 * omap4 is 8 bit wide
854 */
855 if (dev->flags & OMAP_I2C_FLAG_16BIT_DATA_REG) {
856 w |= *dev->buf++ << 8;
857 dev->buf_len--;
858 }
859
860 if (dev->errata & I2C_OMAP_ERRATA_I462) {
861 int ret;
862
863 ret = errata_omap3_i462(dev);
864 if (ret < 0)
865 return ret;
866 }
867
868 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
869 }
870
871 return 0;
872}
873
874static irqreturn_t
875omap_i2c_isr(int irq, void *dev_id)
876{
877 struct omap_i2c_dev *dev = dev_id;
878 irqreturn_t ret = IRQ_HANDLED;
879 u16 mask;
880 u16 stat;
881
882 spin_lock(&dev->lock);
883 mask = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
884 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
885
886 if (stat & mask)
887 ret = IRQ_WAKE_THREAD;
888
889 spin_unlock(&dev->lock);
890
891 return ret;
892}
893
894static irqreturn_t
895omap_i2c_isr_thread(int this_irq, void *dev_id)
896{
897 struct omap_i2c_dev *dev = dev_id;
898 unsigned long flags;
899 u16 bits;
900 u16 stat;
901 int err = 0, count = 0;
902
903 spin_lock_irqsave(&dev->lock, flags);
904 do {
905 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
906 stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
907 stat &= bits;
908
909 /* If we're in receiver mode, ignore XDR/XRDY */
910 if (dev->receiver)
911 stat &= ~(OMAP_I2C_STAT_XDR | OMAP_I2C_STAT_XRDY);
912 else
913 stat &= ~(OMAP_I2C_STAT_RDR | OMAP_I2C_STAT_RRDY);
914
915 if (!stat) {
916 /* my work here is done */
917 goto out;
918 }
919
920 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
921 if (count++ == 100) {
922 dev_warn(dev->dev, "Too much work in one IRQ\n");
923 break;
924 }
925
926 if (stat & OMAP_I2C_STAT_NACK) {
927 err |= OMAP_I2C_STAT_NACK;
928 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_NACK);
929 break;
930 }
931
932 if (stat & OMAP_I2C_STAT_AL) {
933 dev_err(dev->dev, "Arbitration lost\n");
934 err |= OMAP_I2C_STAT_AL;
935 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_AL);
936 break;
937 }
938
939 /*
940 * ProDB0017052: Clear ARDY bit twice
941 */
942 if (stat & OMAP_I2C_STAT_ARDY)
943 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ARDY);
944
945 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
946 OMAP_I2C_STAT_AL)) {
947 omap_i2c_ack_stat(dev, (OMAP_I2C_STAT_RRDY |
948 OMAP_I2C_STAT_RDR |
949 OMAP_I2C_STAT_XRDY |
950 OMAP_I2C_STAT_XDR |
951 OMAP_I2C_STAT_ARDY));
952 break;
953 }
954
955 if (stat & OMAP_I2C_STAT_RDR) {
956 u8 num_bytes = 1;
957
958 if (dev->fifo_size)
959 num_bytes = dev->buf_len;
960
961 omap_i2c_receive_data(dev, num_bytes, true);
962
963 if (dev->errata & I2C_OMAP_ERRATA_I207)
964 i2c_omap_errata_i207(dev, stat);
965
966 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
967 continue;
968 }
969
970 if (stat & OMAP_I2C_STAT_RRDY) {
971 u8 num_bytes = 1;
972
973 if (dev->threshold)
974 num_bytes = dev->threshold;
975
976 omap_i2c_receive_data(dev, num_bytes, false);
977 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RRDY);
978 continue;
979 }
980
981 if (stat & OMAP_I2C_STAT_XDR) {
982 u8 num_bytes = 1;
983 int ret;
984
985 if (dev->fifo_size)
986 num_bytes = dev->buf_len;
987
988 ret = omap_i2c_transmit_data(dev, num_bytes, true);
989 if (ret < 0)
990 break;
991
992 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XDR);
993 continue;
994 }
995
996 if (stat & OMAP_I2C_STAT_XRDY) {
997 u8 num_bytes = 1;
998 int ret;
999
1000 if (dev->threshold)
1001 num_bytes = dev->threshold;
1002
1003 ret = omap_i2c_transmit_data(dev, num_bytes, false);
1004 if (ret < 0)
1005 break;
1006
1007 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XRDY);
1008 continue;
1009 }
1010
1011 if (stat & OMAP_I2C_STAT_ROVR) {
1012 dev_err(dev->dev, "Receive overrun\n");
1013 err |= OMAP_I2C_STAT_ROVR;
1014 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_ROVR);
1015 break;
1016 }
1017
1018 if (stat & OMAP_I2C_STAT_XUDF) {
1019 dev_err(dev->dev, "Transmit underflow\n");
1020 err |= OMAP_I2C_STAT_XUDF;
1021 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_XUDF);
1022 break;
1023 }
1024 } while (stat);
1025
1026 omap_i2c_complete_cmd(dev, err);
1027
1028out:
1029 spin_unlock_irqrestore(&dev->lock, flags);
1030
1031 return IRQ_HANDLED;
1032}
1033
1034static const struct i2c_algorithm omap_i2c_algo = {
1035 .master_xfer = omap_i2c_xfer,
1036 .functionality = omap_i2c_func,
1037};
1038
1039#ifdef CONFIG_OF
1040static struct omap_i2c_bus_platform_data omap2420_pdata = {
1041 .rev = OMAP_I2C_IP_VERSION_1,
1042 .flags = OMAP_I2C_FLAG_NO_FIFO |
1043 OMAP_I2C_FLAG_SIMPLE_CLOCK |
1044 OMAP_I2C_FLAG_16BIT_DATA_REG |
1045 OMAP_I2C_FLAG_BUS_SHIFT_2,
1046};
1047
1048static struct omap_i2c_bus_platform_data omap2430_pdata = {
1049 .rev = OMAP_I2C_IP_VERSION_1,
1050 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2 |
1051 OMAP_I2C_FLAG_FORCE_19200_INT_CLK,
1052};
1053
1054static struct omap_i2c_bus_platform_data omap3_pdata = {
1055 .rev = OMAP_I2C_IP_VERSION_1,
1056 .flags = OMAP_I2C_FLAG_BUS_SHIFT_2,
1057};
1058
1059static struct omap_i2c_bus_platform_data omap4_pdata = {
1060 .rev = OMAP_I2C_IP_VERSION_2,
1061};
1062
1063static const struct of_device_id omap_i2c_of_match[] = {
1064 {
1065 .compatible = "ti,omap4-i2c",
1066 .data = &omap4_pdata,
1067 },
1068 {
1069 .compatible = "ti,omap3-i2c",
1070 .data = &omap3_pdata,
1071 },
1072 {
1073 .compatible = "ti,omap2430-i2c",
1074 .data = &omap2430_pdata,
1075 },
1076 {
1077 .compatible = "ti,omap2420-i2c",
1078 .data = &omap2420_pdata,
1079 },
1080 { },
1081};
1082MODULE_DEVICE_TABLE(of, omap_i2c_of_match);
1083#endif
1084
1085#define OMAP_I2C_SCHEME(rev) ((rev & 0xc000) >> 14)
1086
1087#define OMAP_I2C_REV_SCHEME_0_MAJOR(rev) (rev >> 4)
1088#define OMAP_I2C_REV_SCHEME_0_MINOR(rev) (rev & 0xf)
1089
1090#define OMAP_I2C_REV_SCHEME_1_MAJOR(rev) ((rev & 0x0700) >> 7)
1091#define OMAP_I2C_REV_SCHEME_1_MINOR(rev) (rev & 0x1f)
1092#define OMAP_I2C_SCHEME_0 0
1093#define OMAP_I2C_SCHEME_1 1
1094
1095static int
1096omap_i2c_probe(struct platform_device *pdev)
1097{
1098 struct omap_i2c_dev *dev;
1099 struct i2c_adapter *adap;
1100 struct resource *mem;
1101 const struct omap_i2c_bus_platform_data *pdata =
1102 dev_get_platdata(&pdev->dev);
1103 struct device_node *node = pdev->dev.of_node;
1104 const struct of_device_id *match;
1105 int irq;
1106 int r;
1107 u32 rev;
1108 u16 minor, major;
1109
1110 irq = platform_get_irq(pdev, 0);
1111 if (irq < 0) {
1112 dev_err(&pdev->dev, "no irq resource?\n");
1113 return irq;
1114 }
1115
1116 dev = devm_kzalloc(&pdev->dev, sizeof(struct omap_i2c_dev), GFP_KERNEL);
1117 if (!dev) {
1118 dev_err(&pdev->dev, "Menory allocation failed\n");
1119 return -ENOMEM;
1120 }
1121
1122 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1123 dev->base = devm_ioremap_resource(&pdev->dev, mem);
1124 if (IS_ERR(dev->base))
1125 return PTR_ERR(dev->base);
1126
1127 match = of_match_device(of_match_ptr(omap_i2c_of_match), &pdev->dev);
1128 if (match) {
1129 u32 freq = 100000; /* default to 100000 Hz */
1130
1131 pdata = match->data;
1132 dev->flags = pdata->flags;
1133
1134 of_property_read_u32(node, "clock-frequency", &freq);
1135 /* convert DT freq value in Hz into kHz for speed */
1136 dev->speed = freq / 1000;
1137 } else if (pdata != NULL) {
1138 dev->speed = pdata->clkrate;
1139 dev->flags = pdata->flags;
1140 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1141 }
1142
1143 dev->dev = &pdev->dev;
1144 dev->irq = irq;
1145
1146 spin_lock_init(&dev->lock);
1147
1148 platform_set_drvdata(pdev, dev);
1149 init_completion(&dev->cmd_complete);
1150
1151 dev->reg_shift = (dev->flags >> OMAP_I2C_FLAG_BUS_SHIFT__SHIFT) & 3;
1152
1153 pm_runtime_enable(dev->dev);
1154 pm_runtime_set_autosuspend_delay(dev->dev, OMAP_I2C_PM_TIMEOUT);
1155 pm_runtime_use_autosuspend(dev->dev);
1156
1157 r = pm_runtime_get_sync(dev->dev);
1158 if (r < 0)
1159 goto err_free_mem;
1160
1161 /*
1162 * Read the Rev hi bit-[15:14] ie scheme this is 1 indicates ver2.
1163 * On omap1/3/2 Offset 4 is IE Reg the bit [15:14] is 0 at reset.
1164 * Also since the omap_i2c_read_reg uses reg_map_ip_* a
1165 * readw_relaxed is done.
1166 */
1167 rev = readw_relaxed(dev->base + 0x04);
1168
1169 dev->scheme = OMAP_I2C_SCHEME(rev);
1170 switch (dev->scheme) {
1171 case OMAP_I2C_SCHEME_0:
1172 dev->regs = (u8 *)reg_map_ip_v1;
1173 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG);
1174 minor = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1175 major = OMAP_I2C_REV_SCHEME_0_MAJOR(dev->rev);
1176 break;
1177 case OMAP_I2C_SCHEME_1:
1178 /* FALLTHROUGH */
1179 default:
1180 dev->regs = (u8 *)reg_map_ip_v2;
1181 rev = (rev << 16) |
1182 omap_i2c_read_reg(dev, OMAP_I2C_IP_V2_REVNB_LO);
1183 minor = OMAP_I2C_REV_SCHEME_1_MINOR(rev);
1184 major = OMAP_I2C_REV_SCHEME_1_MAJOR(rev);
1185 dev->rev = rev;
1186 }
1187
1188 dev->errata = 0;
1189
1190 if (dev->rev >= OMAP_I2C_REV_ON_2430 &&
1191 dev->rev < OMAP_I2C_REV_ON_4430_PLUS)
1192 dev->errata |= I2C_OMAP_ERRATA_I207;
1193
1194 if (dev->rev <= OMAP_I2C_REV_ON_3430_3530)
1195 dev->errata |= I2C_OMAP_ERRATA_I462;
1196
1197 if (!(dev->flags & OMAP_I2C_FLAG_NO_FIFO)) {
1198 u16 s;
1199
1200 /* Set up the fifo size - Get total size */
1201 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1202 dev->fifo_size = 0x8 << s;
1203
1204 /*
1205 * Set up notification threshold as half the total available
1206 * size. This is to ensure that we can handle the status on int
1207 * call back latencies.
1208 */
1209
1210 dev->fifo_size = (dev->fifo_size / 2);
1211
1212 if (dev->rev < OMAP_I2C_REV_ON_3630)
1213 dev->b_hw = 1; /* Enable hardware fixes */
1214
1215 /* calculate wakeup latency constraint for MPU */
1216 if (dev->set_mpu_wkup_lat != NULL)
1217 dev->latency = (1000000 * dev->fifo_size) /
1218 (1000 * dev->speed / 8);
1219 }
1220
1221 /* reset ASAP, clearing any IRQs */
1222 omap_i2c_init(dev);
1223
1224 if (dev->rev < OMAP_I2C_OMAP1_REV_2)
1225 r = devm_request_irq(&pdev->dev, dev->irq, omap_i2c_omap1_isr,
1226 IRQF_NO_SUSPEND, pdev->name, dev);
1227 else
1228 r = devm_request_threaded_irq(&pdev->dev, dev->irq,
1229 omap_i2c_isr, omap_i2c_isr_thread,
1230 IRQF_NO_SUSPEND | IRQF_ONESHOT,
1231 pdev->name, dev);
1232
1233 if (r) {
1234 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1235 goto err_unuse_clocks;
1236 }
1237
1238 adap = &dev->adapter;
1239 i2c_set_adapdata(adap, dev);
1240 adap->owner = THIS_MODULE;
1241 adap->class = I2C_CLASS_HWMON | I2C_CLASS_DEPRECATED;
1242 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1243 adap->algo = &omap_i2c_algo;
1244 adap->dev.parent = &pdev->dev;
1245 adap->dev.of_node = pdev->dev.of_node;
1246
1247 /* i2c device drivers may be active on return from add_adapter() */
1248 adap->nr = pdev->id;
1249 r = i2c_add_numbered_adapter(adap);
1250 if (r) {
1251 dev_err(dev->dev, "failure adding adapter\n");
1252 goto err_unuse_clocks;
1253 }
1254
1255 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n", adap->nr,
1256 major, minor, dev->speed);
1257
1258 pm_runtime_mark_last_busy(dev->dev);
1259 pm_runtime_put_autosuspend(dev->dev);
1260
1261 return 0;
1262
1263err_unuse_clocks:
1264 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1265 pm_runtime_put(dev->dev);
1266 pm_runtime_disable(&pdev->dev);
1267err_free_mem:
1268
1269 return r;
1270}
1271
1272static int omap_i2c_remove(struct platform_device *pdev)
1273{
1274 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1275 int ret;
1276
1277 i2c_del_adapter(&dev->adapter);
1278 ret = pm_runtime_get_sync(&pdev->dev);
1279 if (ret < 0)
1280 return ret;
1281
1282 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1283 pm_runtime_put(&pdev->dev);
1284 pm_runtime_disable(&pdev->dev);
1285 return 0;
1286}
1287
1288#ifdef CONFIG_PM
1289#ifdef CONFIG_PM_RUNTIME
1290static int omap_i2c_runtime_suspend(struct device *dev)
1291{
1292 struct platform_device *pdev = to_platform_device(dev);
1293 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1294
1295 _dev->iestate = omap_i2c_read_reg(_dev, OMAP_I2C_IE_REG);
1296
1297 if (_dev->scheme == OMAP_I2C_SCHEME_0)
1298 omap_i2c_write_reg(_dev, OMAP_I2C_IE_REG, 0);
1299 else
1300 omap_i2c_write_reg(_dev, OMAP_I2C_IP_V2_IRQENABLE_CLR,
1301 OMAP_I2C_IP_V2_INTERRUPTS_MASK);
1302
1303 if (_dev->rev < OMAP_I2C_OMAP1_REV_2) {
1304 omap_i2c_read_reg(_dev, OMAP_I2C_IV_REG); /* Read clears */
1305 } else {
1306 omap_i2c_write_reg(_dev, OMAP_I2C_STAT_REG, _dev->iestate);
1307
1308 /* Flush posted write */
1309 omap_i2c_read_reg(_dev, OMAP_I2C_STAT_REG);
1310 }
1311
1312 return 0;
1313}
1314
1315static int omap_i2c_runtime_resume(struct device *dev)
1316{
1317 struct platform_device *pdev = to_platform_device(dev);
1318 struct omap_i2c_dev *_dev = platform_get_drvdata(pdev);
1319
1320 if (!_dev->regs)
1321 return 0;
1322
1323 __omap_i2c_init(_dev);
1324
1325 return 0;
1326}
1327#endif /* CONFIG_PM_RUNTIME */
1328
1329static struct dev_pm_ops omap_i2c_pm_ops = {
1330 SET_RUNTIME_PM_OPS(omap_i2c_runtime_suspend,
1331 omap_i2c_runtime_resume, NULL)
1332};
1333#define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1334#else
1335#define OMAP_I2C_PM_OPS NULL
1336#endif /* CONFIG_PM */
1337
1338static struct platform_driver omap_i2c_driver = {
1339 .probe = omap_i2c_probe,
1340 .remove = omap_i2c_remove,
1341 .driver = {
1342 .name = "omap_i2c",
1343 .owner = THIS_MODULE,
1344 .pm = OMAP_I2C_PM_OPS,
1345 .of_match_table = of_match_ptr(omap_i2c_of_match),
1346 },
1347};
1348
1349/* I2C may be needed to bring up other drivers */
1350static int __init
1351omap_i2c_init_driver(void)
1352{
1353 return platform_driver_register(&omap_i2c_driver);
1354}
1355subsys_initcall(omap_i2c_init_driver);
1356
1357static void __exit omap_i2c_exit_driver(void)
1358{
1359 platform_driver_unregister(&omap_i2c_driver);
1360}
1361module_exit(omap_i2c_exit_driver);
1362
1363MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1364MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1365MODULE_LICENSE("GPL");
1366MODULE_ALIAS("platform:omap_i2c");