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1/*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010 Cavium Networks, Inc.
6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/sched.h>
17#include <linux/slab.h>
18#include <linux/init.h>
19
20#include <linux/io.h>
21#include <linux/i2c.h>
22#include <linux/interrupt.h>
23#include <linux/delay.h>
24#include <linux/platform_device.h>
25
26#include <asm/octeon/octeon.h>
27
28#define DRV_NAME "i2c-octeon"
29
30/* The previous out-of-tree version was implicitly version 1.0. */
31#define DRV_VERSION "2.0"
32
33/* register offsets */
34#define SW_TWSI 0x00
35#define TWSI_INT 0x10
36
37/* Controller command patterns */
38#define SW_TWSI_V 0x8000000000000000ull
39#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
40#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
41#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
42#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
43#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
44#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
45#define SW_TWSI_R 0x0100000000000000ull
46
47/* Controller command and status bits */
48#define TWSI_CTL_CE 0x80
49#define TWSI_CTL_ENAB 0x40
50#define TWSI_CTL_STA 0x20
51#define TWSI_CTL_STP 0x10
52#define TWSI_CTL_IFLG 0x08
53#define TWSI_CTL_AAK 0x04
54
55/* Some status values */
56#define STAT_START 0x08
57#define STAT_RSTART 0x10
58#define STAT_TXADDR_ACK 0x18
59#define STAT_TXDATA_ACK 0x28
60#define STAT_RXADDR_ACK 0x40
61#define STAT_RXDATA_ACK 0x50
62#define STAT_IDLE 0xF8
63
64struct octeon_i2c {
65 wait_queue_head_t queue;
66 struct i2c_adapter adap;
67 int irq;
68 int twsi_freq;
69 int sys_freq;
70 resource_size_t twsi_phys;
71 void __iomem *twsi_base;
72 resource_size_t regsize;
73 struct device *dev;
74};
75
76/**
77 * octeon_i2c_write_sw - write an I2C core register.
78 * @i2c: The struct octeon_i2c.
79 * @eop_reg: Register selector.
80 * @data: Value to be written.
81 *
82 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
83 */
84static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
85 u64 eop_reg,
86 u8 data)
87{
88 u64 tmp;
89
90 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
91 do {
92 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
93 } while ((tmp & SW_TWSI_V) != 0);
94}
95
96/**
97 * octeon_i2c_read_sw - write an I2C core register.
98 * @i2c: The struct octeon_i2c.
99 * @eop_reg: Register selector.
100 *
101 * Returns the data.
102 *
103 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
104 */
105static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
106{
107 u64 tmp;
108
109 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
110 do {
111 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
112 } while ((tmp & SW_TWSI_V) != 0);
113
114 return tmp & 0xFF;
115}
116
117/**
118 * octeon_i2c_write_int - write the TWSI_INT register
119 * @i2c: The struct octeon_i2c.
120 * @data: Value to be written.
121 */
122static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
123{
124 u64 tmp;
125
126 __raw_writeq(data, i2c->twsi_base + TWSI_INT);
127 tmp = __raw_readq(i2c->twsi_base + TWSI_INT);
128}
129
130/**
131 * octeon_i2c_int_enable - enable the TS interrupt.
132 * @i2c: The struct octeon_i2c.
133 *
134 * The interrupt will be asserted when there is non-STAT_IDLE state in
135 * the SW_TWSI_EOP_TWSI_STAT register.
136 */
137static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
138{
139 octeon_i2c_write_int(i2c, 0x40);
140}
141
142/**
143 * octeon_i2c_int_disable - disable the TS interrupt.
144 * @i2c: The struct octeon_i2c.
145 */
146static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
147{
148 octeon_i2c_write_int(i2c, 0);
149}
150
151/**
152 * octeon_i2c_unblock - unblock the bus.
153 * @i2c: The struct octeon_i2c.
154 *
155 * If there was a reset while a device was driving 0 to bus,
156 * bus is blocked. We toggle it free manually by some clock
157 * cycles and send a stop.
158 */
159static void octeon_i2c_unblock(struct octeon_i2c *i2c)
160{
161 int i;
162
163 dev_dbg(i2c->dev, "%s\n", __func__);
164 for (i = 0; i < 9; i++) {
165 octeon_i2c_write_int(i2c, 0x0);
166 udelay(5);
167 octeon_i2c_write_int(i2c, 0x200);
168 udelay(5);
169 }
170 octeon_i2c_write_int(i2c, 0x300);
171 udelay(5);
172 octeon_i2c_write_int(i2c, 0x100);
173 udelay(5);
174 octeon_i2c_write_int(i2c, 0x0);
175}
176
177/**
178 * octeon_i2c_isr - the interrupt service routine.
179 * @int: The irq, unused.
180 * @dev_id: Our struct octeon_i2c.
181 */
182static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
183{
184 struct octeon_i2c *i2c = dev_id;
185
186 octeon_i2c_int_disable(i2c);
187 wake_up_interruptible(&i2c->queue);
188
189 return IRQ_HANDLED;
190}
191
192
193static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
194{
195 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
196}
197
198/**
199 * octeon_i2c_wait - wait for the IFLG to be set.
200 * @i2c: The struct octeon_i2c.
201 *
202 * Returns 0 on success, otherwise a negative errno.
203 */
204static int octeon_i2c_wait(struct octeon_i2c *i2c)
205{
206 int result;
207
208 octeon_i2c_int_enable(i2c);
209
210 result = wait_event_interruptible_timeout(i2c->queue,
211 octeon_i2c_test_iflg(i2c),
212 i2c->adap.timeout);
213
214 octeon_i2c_int_disable(i2c);
215
216 if (result < 0) {
217 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
218 return result;
219 } else if (result == 0) {
220 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
221 return -ETIMEDOUT;
222 }
223
224 return 0;
225}
226
227/**
228 * octeon_i2c_start - send START to the bus.
229 * @i2c: The struct octeon_i2c.
230 *
231 * Returns 0 on success, otherwise a negative errno.
232 */
233static int octeon_i2c_start(struct octeon_i2c *i2c)
234{
235 u8 data;
236 int result;
237
238 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
239 TWSI_CTL_ENAB | TWSI_CTL_STA);
240
241 result = octeon_i2c_wait(i2c);
242 if (result) {
243 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
244 /*
245 * Controller refused to send start flag May
246 * be a client is holding SDA low - let's try
247 * to free it.
248 */
249 octeon_i2c_unblock(i2c);
250 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
251 TWSI_CTL_ENAB | TWSI_CTL_STA);
252
253 result = octeon_i2c_wait(i2c);
254 }
255 if (result)
256 return result;
257 }
258
259 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
260 if ((data != STAT_START) && (data != STAT_RSTART)) {
261 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
262 return -EIO;
263 }
264
265 return 0;
266}
267
268/**
269 * octeon_i2c_stop - send STOP to the bus.
270 * @i2c: The struct octeon_i2c.
271 *
272 * Returns 0 on success, otherwise a negative errno.
273 */
274static int octeon_i2c_stop(struct octeon_i2c *i2c)
275{
276 u8 data;
277
278 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
279 TWSI_CTL_ENAB | TWSI_CTL_STP);
280
281 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
282
283 if (data != STAT_IDLE) {
284 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
285 return -EIO;
286 }
287 return 0;
288}
289
290/**
291 * octeon_i2c_write - send data to the bus.
292 * @i2c: The struct octeon_i2c.
293 * @target: Target address.
294 * @data: Pointer to the data to be sent.
295 * @length: Length of the data.
296 *
297 * The address is sent over the bus, then the data.
298 *
299 * Returns 0 on success, otherwise a negative errno.
300 */
301static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
302 const u8 *data, int length)
303{
304 int i, result;
305 u8 tmp;
306
307 result = octeon_i2c_start(i2c);
308 if (result)
309 return result;
310
311 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
312 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
313
314 result = octeon_i2c_wait(i2c);
315 if (result)
316 return result;
317
318 for (i = 0; i < length; i++) {
319 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
320 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
321 dev_err(i2c->dev,
322 "%s: bad status before write (0x%x)\n",
323 __func__, tmp);
324 return -EIO;
325 }
326
327 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
328 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
329
330 result = octeon_i2c_wait(i2c);
331 if (result)
332 return result;
333 }
334
335 return 0;
336}
337
338/**
339 * octeon_i2c_read - receive data from the bus.
340 * @i2c: The struct octeon_i2c.
341 * @target: Target address.
342 * @data: Pointer to the location to store the datae .
343 * @length: Length of the data.
344 *
345 * The address is sent over the bus, then the data is read.
346 *
347 * Returns 0 on success, otherwise a negative errno.
348 */
349static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
350 u8 *data, int length)
351{
352 int i, result;
353 u8 tmp;
354
355 if (length < 1)
356 return -EINVAL;
357
358 result = octeon_i2c_start(i2c);
359 if (result)
360 return result;
361
362 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
363 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
364
365 result = octeon_i2c_wait(i2c);
366 if (result)
367 return result;
368
369 for (i = 0; i < length; i++) {
370 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
371 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
372 dev_err(i2c->dev,
373 "%s: bad status before read (0x%x)\n",
374 __func__, tmp);
375 return -EIO;
376 }
377
378 if (i+1 < length)
379 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
380 TWSI_CTL_ENAB | TWSI_CTL_AAK);
381 else
382 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
383 TWSI_CTL_ENAB);
384
385 result = octeon_i2c_wait(i2c);
386 if (result)
387 return result;
388
389 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
390 }
391 return 0;
392}
393
394/**
395 * octeon_i2c_xfer - The driver's master_xfer function.
396 * @adap: Pointer to the i2c_adapter structure.
397 * @msgs: Pointer to the messages to be processed.
398 * @num: Length of the MSGS array.
399 *
400 * Returns the number of messages processed, or a negative errno on
401 * failure.
402 */
403static int octeon_i2c_xfer(struct i2c_adapter *adap,
404 struct i2c_msg *msgs,
405 int num)
406{
407 struct i2c_msg *pmsg;
408 int i;
409 int ret = 0;
410 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
411
412 for (i = 0; ret == 0 && i < num; i++) {
413 pmsg = &msgs[i];
414 dev_dbg(i2c->dev,
415 "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
416 pmsg->flags & I2C_M_RD ? "read" : "write",
417 pmsg->len, pmsg->addr, i + 1, num);
418 if (pmsg->flags & I2C_M_RD)
419 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
420 pmsg->len);
421 else
422 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
423 pmsg->len);
424 }
425 octeon_i2c_stop(i2c);
426
427 return (ret != 0) ? ret : num;
428}
429
430static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
431{
432 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
433}
434
435static const struct i2c_algorithm octeon_i2c_algo = {
436 .master_xfer = octeon_i2c_xfer,
437 .functionality = octeon_i2c_functionality,
438};
439
440static struct i2c_adapter octeon_i2c_ops = {
441 .owner = THIS_MODULE,
442 .name = "OCTEON adapter",
443 .algo = &octeon_i2c_algo,
444 .timeout = 2,
445};
446
447/**
448 * octeon_i2c_setclock - Calculate and set clock divisors.
449 */
450static int __devinit octeon_i2c_setclock(struct octeon_i2c *i2c)
451{
452 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
453 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
454
455 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
456 /*
457 * An mdiv value of less than 2 seems to not work well
458 * with ds1337 RTCs, so we constrain it to larger
459 * values.
460 */
461 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
462 /*
463 * For given ndiv and mdiv values check the
464 * two closest thp values.
465 */
466 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
467 tclk *= (1 << ndiv_idx);
468 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
469 for (inc = 0; inc <= 1; inc++) {
470 thp_idx = thp_base + inc;
471 if (thp_idx < 5 || thp_idx > 0xff)
472 continue;
473
474 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
475 foscl = foscl / (1 << ndiv_idx);
476 foscl = foscl / (mdiv_idx + 1) / 10;
477 diff = abs(foscl - i2c->twsi_freq);
478 if (diff < delta_hz) {
479 delta_hz = diff;
480 thp = thp_idx;
481 mdiv = mdiv_idx;
482 ndiv = ndiv_idx;
483 }
484 }
485 }
486 }
487 octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
488 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
489
490 return 0;
491}
492
493static int __devinit octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
494{
495 u8 status;
496 int tries;
497
498 /* disable high level controller, enable bus access */
499 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
500
501 /* reset controller */
502 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
503
504 for (tries = 10; tries; tries--) {
505 udelay(1);
506 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
507 if (status == STAT_IDLE)
508 return 0;
509 }
510 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
511 return -EIO;
512}
513
514static int __devinit octeon_i2c_probe(struct platform_device *pdev)
515{
516 int irq, result = 0;
517 struct octeon_i2c *i2c;
518 struct octeon_i2c_data *i2c_data;
519 struct resource *res_mem;
520
521 /* All adaptors have an irq. */
522 irq = platform_get_irq(pdev, 0);
523 if (irq < 0)
524 return irq;
525
526 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
527 if (!i2c) {
528 dev_err(&pdev->dev, "kzalloc failed\n");
529 result = -ENOMEM;
530 goto out;
531 }
532 i2c->dev = &pdev->dev;
533 i2c_data = pdev->dev.platform_data;
534
535 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
536
537 if (res_mem == NULL) {
538 dev_err(i2c->dev, "found no memory resource\n");
539 result = -ENXIO;
540 goto fail_region;
541 }
542
543 if (i2c_data == NULL) {
544 dev_err(i2c->dev, "no I2C frequency data\n");
545 result = -ENXIO;
546 goto fail_region;
547 }
548
549 i2c->twsi_phys = res_mem->start;
550 i2c->regsize = resource_size(res_mem);
551 i2c->twsi_freq = i2c_data->i2c_freq;
552 i2c->sys_freq = i2c_data->sys_freq;
553
554 if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) {
555 dev_err(i2c->dev, "request_mem_region failed\n");
556 goto fail_region;
557 }
558 i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize);
559
560 init_waitqueue_head(&i2c->queue);
561
562 i2c->irq = irq;
563
564 result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c);
565 if (result < 0) {
566 dev_err(i2c->dev, "failed to attach interrupt\n");
567 goto fail_irq;
568 }
569
570 result = octeon_i2c_initlowlevel(i2c);
571 if (result) {
572 dev_err(i2c->dev, "init low level failed\n");
573 goto fail_add;
574 }
575
576 result = octeon_i2c_setclock(i2c);
577 if (result) {
578 dev_err(i2c->dev, "clock init failed\n");
579 goto fail_add;
580 }
581
582 i2c->adap = octeon_i2c_ops;
583 i2c->adap.dev.parent = &pdev->dev;
584 i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0;
585 i2c_set_adapdata(&i2c->adap, i2c);
586 platform_set_drvdata(pdev, i2c);
587
588 result = i2c_add_numbered_adapter(&i2c->adap);
589 if (result < 0) {
590 dev_err(i2c->dev, "failed to add adapter\n");
591 goto fail_add;
592 }
593
594 dev_info(i2c->dev, "version %s\n", DRV_VERSION);
595
596 return result;
597
598fail_add:
599 platform_set_drvdata(pdev, NULL);
600 free_irq(i2c->irq, i2c);
601fail_irq:
602 iounmap(i2c->twsi_base);
603 release_mem_region(i2c->twsi_phys, i2c->regsize);
604fail_region:
605 kfree(i2c);
606out:
607 return result;
608};
609
610static int __devexit octeon_i2c_remove(struct platform_device *pdev)
611{
612 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
613
614 i2c_del_adapter(&i2c->adap);
615 platform_set_drvdata(pdev, NULL);
616 free_irq(i2c->irq, i2c);
617 iounmap(i2c->twsi_base);
618 release_mem_region(i2c->twsi_phys, i2c->regsize);
619 kfree(i2c);
620 return 0;
621};
622
623static struct platform_driver octeon_i2c_driver = {
624 .probe = octeon_i2c_probe,
625 .remove = __devexit_p(octeon_i2c_remove),
626 .driver = {
627 .owner = THIS_MODULE,
628 .name = DRV_NAME,
629 },
630};
631
632static int __init octeon_i2c_init(void)
633{
634 int rv;
635
636 rv = platform_driver_register(&octeon_i2c_driver);
637 return rv;
638}
639
640static void __exit octeon_i2c_exit(void)
641{
642 platform_driver_unregister(&octeon_i2c_driver);
643}
644
645MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
646MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
647MODULE_LICENSE("GPL");
648MODULE_VERSION(DRV_VERSION);
649MODULE_ALIAS("platform:" DRV_NAME);
650
651module_init(octeon_i2c_init);
652module_exit(octeon_i2c_exit);
1/*
2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 *
5 * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 *
9 * This file is licensed under the terms of the GNU General Public
10 * License version 2. This program is licensed "as is" without any
11 * warranty of any kind, whether express or implied.
12 */
13
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/delay.h>
19#include <linux/sched.h>
20#include <linux/slab.h>
21#include <linux/i2c.h>
22#include <linux/io.h>
23#include <linux/of.h>
24
25#include <asm/octeon/octeon.h>
26
27#define DRV_NAME "i2c-octeon"
28
29/* The previous out-of-tree version was implicitly version 1.0. */
30#define DRV_VERSION "2.0"
31
32/* register offsets */
33#define SW_TWSI 0x00
34#define TWSI_INT 0x10
35
36/* Controller command patterns */
37#define SW_TWSI_V 0x8000000000000000ull
38#define SW_TWSI_EOP_TWSI_DATA 0x0C00000100000000ull
39#define SW_TWSI_EOP_TWSI_CTL 0x0C00000200000000ull
40#define SW_TWSI_EOP_TWSI_CLKCTL 0x0C00000300000000ull
41#define SW_TWSI_EOP_TWSI_STAT 0x0C00000300000000ull
42#define SW_TWSI_EOP_TWSI_RST 0x0C00000700000000ull
43#define SW_TWSI_OP_TWSI_CLK 0x0800000000000000ull
44#define SW_TWSI_R 0x0100000000000000ull
45
46/* Controller command and status bits */
47#define TWSI_CTL_CE 0x80
48#define TWSI_CTL_ENAB 0x40
49#define TWSI_CTL_STA 0x20
50#define TWSI_CTL_STP 0x10
51#define TWSI_CTL_IFLG 0x08
52#define TWSI_CTL_AAK 0x04
53
54/* Some status values */
55#define STAT_START 0x08
56#define STAT_RSTART 0x10
57#define STAT_TXADDR_ACK 0x18
58#define STAT_TXDATA_ACK 0x28
59#define STAT_RXADDR_ACK 0x40
60#define STAT_RXDATA_ACK 0x50
61#define STAT_IDLE 0xF8
62
63struct octeon_i2c {
64 wait_queue_head_t queue;
65 struct i2c_adapter adap;
66 int irq;
67 u32 twsi_freq;
68 int sys_freq;
69 resource_size_t twsi_phys;
70 void __iomem *twsi_base;
71 resource_size_t regsize;
72 struct device *dev;
73};
74
75/**
76 * octeon_i2c_write_sw - write an I2C core register.
77 * @i2c: The struct octeon_i2c.
78 * @eop_reg: Register selector.
79 * @data: Value to be written.
80 *
81 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
82 */
83static void octeon_i2c_write_sw(struct octeon_i2c *i2c,
84 u64 eop_reg,
85 u8 data)
86{
87 u64 tmp;
88
89 __raw_writeq(SW_TWSI_V | eop_reg | data, i2c->twsi_base + SW_TWSI);
90 do {
91 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
92 } while ((tmp & SW_TWSI_V) != 0);
93}
94
95/**
96 * octeon_i2c_read_sw - write an I2C core register.
97 * @i2c: The struct octeon_i2c.
98 * @eop_reg: Register selector.
99 *
100 * Returns the data.
101 *
102 * The I2C core registers are accessed indirectly via the SW_TWSI CSR.
103 */
104static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
105{
106 u64 tmp;
107
108 __raw_writeq(SW_TWSI_V | eop_reg | SW_TWSI_R, i2c->twsi_base + SW_TWSI);
109 do {
110 tmp = __raw_readq(i2c->twsi_base + SW_TWSI);
111 } while ((tmp & SW_TWSI_V) != 0);
112
113 return tmp & 0xFF;
114}
115
116/**
117 * octeon_i2c_write_int - write the TWSI_INT register
118 * @i2c: The struct octeon_i2c.
119 * @data: Value to be written.
120 */
121static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
122{
123 __raw_writeq(data, i2c->twsi_base + TWSI_INT);
124 __raw_readq(i2c->twsi_base + TWSI_INT);
125}
126
127/**
128 * octeon_i2c_int_enable - enable the TS interrupt.
129 * @i2c: The struct octeon_i2c.
130 *
131 * The interrupt will be asserted when there is non-STAT_IDLE state in
132 * the SW_TWSI_EOP_TWSI_STAT register.
133 */
134static void octeon_i2c_int_enable(struct octeon_i2c *i2c)
135{
136 octeon_i2c_write_int(i2c, 0x40);
137}
138
139/**
140 * octeon_i2c_int_disable - disable the TS interrupt.
141 * @i2c: The struct octeon_i2c.
142 */
143static void octeon_i2c_int_disable(struct octeon_i2c *i2c)
144{
145 octeon_i2c_write_int(i2c, 0);
146}
147
148/**
149 * octeon_i2c_unblock - unblock the bus.
150 * @i2c: The struct octeon_i2c.
151 *
152 * If there was a reset while a device was driving 0 to bus,
153 * bus is blocked. We toggle it free manually by some clock
154 * cycles and send a stop.
155 */
156static void octeon_i2c_unblock(struct octeon_i2c *i2c)
157{
158 int i;
159
160 dev_dbg(i2c->dev, "%s\n", __func__);
161 for (i = 0; i < 9; i++) {
162 octeon_i2c_write_int(i2c, 0x0);
163 udelay(5);
164 octeon_i2c_write_int(i2c, 0x200);
165 udelay(5);
166 }
167 octeon_i2c_write_int(i2c, 0x300);
168 udelay(5);
169 octeon_i2c_write_int(i2c, 0x100);
170 udelay(5);
171 octeon_i2c_write_int(i2c, 0x0);
172}
173
174/**
175 * octeon_i2c_isr - the interrupt service routine.
176 * @int: The irq, unused.
177 * @dev_id: Our struct octeon_i2c.
178 */
179static irqreturn_t octeon_i2c_isr(int irq, void *dev_id)
180{
181 struct octeon_i2c *i2c = dev_id;
182
183 octeon_i2c_int_disable(i2c);
184 wake_up(&i2c->queue);
185
186 return IRQ_HANDLED;
187}
188
189
190static int octeon_i2c_test_iflg(struct octeon_i2c *i2c)
191{
192 return (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_CTL) & TWSI_CTL_IFLG) != 0;
193}
194
195/**
196 * octeon_i2c_wait - wait for the IFLG to be set.
197 * @i2c: The struct octeon_i2c.
198 *
199 * Returns 0 on success, otherwise a negative errno.
200 */
201static int octeon_i2c_wait(struct octeon_i2c *i2c)
202{
203 int result;
204
205 octeon_i2c_int_enable(i2c);
206
207 result = wait_event_timeout(i2c->queue,
208 octeon_i2c_test_iflg(i2c),
209 i2c->adap.timeout);
210
211 octeon_i2c_int_disable(i2c);
212
213 if (result < 0) {
214 dev_dbg(i2c->dev, "%s: wait interrupted\n", __func__);
215 return result;
216 } else if (result == 0) {
217 dev_dbg(i2c->dev, "%s: timeout\n", __func__);
218 return -ETIMEDOUT;
219 }
220
221 return 0;
222}
223
224/**
225 * octeon_i2c_start - send START to the bus.
226 * @i2c: The struct octeon_i2c.
227 *
228 * Returns 0 on success, otherwise a negative errno.
229 */
230static int octeon_i2c_start(struct octeon_i2c *i2c)
231{
232 u8 data;
233 int result;
234
235 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
236 TWSI_CTL_ENAB | TWSI_CTL_STA);
237
238 result = octeon_i2c_wait(i2c);
239 if (result) {
240 if (octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT) == STAT_IDLE) {
241 /*
242 * Controller refused to send start flag May
243 * be a client is holding SDA low - let's try
244 * to free it.
245 */
246 octeon_i2c_unblock(i2c);
247 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
248 TWSI_CTL_ENAB | TWSI_CTL_STA);
249
250 result = octeon_i2c_wait(i2c);
251 }
252 if (result)
253 return result;
254 }
255
256 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
257 if ((data != STAT_START) && (data != STAT_RSTART)) {
258 dev_err(i2c->dev, "%s: bad status (0x%x)\n", __func__, data);
259 return -EIO;
260 }
261
262 return 0;
263}
264
265/**
266 * octeon_i2c_stop - send STOP to the bus.
267 * @i2c: The struct octeon_i2c.
268 *
269 * Returns 0 on success, otherwise a negative errno.
270 */
271static int octeon_i2c_stop(struct octeon_i2c *i2c)
272{
273 u8 data;
274
275 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
276 TWSI_CTL_ENAB | TWSI_CTL_STP);
277
278 data = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
279
280 if (data != STAT_IDLE) {
281 dev_err(i2c->dev, "%s: bad status(0x%x)\n", __func__, data);
282 return -EIO;
283 }
284 return 0;
285}
286
287/**
288 * octeon_i2c_write - send data to the bus.
289 * @i2c: The struct octeon_i2c.
290 * @target: Target address.
291 * @data: Pointer to the data to be sent.
292 * @length: Length of the data.
293 *
294 * The address is sent over the bus, then the data.
295 *
296 * Returns 0 on success, otherwise a negative errno.
297 */
298static int octeon_i2c_write(struct octeon_i2c *i2c, int target,
299 const u8 *data, int length)
300{
301 int i, result;
302 u8 tmp;
303
304 result = octeon_i2c_start(i2c);
305 if (result)
306 return result;
307
308 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, target << 1);
309 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
310
311 result = octeon_i2c_wait(i2c);
312 if (result)
313 return result;
314
315 for (i = 0; i < length; i++) {
316 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
317 if ((tmp != STAT_TXADDR_ACK) && (tmp != STAT_TXDATA_ACK)) {
318 dev_err(i2c->dev,
319 "%s: bad status before write (0x%x)\n",
320 __func__, tmp);
321 return -EIO;
322 }
323
324 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, data[i]);
325 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
326
327 result = octeon_i2c_wait(i2c);
328 if (result)
329 return result;
330 }
331
332 return 0;
333}
334
335/**
336 * octeon_i2c_read - receive data from the bus.
337 * @i2c: The struct octeon_i2c.
338 * @target: Target address.
339 * @data: Pointer to the location to store the datae .
340 * @length: Length of the data.
341 *
342 * The address is sent over the bus, then the data is read.
343 *
344 * Returns 0 on success, otherwise a negative errno.
345 */
346static int octeon_i2c_read(struct octeon_i2c *i2c, int target,
347 u8 *data, int length)
348{
349 int i, result;
350 u8 tmp;
351
352 if (length < 1)
353 return -EINVAL;
354
355 result = octeon_i2c_start(i2c);
356 if (result)
357 return result;
358
359 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_DATA, (target<<1) | 1);
360 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
361
362 result = octeon_i2c_wait(i2c);
363 if (result)
364 return result;
365
366 for (i = 0; i < length; i++) {
367 tmp = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
368 if ((tmp != STAT_RXDATA_ACK) && (tmp != STAT_RXADDR_ACK)) {
369 dev_err(i2c->dev,
370 "%s: bad status before read (0x%x)\n",
371 __func__, tmp);
372 return -EIO;
373 }
374
375 if (i+1 < length)
376 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
377 TWSI_CTL_ENAB | TWSI_CTL_AAK);
378 else
379 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL,
380 TWSI_CTL_ENAB);
381
382 result = octeon_i2c_wait(i2c);
383 if (result)
384 return result;
385
386 data[i] = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_DATA);
387 }
388 return 0;
389}
390
391/**
392 * octeon_i2c_xfer - The driver's master_xfer function.
393 * @adap: Pointer to the i2c_adapter structure.
394 * @msgs: Pointer to the messages to be processed.
395 * @num: Length of the MSGS array.
396 *
397 * Returns the number of messages processed, or a negative errno on
398 * failure.
399 */
400static int octeon_i2c_xfer(struct i2c_adapter *adap,
401 struct i2c_msg *msgs,
402 int num)
403{
404 struct i2c_msg *pmsg;
405 int i;
406 int ret = 0;
407 struct octeon_i2c *i2c = i2c_get_adapdata(adap);
408
409 for (i = 0; ret == 0 && i < num; i++) {
410 pmsg = &msgs[i];
411 dev_dbg(i2c->dev,
412 "Doing %s %d byte(s) to/from 0x%02x - %d of %d messages\n",
413 pmsg->flags & I2C_M_RD ? "read" : "write",
414 pmsg->len, pmsg->addr, i + 1, num);
415 if (pmsg->flags & I2C_M_RD)
416 ret = octeon_i2c_read(i2c, pmsg->addr, pmsg->buf,
417 pmsg->len);
418 else
419 ret = octeon_i2c_write(i2c, pmsg->addr, pmsg->buf,
420 pmsg->len);
421 }
422 octeon_i2c_stop(i2c);
423
424 return (ret != 0) ? ret : num;
425}
426
427static u32 octeon_i2c_functionality(struct i2c_adapter *adap)
428{
429 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
430}
431
432static const struct i2c_algorithm octeon_i2c_algo = {
433 .master_xfer = octeon_i2c_xfer,
434 .functionality = octeon_i2c_functionality,
435};
436
437static struct i2c_adapter octeon_i2c_ops = {
438 .owner = THIS_MODULE,
439 .name = "OCTEON adapter",
440 .algo = &octeon_i2c_algo,
441 .timeout = HZ / 50,
442};
443
444/**
445 * octeon_i2c_setclock - Calculate and set clock divisors.
446 */
447static int octeon_i2c_setclock(struct octeon_i2c *i2c)
448{
449 int tclk, thp_base, inc, thp_idx, mdiv_idx, ndiv_idx, foscl, diff;
450 int thp = 0x18, mdiv = 2, ndiv = 0, delta_hz = 1000000;
451
452 for (ndiv_idx = 0; ndiv_idx < 8 && delta_hz != 0; ndiv_idx++) {
453 /*
454 * An mdiv value of less than 2 seems to not work well
455 * with ds1337 RTCs, so we constrain it to larger
456 * values.
457 */
458 for (mdiv_idx = 15; mdiv_idx >= 2 && delta_hz != 0; mdiv_idx--) {
459 /*
460 * For given ndiv and mdiv values check the
461 * two closest thp values.
462 */
463 tclk = i2c->twsi_freq * (mdiv_idx + 1) * 10;
464 tclk *= (1 << ndiv_idx);
465 thp_base = (i2c->sys_freq / (tclk * 2)) - 1;
466 for (inc = 0; inc <= 1; inc++) {
467 thp_idx = thp_base + inc;
468 if (thp_idx < 5 || thp_idx > 0xff)
469 continue;
470
471 foscl = i2c->sys_freq / (2 * (thp_idx + 1));
472 foscl = foscl / (1 << ndiv_idx);
473 foscl = foscl / (mdiv_idx + 1) / 10;
474 diff = abs(foscl - i2c->twsi_freq);
475 if (diff < delta_hz) {
476 delta_hz = diff;
477 thp = thp_idx;
478 mdiv = mdiv_idx;
479 ndiv = ndiv_idx;
480 }
481 }
482 }
483 }
484 octeon_i2c_write_sw(i2c, SW_TWSI_OP_TWSI_CLK, thp);
485 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CLKCTL, (mdiv << 3) | ndiv);
486
487 return 0;
488}
489
490static int octeon_i2c_initlowlevel(struct octeon_i2c *i2c)
491{
492 u8 status;
493 int tries;
494
495 /* disable high level controller, enable bus access */
496 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_CTL, TWSI_CTL_ENAB);
497
498 /* reset controller */
499 octeon_i2c_write_sw(i2c, SW_TWSI_EOP_TWSI_RST, 0);
500
501 for (tries = 10; tries; tries--) {
502 udelay(1);
503 status = octeon_i2c_read_sw(i2c, SW_TWSI_EOP_TWSI_STAT);
504 if (status == STAT_IDLE)
505 return 0;
506 }
507 dev_err(i2c->dev, "%s: TWSI_RST failed! (0x%x)\n", __func__, status);
508 return -EIO;
509}
510
511static int octeon_i2c_probe(struct platform_device *pdev)
512{
513 int irq, result = 0;
514 struct octeon_i2c *i2c;
515 struct resource *res_mem;
516
517 /* All adaptors have an irq. */
518 irq = platform_get_irq(pdev, 0);
519 if (irq < 0)
520 return irq;
521
522 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
523 if (!i2c) {
524 dev_err(&pdev->dev, "kzalloc failed\n");
525 result = -ENOMEM;
526 goto out;
527 }
528 i2c->dev = &pdev->dev;
529
530 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
531
532 if (res_mem == NULL) {
533 dev_err(i2c->dev, "found no memory resource\n");
534 result = -ENXIO;
535 goto out;
536 }
537 i2c->twsi_phys = res_mem->start;
538 i2c->regsize = resource_size(res_mem);
539
540 /*
541 * "clock-rate" is a legacy binding, the official binding is
542 * "clock-frequency". Try the official one first and then
543 * fall back if it doesn't exist.
544 */
545 if (of_property_read_u32(pdev->dev.of_node,
546 "clock-frequency", &i2c->twsi_freq) &&
547 of_property_read_u32(pdev->dev.of_node,
548 "clock-rate", &i2c->twsi_freq)) {
549 dev_err(i2c->dev,
550 "no I2C 'clock-rate' or 'clock-frequency' property\n");
551 result = -ENXIO;
552 goto out;
553 }
554
555 i2c->sys_freq = octeon_get_io_clock_rate();
556
557 if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
558 res_mem->name)) {
559 dev_err(i2c->dev, "request_mem_region failed\n");
560 goto out;
561 }
562 i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
563
564 init_waitqueue_head(&i2c->queue);
565
566 i2c->irq = irq;
567
568 result = devm_request_irq(&pdev->dev, i2c->irq,
569 octeon_i2c_isr, 0, DRV_NAME, i2c);
570 if (result < 0) {
571 dev_err(i2c->dev, "failed to attach interrupt\n");
572 goto out;
573 }
574
575 result = octeon_i2c_initlowlevel(i2c);
576 if (result) {
577 dev_err(i2c->dev, "init low level failed\n");
578 goto out;
579 }
580
581 result = octeon_i2c_setclock(i2c);
582 if (result) {
583 dev_err(i2c->dev, "clock init failed\n");
584 goto out;
585 }
586
587 i2c->adap = octeon_i2c_ops;
588 i2c->adap.dev.parent = &pdev->dev;
589 i2c->adap.dev.of_node = pdev->dev.of_node;
590 i2c_set_adapdata(&i2c->adap, i2c);
591 platform_set_drvdata(pdev, i2c);
592
593 result = i2c_add_adapter(&i2c->adap);
594 if (result < 0) {
595 dev_err(i2c->dev, "failed to add adapter\n");
596 goto out;
597 }
598 dev_info(i2c->dev, "version %s\n", DRV_VERSION);
599
600 return 0;
601
602out:
603 return result;
604};
605
606static int octeon_i2c_remove(struct platform_device *pdev)
607{
608 struct octeon_i2c *i2c = platform_get_drvdata(pdev);
609
610 i2c_del_adapter(&i2c->adap);
611 return 0;
612};
613
614static struct of_device_id octeon_i2c_match[] = {
615 {
616 .compatible = "cavium,octeon-3860-twsi",
617 },
618 {},
619};
620MODULE_DEVICE_TABLE(of, octeon_i2c_match);
621
622static struct platform_driver octeon_i2c_driver = {
623 .probe = octeon_i2c_probe,
624 .remove = octeon_i2c_remove,
625 .driver = {
626 .owner = THIS_MODULE,
627 .name = DRV_NAME,
628 .of_match_table = octeon_i2c_match,
629 },
630};
631
632module_platform_driver(octeon_i2c_driver);
633
634MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
635MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
636MODULE_LICENSE("GPL");
637MODULE_VERSION(DRV_VERSION);