1/*
   2 * Copyright 2007-8 Advanced Micro Devices, Inc.
   3 * Copyright 2008 Red Hat Inc.
   4 *
   5 * Permission is hereby granted, free of charge, to any person obtaining a
   6 * copy of this software and associated documentation files (the "Software"),
   7 * to deal in the Software without restriction, including without limitation
   8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9 * and/or sell copies of the Software, and to permit persons to whom the
  10 * Software is furnished to do so, subject to the following conditions:
  11 *
  12 * The above copyright notice and this permission notice shall be included in
  13 * all copies or substantial portions of the Software.
  14 *
  15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21 * OTHER DEALINGS IN THE SOFTWARE.
  22 *
  23 * Authors: Dave Airlie
  24 *          Alex Deucher
  25 */
  26#include "drmP.h"
  27#include "drm_crtc_helper.h"
  28#include "radeon_drm.h"
  29#include "radeon.h"
  30#include "atom.h"
  31#include <linux/backlight.h>
  32#ifdef CONFIG_PMAC_BACKLIGHT
  33#include <asm/backlight.h>
  34#endif
  35
  36static void radeon_legacy_encoder_disable(struct drm_encoder *encoder)
  37{
  38	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  39	struct drm_encoder_helper_funcs *encoder_funcs;
  40
  41	encoder_funcs = encoder->helper_private;
  42	encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
  43	radeon_encoder->active_device = 0;
  44}
  45
  46static void radeon_legacy_lvds_update(struct drm_encoder *encoder, int mode)
  47{
  48	struct drm_device *dev = encoder->dev;
  49	struct radeon_device *rdev = dev->dev_private;
  50	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
  51	uint32_t lvds_gen_cntl, lvds_pll_cntl, pixclks_cntl, disp_pwr_man;
  52	int panel_pwr_delay = 2000;
  53	bool is_mac = false;
  54	uint8_t backlight_level;
  55	DRM_DEBUG_KMS("\n");
  56
  57	lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
  58	backlight_level = (lvds_gen_cntl >> RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
  59
  60	if (radeon_encoder->enc_priv) {
  61		if (rdev->is_atom_bios) {
  62			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
  63			panel_pwr_delay = lvds->panel_pwr_delay;
  64			if (lvds->bl_dev)
  65				backlight_level = lvds->backlight_level;
  66		} else {
  67			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
  68			panel_pwr_delay = lvds->panel_pwr_delay;
  69			if (lvds->bl_dev)
  70				backlight_level = lvds->backlight_level;
  71		}
  72	}
  73
  74	/* macs (and possibly some x86 oem systems?) wire up LVDS strangely
  75	 * Taken from radeonfb.
  76	 */
  77	if ((rdev->mode_info.connector_table == CT_IBOOK) ||
  78	    (rdev->mode_info.connector_table == CT_POWERBOOK_EXTERNAL) ||
  79	    (rdev->mode_info.connector_table == CT_POWERBOOK_INTERNAL) ||
  80	    (rdev->mode_info.connector_table == CT_POWERBOOK_VGA))
  81		is_mac = true;
  82
  83	switch (mode) {
  84	case DRM_MODE_DPMS_ON:
  85		disp_pwr_man = RREG32(RADEON_DISP_PWR_MAN);
  86		disp_pwr_man |= RADEON_AUTO_PWRUP_EN;
  87		WREG32(RADEON_DISP_PWR_MAN, disp_pwr_man);
  88		lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  89		lvds_pll_cntl |= RADEON_LVDS_PLL_EN;
  90		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  91		udelay(1000);
  92
  93		lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
  94		lvds_pll_cntl &= ~RADEON_LVDS_PLL_RESET;
  95		WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
  96
  97		lvds_gen_cntl &= ~(RADEON_LVDS_DISPLAY_DIS |
  98				   RADEON_LVDS_BL_MOD_LEVEL_MASK);
  99		lvds_gen_cntl |= (RADEON_LVDS_ON | RADEON_LVDS_EN |
 100				  RADEON_LVDS_DIGON | RADEON_LVDS_BLON |
 101				  (backlight_level << RADEON_LVDS_BL_MOD_LEVEL_SHIFT));
 102		if (is_mac)
 103			lvds_gen_cntl |= RADEON_LVDS_BL_MOD_EN;
 104		udelay(panel_pwr_delay * 1000);
 105		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 106		break;
 107	case DRM_MODE_DPMS_STANDBY:
 108	case DRM_MODE_DPMS_SUSPEND:
 109	case DRM_MODE_DPMS_OFF:
 110		pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
 111		WREG32_PLL_P(RADEON_PIXCLKS_CNTL, 0, ~RADEON_PIXCLK_LVDS_ALWAYS_ONb);
 112		lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 113		if (is_mac) {
 114			lvds_gen_cntl &= ~RADEON_LVDS_BL_MOD_EN;
 115			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 116			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_EN);
 117		} else {
 118			WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 119			lvds_gen_cntl &= ~(RADEON_LVDS_ON | RADEON_LVDS_BLON | RADEON_LVDS_EN | RADEON_LVDS_DIGON);
 120		}
 121		udelay(panel_pwr_delay * 1000);
 122		WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 123		WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
 124		udelay(panel_pwr_delay * 1000);
 125		break;
 126	}
 127
 128	if (rdev->is_atom_bios)
 129		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 130	else
 131		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 132
 133}
 134
 135static void radeon_legacy_lvds_dpms(struct drm_encoder *encoder, int mode)
 136{
 137	struct radeon_device *rdev = encoder->dev->dev_private;
 138	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 139	DRM_DEBUG("\n");
 140
 141	if (radeon_encoder->enc_priv) {
 142		if (rdev->is_atom_bios) {
 143			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 144			lvds->dpms_mode = mode;
 145		} else {
 146			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 147			lvds->dpms_mode = mode;
 148		}
 149	}
 150
 151	radeon_legacy_lvds_update(encoder, mode);
 152}
 153
 154static void radeon_legacy_lvds_prepare(struct drm_encoder *encoder)
 155{
 156	struct radeon_device *rdev = encoder->dev->dev_private;
 157
 158	if (rdev->is_atom_bios)
 159		radeon_atom_output_lock(encoder, true);
 160	else
 161		radeon_combios_output_lock(encoder, true);
 162	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_OFF);
 163}
 164
 165static void radeon_legacy_lvds_commit(struct drm_encoder *encoder)
 166{
 167	struct radeon_device *rdev = encoder->dev->dev_private;
 168
 169	radeon_legacy_lvds_dpms(encoder, DRM_MODE_DPMS_ON);
 170	if (rdev->is_atom_bios)
 171		radeon_atom_output_lock(encoder, false);
 172	else
 173		radeon_combios_output_lock(encoder, false);
 174}
 175
 176static void radeon_legacy_lvds_mode_set(struct drm_encoder *encoder,
 177					struct drm_display_mode *mode,
 178					struct drm_display_mode *adjusted_mode)
 179{
 180	struct drm_device *dev = encoder->dev;
 181	struct radeon_device *rdev = dev->dev_private;
 182	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 183	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 184	uint32_t lvds_pll_cntl, lvds_gen_cntl, lvds_ss_gen_cntl;
 185
 186	DRM_DEBUG_KMS("\n");
 187
 188	lvds_pll_cntl = RREG32(RADEON_LVDS_PLL_CNTL);
 189	lvds_pll_cntl &= ~RADEON_LVDS_PLL_EN;
 190
 191	lvds_ss_gen_cntl = RREG32(RADEON_LVDS_SS_GEN_CNTL);
 192	if (rdev->is_atom_bios) {
 193		/* LVDS_GEN_CNTL parameters are computed in LVDSEncoderControl
 194		 * need to call that on resume to set up the reg properly.
 195		 */
 196		radeon_encoder->pixel_clock = adjusted_mode->clock;
 197		atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
 198		lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 199	} else {
 200		struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
 201		if (lvds) {
 202			DRM_DEBUG_KMS("bios LVDS_GEN_CNTL: 0x%x\n", lvds->lvds_gen_cntl);
 203			lvds_gen_cntl = lvds->lvds_gen_cntl;
 204			lvds_ss_gen_cntl &= ~((0xf << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 205					      (0xf << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 206			lvds_ss_gen_cntl |= ((lvds->panel_digon_delay << RADEON_LVDS_PWRSEQ_DELAY1_SHIFT) |
 207					     (lvds->panel_blon_delay << RADEON_LVDS_PWRSEQ_DELAY2_SHIFT));
 208		} else
 209			lvds_gen_cntl = RREG32(RADEON_LVDS_GEN_CNTL);
 210	}
 211	lvds_gen_cntl |= RADEON_LVDS_DISPLAY_DIS;
 212	lvds_gen_cntl &= ~(RADEON_LVDS_ON |
 213			   RADEON_LVDS_BLON |
 214			   RADEON_LVDS_EN |
 215			   RADEON_LVDS_RST_FM);
 216
 217	if (ASIC_IS_R300(rdev))
 218		lvds_pll_cntl &= ~(R300_LVDS_SRC_SEL_MASK);
 219
 220	if (radeon_crtc->crtc_id == 0) {
 221		if (ASIC_IS_R300(rdev)) {
 222			if (radeon_encoder->rmx_type != RMX_OFF)
 223				lvds_pll_cntl |= R300_LVDS_SRC_SEL_RMX;
 224		} else
 225			lvds_gen_cntl &= ~RADEON_LVDS_SEL_CRTC2;
 226	} else {
 227		if (ASIC_IS_R300(rdev))
 228			lvds_pll_cntl |= R300_LVDS_SRC_SEL_CRTC2;
 229		else
 230			lvds_gen_cntl |= RADEON_LVDS_SEL_CRTC2;
 231	}
 232
 233	WREG32(RADEON_LVDS_GEN_CNTL, lvds_gen_cntl);
 234	WREG32(RADEON_LVDS_PLL_CNTL, lvds_pll_cntl);
 235	WREG32(RADEON_LVDS_SS_GEN_CNTL, lvds_ss_gen_cntl);
 236
 237	if (rdev->family == CHIP_RV410)
 238		WREG32(RADEON_CLOCK_CNTL_INDEX, 0);
 239
 240	if (rdev->is_atom_bios)
 241		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 242	else
 243		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 244}
 245
 246static bool radeon_legacy_mode_fixup(struct drm_encoder *encoder,
 247				     struct drm_display_mode *mode,
 248				     struct drm_display_mode *adjusted_mode)
 249{
 250	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 251
 252	/* set the active encoder to connector routing */
 253	radeon_encoder_set_active_device(encoder);
 254	drm_mode_set_crtcinfo(adjusted_mode, 0);
 255
 256	/* get the native mode for LVDS */
 257	if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
 258		radeon_panel_mode_fixup(encoder, adjusted_mode);
 259
 260	return true;
 261}
 262
 263static const struct drm_encoder_helper_funcs radeon_legacy_lvds_helper_funcs = {
 264	.dpms = radeon_legacy_lvds_dpms,
 265	.mode_fixup = radeon_legacy_mode_fixup,
 266	.prepare = radeon_legacy_lvds_prepare,
 267	.mode_set = radeon_legacy_lvds_mode_set,
 268	.commit = radeon_legacy_lvds_commit,
 269	.disable = radeon_legacy_encoder_disable,
 270};
 271
 272#if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
 
 
 
 
 
 273
 274#define MAX_RADEON_LEVEL 0xFF
 
 275
 276struct radeon_backlight_privdata {
 277	struct radeon_encoder *encoder;
 278	uint8_t negative;
 279};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 280
 281static uint8_t radeon_legacy_lvds_level(struct backlight_device *bd)
 282{
 283	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 284	uint8_t level;
 285
 286	/* Convert brightness to hardware level */
 287	if (bd->props.brightness < 0)
 288		level = 0;
 289	else if (bd->props.brightness > MAX_RADEON_LEVEL)
 290		level = MAX_RADEON_LEVEL;
 291	else
 292		level = bd->props.brightness;
 293
 294	if (pdata->negative)
 295		level = MAX_RADEON_LEVEL - level;
 296
 297	return level;
 298}
 299
 300static int radeon_legacy_backlight_update_status(struct backlight_device *bd)
 301{
 302	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 303	struct radeon_encoder *radeon_encoder = pdata->encoder;
 304	struct drm_device *dev = radeon_encoder->base.dev;
 305	struct radeon_device *rdev = dev->dev_private;
 306	int dpms_mode = DRM_MODE_DPMS_ON;
 307
 308	if (radeon_encoder->enc_priv) {
 309		if (rdev->is_atom_bios) {
 310			struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 311			dpms_mode = lvds->dpms_mode;
 312			lvds->backlight_level = radeon_legacy_lvds_level(bd);
 313		} else {
 314			struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 315			dpms_mode = lvds->dpms_mode;
 316			lvds->backlight_level = radeon_legacy_lvds_level(bd);
 317		}
 318	}
 319
 320	if (bd->props.brightness > 0)
 321		radeon_legacy_lvds_update(&radeon_encoder->base, dpms_mode);
 322	else
 323		radeon_legacy_lvds_update(&radeon_encoder->base, DRM_MODE_DPMS_OFF);
 324
 325	return 0;
 326}
 327
 328static int radeon_legacy_backlight_get_brightness(struct backlight_device *bd)
 329{
 330	struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 331	struct radeon_encoder *radeon_encoder = pdata->encoder;
 332	struct drm_device *dev = radeon_encoder->base.dev;
 333	struct radeon_device *rdev = dev->dev_private;
 334	uint8_t backlight_level;
 335
 336	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
 337			   RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
 338
 339	return pdata->negative ? MAX_RADEON_LEVEL - backlight_level : backlight_level;
 340}
 341
 342static const struct backlight_ops radeon_backlight_ops = {
 343	.get_brightness = radeon_legacy_backlight_get_brightness,
 344	.update_status	= radeon_legacy_backlight_update_status,
 345};
 346
 347void radeon_legacy_backlight_init(struct radeon_encoder *radeon_encoder,
 348				  struct drm_connector *drm_connector)
 349{
 350	struct drm_device *dev = radeon_encoder->base.dev;
 351	struct radeon_device *rdev = dev->dev_private;
 352	struct backlight_device *bd;
 353	struct backlight_properties props;
 354	struct radeon_backlight_privdata *pdata;
 355	uint8_t backlight_level;
 
 356
 357	if (!radeon_encoder->enc_priv)
 358		return;
 359
 360#ifdef CONFIG_PMAC_BACKLIGHT
 361	if (!pmac_has_backlight_type("ati") &&
 362	    !pmac_has_backlight_type("mnca"))
 363		return;
 364#endif
 365
 366	pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 367	if (!pdata) {
 368		DRM_ERROR("Memory allocation failed\n");
 369		goto error;
 370	}
 371
 372	props.max_brightness = MAX_RADEON_LEVEL;
 
 373	props.type = BACKLIGHT_RAW;
 374	bd = backlight_device_register("radeon_bl", &drm_connector->kdev,
 
 
 375				       pdata, &radeon_backlight_ops, &props);
 376	if (IS_ERR(bd)) {
 377		DRM_ERROR("Backlight registration failed\n");
 378		goto error;
 379	}
 380
 381	pdata->encoder = radeon_encoder;
 382
 383	backlight_level = (RREG32(RADEON_LVDS_GEN_CNTL) >>
 384			   RADEON_LVDS_BL_MOD_LEVEL_SHIFT) & 0xff;
 385
 386	/* First, try to detect backlight level sense based on the assumption
 387	 * that firmware set it up at full brightness
 388	 */
 389	if (backlight_level == 0)
 390		pdata->negative = true;
 391	else if (backlight_level == 0xff)
 392		pdata->negative = false;
 393	else {
 394		/* XXX hack... maybe some day we can figure out in what direction
 395		 * backlight should work on a given panel?
 396		 */
 397		pdata->negative = (rdev->family != CHIP_RV200 &&
 398				   rdev->family != CHIP_RV250 &&
 399				   rdev->family != CHIP_RV280 &&
 400				   rdev->family != CHIP_RV350);
 401
 402#ifdef CONFIG_PMAC_BACKLIGHT
 403		pdata->negative = (pdata->negative ||
 404				   of_machine_is_compatible("PowerBook4,3") ||
 405				   of_machine_is_compatible("PowerBook6,3") ||
 406				   of_machine_is_compatible("PowerBook6,5"));
 407#endif
 408	}
 409
 410	if (rdev->is_atom_bios) {
 411		struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 412		lvds->bl_dev = bd;
 413	} else {
 414		struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 415		lvds->bl_dev = bd;
 416	}
 417
 418	bd->props.brightness = radeon_legacy_backlight_get_brightness(bd);
 419	bd->props.power = FB_BLANK_UNBLANK;
 420	backlight_update_status(bd);
 421
 422	DRM_INFO("radeon legacy LVDS backlight initialized\n");
 423
 424	return;
 425
 426error:
 427	kfree(pdata);
 428	return;
 429}
 430
 431static void radeon_legacy_backlight_exit(struct radeon_encoder *radeon_encoder)
 432{
 433	struct drm_device *dev = radeon_encoder->base.dev;
 434	struct radeon_device *rdev = dev->dev_private;
 435	struct backlight_device *bd = NULL;
 436
 437	if (!radeon_encoder->enc_priv)
 438		return;
 439
 440	if (rdev->is_atom_bios) {
 441		struct radeon_encoder_atom_dig *lvds = radeon_encoder->enc_priv;
 442		bd = lvds->bl_dev;
 443		lvds->bl_dev = NULL;
 444	} else {
 445		struct radeon_encoder_lvds *lvds = radeon_encoder->enc_priv;
 446		bd = lvds->bl_dev;
 447		lvds->bl_dev = NULL;
 448	}
 449
 450	if (bd) {
 451		struct radeon_legacy_backlight_privdata *pdata;
 452
 453		pdata = bl_get_data(bd);
 454		backlight_device_unregister(bd);
 455		kfree(pdata);
 456
 457		DRM_INFO("radeon legacy LVDS backlight unloaded\n");
 458	}
 459}
 460
 461#else /* !CONFIG_BACKLIGHT_CLASS_DEVICE */
 462
 463void radeon_legacy_backlight_init(struct radeon_encoder *encoder)
 464{
 465}
 466
 467static void radeon_legacy_backlight_exit(struct radeon_encoder *encoder)
 468{
 469}
 470
 471#endif
 472
 473
 474static void radeon_lvds_enc_destroy(struct drm_encoder *encoder)
 475{
 476	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 477
 478	if (radeon_encoder->enc_priv) {
 479		radeon_legacy_backlight_exit(radeon_encoder);
 480		kfree(radeon_encoder->enc_priv);
 481	}
 482	drm_encoder_cleanup(encoder);
 483	kfree(radeon_encoder);
 484}
 485
 486static const struct drm_encoder_funcs radeon_legacy_lvds_enc_funcs = {
 487	.destroy = radeon_lvds_enc_destroy,
 488};
 489
 490static void radeon_legacy_primary_dac_dpms(struct drm_encoder *encoder, int mode)
 491{
 492	struct drm_device *dev = encoder->dev;
 493	struct radeon_device *rdev = dev->dev_private;
 494	uint32_t crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 495	uint32_t dac_cntl = RREG32(RADEON_DAC_CNTL);
 496	uint32_t dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 497
 498	DRM_DEBUG_KMS("\n");
 499
 500	switch (mode) {
 501	case DRM_MODE_DPMS_ON:
 502		crtc_ext_cntl |= RADEON_CRTC_CRT_ON;
 503		dac_cntl &= ~RADEON_DAC_PDWN;
 504		dac_macro_cntl &= ~(RADEON_DAC_PDWN_R |
 505				    RADEON_DAC_PDWN_G |
 506				    RADEON_DAC_PDWN_B);
 507		break;
 508	case DRM_MODE_DPMS_STANDBY:
 509	case DRM_MODE_DPMS_SUSPEND:
 510	case DRM_MODE_DPMS_OFF:
 511		crtc_ext_cntl &= ~RADEON_CRTC_CRT_ON;
 512		dac_cntl |= RADEON_DAC_PDWN;
 513		dac_macro_cntl |= (RADEON_DAC_PDWN_R |
 514				   RADEON_DAC_PDWN_G |
 515				   RADEON_DAC_PDWN_B);
 516		break;
 517	}
 518
 519	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 
 
 520	WREG32(RADEON_DAC_CNTL, dac_cntl);
 521	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 522
 523	if (rdev->is_atom_bios)
 524		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 525	else
 526		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 527
 528}
 529
 530static void radeon_legacy_primary_dac_prepare(struct drm_encoder *encoder)
 531{
 532	struct radeon_device *rdev = encoder->dev->dev_private;
 533
 534	if (rdev->is_atom_bios)
 535		radeon_atom_output_lock(encoder, true);
 536	else
 537		radeon_combios_output_lock(encoder, true);
 538	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
 539}
 540
 541static void radeon_legacy_primary_dac_commit(struct drm_encoder *encoder)
 542{
 543	struct radeon_device *rdev = encoder->dev->dev_private;
 544
 545	radeon_legacy_primary_dac_dpms(encoder, DRM_MODE_DPMS_ON);
 546
 547	if (rdev->is_atom_bios)
 548		radeon_atom_output_lock(encoder, false);
 549	else
 550		radeon_combios_output_lock(encoder, false);
 551}
 552
 553static void radeon_legacy_primary_dac_mode_set(struct drm_encoder *encoder,
 554					       struct drm_display_mode *mode,
 555					       struct drm_display_mode *adjusted_mode)
 556{
 557	struct drm_device *dev = encoder->dev;
 558	struct radeon_device *rdev = dev->dev_private;
 559	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 560	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 561	uint32_t disp_output_cntl, dac_cntl, dac2_cntl, dac_macro_cntl;
 562
 563	DRM_DEBUG_KMS("\n");
 564
 565	if (radeon_crtc->crtc_id == 0) {
 566		if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 567			disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 568				~(RADEON_DISP_DAC_SOURCE_MASK);
 569			WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 570		} else {
 571			dac2_cntl = RREG32(RADEON_DAC_CNTL2)  & ~(RADEON_DAC2_DAC_CLK_SEL);
 572			WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 573		}
 574	} else {
 575		if (rdev->family == CHIP_R200 || ASIC_IS_R300(rdev)) {
 576			disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL) &
 577				~(RADEON_DISP_DAC_SOURCE_MASK);
 578			disp_output_cntl |= RADEON_DISP_DAC_SOURCE_CRTC2;
 579			WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
 580		} else {
 581			dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC_CLK_SEL;
 582			WREG32(RADEON_DAC_CNTL2, dac2_cntl);
 583		}
 584	}
 585
 586	dac_cntl = (RADEON_DAC_MASK_ALL |
 587		    RADEON_DAC_VGA_ADR_EN |
 588		    /* TODO 6-bits */
 589		    RADEON_DAC_8BIT_EN);
 590
 591	WREG32_P(RADEON_DAC_CNTL,
 592		       dac_cntl,
 593		       RADEON_DAC_RANGE_CNTL |
 594		       RADEON_DAC_BLANKING);
 595
 596	if (radeon_encoder->enc_priv) {
 597		struct radeon_encoder_primary_dac *p_dac = (struct radeon_encoder_primary_dac *)radeon_encoder->enc_priv;
 598		dac_macro_cntl = p_dac->ps2_pdac_adj;
 599	} else
 600		dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 601	dac_macro_cntl |= RADEON_DAC_PDWN_R | RADEON_DAC_PDWN_G | RADEON_DAC_PDWN_B;
 602	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 603
 604	if (rdev->is_atom_bios)
 605		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 606	else
 607		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 608}
 609
 610static enum drm_connector_status radeon_legacy_primary_dac_detect(struct drm_encoder *encoder,
 611								  struct drm_connector *connector)
 612{
 613	struct drm_device *dev = encoder->dev;
 614	struct radeon_device *rdev = dev->dev_private;
 615	uint32_t vclk_ecp_cntl, crtc_ext_cntl;
 616	uint32_t dac_ext_cntl, dac_cntl, dac_macro_cntl, tmp;
 617	enum drm_connector_status found = connector_status_disconnected;
 618	bool color = true;
 619
 
 
 
 
 
 
 
 
 620	/* save the regs we need */
 621	vclk_ecp_cntl = RREG32_PLL(RADEON_VCLK_ECP_CNTL);
 622	crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
 623	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
 624	dac_cntl = RREG32(RADEON_DAC_CNTL);
 625	dac_macro_cntl = RREG32(RADEON_DAC_MACRO_CNTL);
 626
 627	tmp = vclk_ecp_cntl &
 628		~(RADEON_PIXCLK_ALWAYS_ONb | RADEON_PIXCLK_DAC_ALWAYS_ONb);
 629	WREG32_PLL(RADEON_VCLK_ECP_CNTL, tmp);
 630
 631	tmp = crtc_ext_cntl | RADEON_CRTC_CRT_ON;
 632	WREG32(RADEON_CRTC_EXT_CNTL, tmp);
 633
 634	tmp = RADEON_DAC_FORCE_BLANK_OFF_EN |
 635		RADEON_DAC_FORCE_DATA_EN;
 636
 637	if (color)
 638		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
 639	else
 640		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
 641
 642	if (ASIC_IS_R300(rdev))
 643		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
 
 
 644	else
 645		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
 646
 647	WREG32(RADEON_DAC_EXT_CNTL, tmp);
 648
 649	tmp = dac_cntl & ~(RADEON_DAC_RANGE_CNTL_MASK | RADEON_DAC_PDWN);
 650	tmp |= RADEON_DAC_RANGE_CNTL_PS2 | RADEON_DAC_CMP_EN;
 651	WREG32(RADEON_DAC_CNTL, tmp);
 652
 
 653	tmp &= ~(RADEON_DAC_PDWN_R |
 654		 RADEON_DAC_PDWN_G |
 655		 RADEON_DAC_PDWN_B);
 656
 657	WREG32(RADEON_DAC_MACRO_CNTL, tmp);
 658
 659	udelay(2000);
 660
 661	if (RREG32(RADEON_DAC_CNTL) & RADEON_DAC_CMP_OUTPUT)
 662		found = connector_status_connected;
 663
 664	/* restore the regs we used */
 665	WREG32(RADEON_DAC_CNTL, dac_cntl);
 666	WREG32(RADEON_DAC_MACRO_CNTL, dac_macro_cntl);
 667	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
 668	WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
 669	WREG32_PLL(RADEON_VCLK_ECP_CNTL, vclk_ecp_cntl);
 670
 671	return found;
 672}
 673
 674static const struct drm_encoder_helper_funcs radeon_legacy_primary_dac_helper_funcs = {
 675	.dpms = radeon_legacy_primary_dac_dpms,
 676	.mode_fixup = radeon_legacy_mode_fixup,
 677	.prepare = radeon_legacy_primary_dac_prepare,
 678	.mode_set = radeon_legacy_primary_dac_mode_set,
 679	.commit = radeon_legacy_primary_dac_commit,
 680	.detect = radeon_legacy_primary_dac_detect,
 681	.disable = radeon_legacy_encoder_disable,
 682};
 683
 684
 685static const struct drm_encoder_funcs radeon_legacy_primary_dac_enc_funcs = {
 686	.destroy = radeon_enc_destroy,
 687};
 688
 689static void radeon_legacy_tmds_int_dpms(struct drm_encoder *encoder, int mode)
 690{
 691	struct drm_device *dev = encoder->dev;
 692	struct radeon_device *rdev = dev->dev_private;
 693	uint32_t fp_gen_cntl = RREG32(RADEON_FP_GEN_CNTL);
 694	DRM_DEBUG_KMS("\n");
 695
 696	switch (mode) {
 697	case DRM_MODE_DPMS_ON:
 698		fp_gen_cntl |= (RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 699		break;
 700	case DRM_MODE_DPMS_STANDBY:
 701	case DRM_MODE_DPMS_SUSPEND:
 702	case DRM_MODE_DPMS_OFF:
 703		fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 704		break;
 705	}
 706
 707	WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 708
 709	if (rdev->is_atom_bios)
 710		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 711	else
 712		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 713
 714}
 715
 716static void radeon_legacy_tmds_int_prepare(struct drm_encoder *encoder)
 717{
 718	struct radeon_device *rdev = encoder->dev->dev_private;
 719
 720	if (rdev->is_atom_bios)
 721		radeon_atom_output_lock(encoder, true);
 722	else
 723		radeon_combios_output_lock(encoder, true);
 724	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_OFF);
 725}
 726
 727static void radeon_legacy_tmds_int_commit(struct drm_encoder *encoder)
 728{
 729	struct radeon_device *rdev = encoder->dev->dev_private;
 730
 731	radeon_legacy_tmds_int_dpms(encoder, DRM_MODE_DPMS_ON);
 732
 733	if (rdev->is_atom_bios)
 734		radeon_atom_output_lock(encoder, true);
 735	else
 736		radeon_combios_output_lock(encoder, true);
 737}
 738
 739static void radeon_legacy_tmds_int_mode_set(struct drm_encoder *encoder,
 740					    struct drm_display_mode *mode,
 741					    struct drm_display_mode *adjusted_mode)
 742{
 743	struct drm_device *dev = encoder->dev;
 744	struct radeon_device *rdev = dev->dev_private;
 745	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 746	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 747	uint32_t tmp, tmds_pll_cntl, tmds_transmitter_cntl, fp_gen_cntl;
 748	int i;
 749
 750	DRM_DEBUG_KMS("\n");
 751
 752	tmp = tmds_pll_cntl = RREG32(RADEON_TMDS_PLL_CNTL);
 753	tmp &= 0xfffff;
 754	if (rdev->family == CHIP_RV280) {
 755		/* bit 22 of TMDS_PLL_CNTL is read-back inverted */
 756		tmp ^= (1 << 22);
 757		tmds_pll_cntl ^= (1 << 22);
 758	}
 759
 760	if (radeon_encoder->enc_priv) {
 761		struct radeon_encoder_int_tmds *tmds = (struct radeon_encoder_int_tmds *)radeon_encoder->enc_priv;
 762
 763		for (i = 0; i < 4; i++) {
 764			if (tmds->tmds_pll[i].freq == 0)
 765				break;
 766			if ((uint32_t)(mode->clock / 10) < tmds->tmds_pll[i].freq) {
 767				tmp = tmds->tmds_pll[i].value ;
 768				break;
 769			}
 770		}
 771	}
 772
 773	if (ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV280)) {
 774		if (tmp & 0xfff00000)
 775			tmds_pll_cntl = tmp;
 776		else {
 777			tmds_pll_cntl &= 0xfff00000;
 778			tmds_pll_cntl |= tmp;
 779		}
 780	} else
 781		tmds_pll_cntl = tmp;
 782
 783	tmds_transmitter_cntl = RREG32(RADEON_TMDS_TRANSMITTER_CNTL) &
 784		~(RADEON_TMDS_TRANSMITTER_PLLRST);
 785
 786    if (rdev->family == CHIP_R200 ||
 787	rdev->family == CHIP_R100 ||
 788	ASIC_IS_R300(rdev))
 789	    tmds_transmitter_cntl &= ~(RADEON_TMDS_TRANSMITTER_PLLEN);
 790    else /* RV chips got this bit reversed */
 791	    tmds_transmitter_cntl |= RADEON_TMDS_TRANSMITTER_PLLEN;
 792
 793    fp_gen_cntl = (RREG32(RADEON_FP_GEN_CNTL) |
 794		   (RADEON_FP_CRTC_DONT_SHADOW_VPAR |
 795		    RADEON_FP_CRTC_DONT_SHADOW_HEND));
 796
 797    fp_gen_cntl &= ~(RADEON_FP_FPON | RADEON_FP_TMDS_EN);
 798
 799    fp_gen_cntl &= ~(RADEON_FP_RMX_HVSYNC_CONTROL_EN |
 800		     RADEON_FP_DFP_SYNC_SEL |
 801		     RADEON_FP_CRT_SYNC_SEL |
 802		     RADEON_FP_CRTC_LOCK_8DOT |
 803		     RADEON_FP_USE_SHADOW_EN |
 804		     RADEON_FP_CRTC_USE_SHADOW_VEND |
 805		     RADEON_FP_CRT_SYNC_ALT);
 806
 807    if (1) /*  FIXME rgbBits == 8 */
 808	    fp_gen_cntl |= RADEON_FP_PANEL_FORMAT;  /* 24 bit format */
 809    else
 810	    fp_gen_cntl &= ~RADEON_FP_PANEL_FORMAT;/* 18 bit format */
 811
 812    if (radeon_crtc->crtc_id == 0) {
 813	    if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 814		    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 815		    if (radeon_encoder->rmx_type != RMX_OFF)
 816			    fp_gen_cntl |= R200_FP_SOURCE_SEL_RMX;
 817		    else
 818			    fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC1;
 819	    } else
 820		    fp_gen_cntl &= ~RADEON_FP_SEL_CRTC2;
 821    } else {
 822	    if (ASIC_IS_R300(rdev) || rdev->family == CHIP_R200) {
 823		    fp_gen_cntl &= ~R200_FP_SOURCE_SEL_MASK;
 824		    fp_gen_cntl |= R200_FP_SOURCE_SEL_CRTC2;
 825	    } else
 826		    fp_gen_cntl |= RADEON_FP_SEL_CRTC2;
 827    }
 828
 829    WREG32(RADEON_TMDS_PLL_CNTL, tmds_pll_cntl);
 830    WREG32(RADEON_TMDS_TRANSMITTER_CNTL, tmds_transmitter_cntl);
 831    WREG32(RADEON_FP_GEN_CNTL, fp_gen_cntl);
 832
 833	if (rdev->is_atom_bios)
 834		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 835	else
 836		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 837}
 838
 839static const struct drm_encoder_helper_funcs radeon_legacy_tmds_int_helper_funcs = {
 840	.dpms = radeon_legacy_tmds_int_dpms,
 841	.mode_fixup = radeon_legacy_mode_fixup,
 842	.prepare = radeon_legacy_tmds_int_prepare,
 843	.mode_set = radeon_legacy_tmds_int_mode_set,
 844	.commit = radeon_legacy_tmds_int_commit,
 845	.disable = radeon_legacy_encoder_disable,
 846};
 847
 848
 849static const struct drm_encoder_funcs radeon_legacy_tmds_int_enc_funcs = {
 850	.destroy = radeon_enc_destroy,
 851};
 852
 853static void radeon_legacy_tmds_ext_dpms(struct drm_encoder *encoder, int mode)
 854{
 855	struct drm_device *dev = encoder->dev;
 856	struct radeon_device *rdev = dev->dev_private;
 857	uint32_t fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 858	DRM_DEBUG_KMS("\n");
 859
 860	switch (mode) {
 861	case DRM_MODE_DPMS_ON:
 862		fp2_gen_cntl &= ~RADEON_FP2_BLANK_EN;
 863		fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 864		break;
 865	case DRM_MODE_DPMS_STANDBY:
 866	case DRM_MODE_DPMS_SUSPEND:
 867	case DRM_MODE_DPMS_OFF:
 868		fp2_gen_cntl |= RADEON_FP2_BLANK_EN;
 869		fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
 870		break;
 871	}
 872
 873	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 874
 875	if (rdev->is_atom_bios)
 876		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 877	else
 878		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
 879
 880}
 881
 882static void radeon_legacy_tmds_ext_prepare(struct drm_encoder *encoder)
 883{
 884	struct radeon_device *rdev = encoder->dev->dev_private;
 885
 886	if (rdev->is_atom_bios)
 887		radeon_atom_output_lock(encoder, true);
 888	else
 889		radeon_combios_output_lock(encoder, true);
 890	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_OFF);
 891}
 892
 893static void radeon_legacy_tmds_ext_commit(struct drm_encoder *encoder)
 894{
 895	struct radeon_device *rdev = encoder->dev->dev_private;
 896	radeon_legacy_tmds_ext_dpms(encoder, DRM_MODE_DPMS_ON);
 897
 898	if (rdev->is_atom_bios)
 899		radeon_atom_output_lock(encoder, false);
 900	else
 901		radeon_combios_output_lock(encoder, false);
 902}
 903
 904static void radeon_legacy_tmds_ext_mode_set(struct drm_encoder *encoder,
 905					    struct drm_display_mode *mode,
 906					    struct drm_display_mode *adjusted_mode)
 907{
 908	struct drm_device *dev = encoder->dev;
 909	struct radeon_device *rdev = dev->dev_private;
 910	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 911	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 912	uint32_t fp2_gen_cntl;
 913
 914	DRM_DEBUG_KMS("\n");
 915
 916	if (rdev->is_atom_bios) {
 917		radeon_encoder->pixel_clock = adjusted_mode->clock;
 918		atombios_dvo_setup(encoder, ATOM_ENABLE);
 919		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 920	} else {
 921		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
 922
 923		if (1) /*  FIXME rgbBits == 8 */
 924			fp2_gen_cntl |= RADEON_FP2_PANEL_FORMAT; /* 24 bit format, */
 925		else
 926			fp2_gen_cntl &= ~RADEON_FP2_PANEL_FORMAT;/* 18 bit format, */
 927
 928		fp2_gen_cntl &= ~(RADEON_FP2_ON |
 929				  RADEON_FP2_DVO_EN |
 930				  RADEON_FP2_DVO_RATE_SEL_SDR);
 931
 932		/* XXX: these are oem specific */
 933		if (ASIC_IS_R300(rdev)) {
 934			if ((dev->pdev->device == 0x4850) &&
 935			    (dev->pdev->subsystem_vendor == 0x1028) &&
 936			    (dev->pdev->subsystem_device == 0x2001)) /* Dell Inspiron 8600 */
 937				fp2_gen_cntl |= R300_FP2_DVO_CLOCK_MODE_SINGLE;
 938			else
 939				fp2_gen_cntl |= RADEON_FP2_PAD_FLOP_EN | R300_FP2_DVO_CLOCK_MODE_SINGLE;
 940
 941			/*if (mode->clock > 165000)
 942			  fp2_gen_cntl |= R300_FP2_DVO_DUAL_CHANNEL_EN;*/
 943		}
 944		if (!radeon_combios_external_tmds_setup(encoder))
 945			radeon_external_tmds_setup(encoder);
 946	}
 947
 948	if (radeon_crtc->crtc_id == 0) {
 949		if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 950			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 951			if (radeon_encoder->rmx_type != RMX_OFF)
 952				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_RMX;
 953			else
 954				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC1;
 955		} else
 956			fp2_gen_cntl &= ~RADEON_FP2_SRC_SEL_CRTC2;
 957	} else {
 958		if ((rdev->family == CHIP_R200) || ASIC_IS_R300(rdev)) {
 959			fp2_gen_cntl &= ~R200_FP2_SOURCE_SEL_MASK;
 960			fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
 961		} else
 962			fp2_gen_cntl |= RADEON_FP2_SRC_SEL_CRTC2;
 963	}
 964
 965	WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
 966
 967	if (rdev->is_atom_bios)
 968		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 969	else
 970		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
 971}
 972
 973static void radeon_ext_tmds_enc_destroy(struct drm_encoder *encoder)
 974{
 975	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 976	struct radeon_encoder_ext_tmds *tmds = radeon_encoder->enc_priv;
 977	if (tmds) {
 978		if (tmds->i2c_bus)
 979			radeon_i2c_destroy(tmds->i2c_bus);
 980	}
 981	kfree(radeon_encoder->enc_priv);
 982	drm_encoder_cleanup(encoder);
 983	kfree(radeon_encoder);
 984}
 985
 986static const struct drm_encoder_helper_funcs radeon_legacy_tmds_ext_helper_funcs = {
 987	.dpms = radeon_legacy_tmds_ext_dpms,
 988	.mode_fixup = radeon_legacy_mode_fixup,
 989	.prepare = radeon_legacy_tmds_ext_prepare,
 990	.mode_set = radeon_legacy_tmds_ext_mode_set,
 991	.commit = radeon_legacy_tmds_ext_commit,
 992	.disable = radeon_legacy_encoder_disable,
 993};
 994
 995
 996static const struct drm_encoder_funcs radeon_legacy_tmds_ext_enc_funcs = {
 997	.destroy = radeon_ext_tmds_enc_destroy,
 998};
 999
1000static void radeon_legacy_tv_dac_dpms(struct drm_encoder *encoder, int mode)
1001{
1002	struct drm_device *dev = encoder->dev;
1003	struct radeon_device *rdev = dev->dev_private;
1004	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1005	uint32_t fp2_gen_cntl = 0, crtc2_gen_cntl = 0, tv_dac_cntl = 0;
1006	uint32_t tv_master_cntl = 0;
1007	bool is_tv;
1008	DRM_DEBUG_KMS("\n");
1009
1010	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1011
1012	if (rdev->family == CHIP_R200)
1013		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1014	else {
1015		if (is_tv)
1016			tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1017		else
1018			crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1019		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1020	}
1021
1022	switch (mode) {
1023	case DRM_MODE_DPMS_ON:
1024		if (rdev->family == CHIP_R200) {
1025			fp2_gen_cntl |= (RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1026		} else {
1027			if (is_tv)
1028				tv_master_cntl |= RADEON_TV_ON;
1029			else
1030				crtc2_gen_cntl |= RADEON_CRTC2_CRT2_ON;
1031
1032			if (rdev->family == CHIP_R420 ||
1033			    rdev->family == CHIP_R423 ||
1034			    rdev->family == CHIP_RV410)
1035				tv_dac_cntl &= ~(R420_TV_DAC_RDACPD |
1036						 R420_TV_DAC_GDACPD |
1037						 R420_TV_DAC_BDACPD |
1038						 RADEON_TV_DAC_BGSLEEP);
1039			else
1040				tv_dac_cntl &= ~(RADEON_TV_DAC_RDACPD |
1041						 RADEON_TV_DAC_GDACPD |
1042						 RADEON_TV_DAC_BDACPD |
1043						 RADEON_TV_DAC_BGSLEEP);
1044		}
1045		break;
1046	case DRM_MODE_DPMS_STANDBY:
1047	case DRM_MODE_DPMS_SUSPEND:
1048	case DRM_MODE_DPMS_OFF:
1049		if (rdev->family == CHIP_R200)
1050			fp2_gen_cntl &= ~(RADEON_FP2_ON | RADEON_FP2_DVO_EN);
1051		else {
1052			if (is_tv)
1053				tv_master_cntl &= ~RADEON_TV_ON;
1054			else
1055				crtc2_gen_cntl &= ~RADEON_CRTC2_CRT2_ON;
1056
1057			if (rdev->family == CHIP_R420 ||
1058			    rdev->family == CHIP_R423 ||
1059			    rdev->family == CHIP_RV410)
1060				tv_dac_cntl |= (R420_TV_DAC_RDACPD |
1061						R420_TV_DAC_GDACPD |
1062						R420_TV_DAC_BDACPD |
1063						RADEON_TV_DAC_BGSLEEP);
1064			else
1065				tv_dac_cntl |= (RADEON_TV_DAC_RDACPD |
1066						RADEON_TV_DAC_GDACPD |
1067						RADEON_TV_DAC_BDACPD |
1068						RADEON_TV_DAC_BGSLEEP);
1069		}
1070		break;
1071	}
1072
1073	if (rdev->family == CHIP_R200) {
1074		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1075	} else {
1076		if (is_tv)
1077			WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1078		else
 
1079			WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1080		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1081	}
1082
1083	if (rdev->is_atom_bios)
1084		radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1085	else
1086		radeon_combios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1087
1088}
1089
1090static void radeon_legacy_tv_dac_prepare(struct drm_encoder *encoder)
1091{
1092	struct radeon_device *rdev = encoder->dev->dev_private;
1093
1094	if (rdev->is_atom_bios)
1095		radeon_atom_output_lock(encoder, true);
1096	else
1097		radeon_combios_output_lock(encoder, true);
1098	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_OFF);
1099}
1100
1101static void radeon_legacy_tv_dac_commit(struct drm_encoder *encoder)
1102{
1103	struct radeon_device *rdev = encoder->dev->dev_private;
1104
1105	radeon_legacy_tv_dac_dpms(encoder, DRM_MODE_DPMS_ON);
1106
1107	if (rdev->is_atom_bios)
1108		radeon_atom_output_lock(encoder, true);
1109	else
1110		radeon_combios_output_lock(encoder, true);
1111}
1112
1113static void radeon_legacy_tv_dac_mode_set(struct drm_encoder *encoder,
1114		struct drm_display_mode *mode,
1115		struct drm_display_mode *adjusted_mode)
1116{
1117	struct drm_device *dev = encoder->dev;
1118	struct radeon_device *rdev = dev->dev_private;
1119	struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1120	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1121	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1122	uint32_t tv_dac_cntl, gpiopad_a = 0, dac2_cntl, disp_output_cntl = 0;
1123	uint32_t disp_hw_debug = 0, fp2_gen_cntl = 0, disp_tv_out_cntl = 0;
1124	bool is_tv = false;
1125
1126	DRM_DEBUG_KMS("\n");
1127
1128	is_tv = radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT ? true : false;
1129
1130	if (rdev->family != CHIP_R200) {
1131		tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1132		if (rdev->family == CHIP_R420 ||
1133		    rdev->family == CHIP_R423 ||
1134		    rdev->family == CHIP_RV410) {
1135			tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1136					 RADEON_TV_DAC_BGADJ_MASK |
1137					 R420_TV_DAC_DACADJ_MASK |
1138					 R420_TV_DAC_RDACPD |
1139					 R420_TV_DAC_GDACPD |
1140					 R420_TV_DAC_BDACPD |
1141					 R420_TV_DAC_TVENABLE);
1142		} else {
1143			tv_dac_cntl &= ~(RADEON_TV_DAC_STD_MASK |
1144					 RADEON_TV_DAC_BGADJ_MASK |
1145					 RADEON_TV_DAC_DACADJ_MASK |
1146					 RADEON_TV_DAC_RDACPD |
1147					 RADEON_TV_DAC_GDACPD |
1148					 RADEON_TV_DAC_BDACPD);
1149		}
1150
1151		tv_dac_cntl |= RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD;
1152
1153		if (is_tv) {
1154			if (tv_dac->tv_std == TV_STD_NTSC ||
1155			    tv_dac->tv_std == TV_STD_NTSC_J ||
1156			    tv_dac->tv_std == TV_STD_PAL_M ||
1157			    tv_dac->tv_std == TV_STD_PAL_60)
1158				tv_dac_cntl |= tv_dac->ntsc_tvdac_adj;
1159			else
1160				tv_dac_cntl |= tv_dac->pal_tvdac_adj;
1161
1162			if (tv_dac->tv_std == TV_STD_NTSC ||
1163			    tv_dac->tv_std == TV_STD_NTSC_J)
1164				tv_dac_cntl |= RADEON_TV_DAC_STD_NTSC;
1165			else
1166				tv_dac_cntl |= RADEON_TV_DAC_STD_PAL;
1167		} else
1168			tv_dac_cntl |= (RADEON_TV_DAC_STD_PS2 |
1169					tv_dac->ps2_tvdac_adj);
1170
1171		WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1172	}
1173
1174	if (ASIC_IS_R300(rdev)) {
1175		gpiopad_a = RREG32(RADEON_GPIOPAD_A) | 1;
1176		disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1177	} else if (rdev->family != CHIP_R200)
1178		disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1179	else if (rdev->family == CHIP_R200)
1180		fp2_gen_cntl = RREG32(RADEON_FP2_GEN_CNTL);
1181
1182	if (rdev->family >= CHIP_R200)
1183		disp_tv_out_cntl = RREG32(RADEON_DISP_TV_OUT_CNTL);
1184
1185	if (is_tv) {
1186		uint32_t dac_cntl;
1187
1188		dac_cntl = RREG32(RADEON_DAC_CNTL);
1189		dac_cntl &= ~RADEON_DAC_TVO_EN;
1190		WREG32(RADEON_DAC_CNTL, dac_cntl);
1191
1192		if (ASIC_IS_R300(rdev))
1193			gpiopad_a = RREG32(RADEON_GPIOPAD_A) & ~1;
1194
1195		dac2_cntl = RREG32(RADEON_DAC_CNTL2) & ~RADEON_DAC2_DAC2_CLK_SEL;
1196		if (radeon_crtc->crtc_id == 0) {
1197			if (ASIC_IS_R300(rdev)) {
1198				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1199				disp_output_cntl |= (RADEON_DISP_TVDAC_SOURCE_CRTC |
1200						     RADEON_DISP_TV_SOURCE_CRTC);
1201			}
1202			if (rdev->family >= CHIP_R200) {
1203				disp_tv_out_cntl &= ~RADEON_DISP_TV_PATH_SRC_CRTC2;
1204			} else {
1205				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1206			}
1207		} else {
1208			if (ASIC_IS_R300(rdev)) {
1209				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1210				disp_output_cntl |= RADEON_DISP_TV_SOURCE_CRTC;
1211			}
1212			if (rdev->family >= CHIP_R200) {
1213				disp_tv_out_cntl |= RADEON_DISP_TV_PATH_SRC_CRTC2;
1214			} else {
1215				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1216			}
1217		}
1218		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1219	} else {
1220
1221		dac2_cntl = RREG32(RADEON_DAC_CNTL2) | RADEON_DAC2_DAC2_CLK_SEL;
1222
1223		if (radeon_crtc->crtc_id == 0) {
1224			if (ASIC_IS_R300(rdev)) {
1225				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1226				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC;
1227			} else if (rdev->family == CHIP_R200) {
1228				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1229						  RADEON_FP2_DVO_RATE_SEL_SDR);
1230			} else
1231				disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1232		} else {
1233			if (ASIC_IS_R300(rdev)) {
1234				disp_output_cntl &= ~RADEON_DISP_TVDAC_SOURCE_MASK;
1235				disp_output_cntl |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1236			} else if (rdev->family == CHIP_R200) {
1237				fp2_gen_cntl &= ~(R200_FP2_SOURCE_SEL_MASK |
1238						  RADEON_FP2_DVO_RATE_SEL_SDR);
1239				fp2_gen_cntl |= R200_FP2_SOURCE_SEL_CRTC2;
1240			} else
1241				disp_hw_debug &= ~RADEON_CRT2_DISP1_SEL;
1242		}
1243		WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1244	}
1245
1246	if (ASIC_IS_R300(rdev)) {
1247		WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1248		WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1249	} else if (rdev->family != CHIP_R200)
1250		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1251	else if (rdev->family == CHIP_R200)
1252		WREG32(RADEON_FP2_GEN_CNTL, fp2_gen_cntl);
1253
1254	if (rdev->family >= CHIP_R200)
1255		WREG32(RADEON_DISP_TV_OUT_CNTL, disp_tv_out_cntl);
1256
1257	if (is_tv)
1258		radeon_legacy_tv_mode_set(encoder, mode, adjusted_mode);
1259
1260	if (rdev->is_atom_bios)
1261		radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1262	else
1263		radeon_combios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1264
1265}
1266
1267static bool r300_legacy_tv_detect(struct drm_encoder *encoder,
1268				  struct drm_connector *connector)
1269{
1270	struct drm_device *dev = encoder->dev;
1271	struct radeon_device *rdev = dev->dev_private;
1272	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1273	uint32_t disp_output_cntl, gpiopad_a, tmp;
1274	bool found = false;
1275
1276	/* save regs needed */
1277	gpiopad_a = RREG32(RADEON_GPIOPAD_A);
1278	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1279	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1280	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1281	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1282	disp_output_cntl = RREG32(RADEON_DISP_OUTPUT_CNTL);
1283
1284	WREG32_P(RADEON_GPIOPAD_A, 0, ~1);
1285
1286	WREG32(RADEON_DAC_CNTL2, RADEON_DAC2_DAC2_CLK_SEL);
1287
1288	WREG32(RADEON_CRTC2_GEN_CNTL,
1289	       RADEON_CRTC2_CRT2_ON | RADEON_CRTC2_VSYNC_TRISTAT);
1290
1291	tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1292	tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1293	WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1294
1295	WREG32(RADEON_DAC_EXT_CNTL,
1296	       RADEON_DAC2_FORCE_BLANK_OFF_EN |
1297	       RADEON_DAC2_FORCE_DATA_EN |
1298	       RADEON_DAC_FORCE_DATA_SEL_RGB |
1299	       (0xec << RADEON_DAC_FORCE_DATA_SHIFT));
1300
1301	WREG32(RADEON_TV_DAC_CNTL,
1302	       RADEON_TV_DAC_STD_NTSC |
1303	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1304	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1305
1306	RREG32(RADEON_TV_DAC_CNTL);
1307	mdelay(4);
1308
1309	WREG32(RADEON_TV_DAC_CNTL,
1310	       RADEON_TV_DAC_NBLANK |
1311	       RADEON_TV_DAC_NHOLD |
1312	       RADEON_TV_MONITOR_DETECT_EN |
1313	       RADEON_TV_DAC_STD_NTSC |
1314	       (8 << RADEON_TV_DAC_BGADJ_SHIFT) |
1315	       (6 << RADEON_TV_DAC_DACADJ_SHIFT));
1316
1317	RREG32(RADEON_TV_DAC_CNTL);
1318	mdelay(6);
1319
1320	tmp = RREG32(RADEON_TV_DAC_CNTL);
1321	if ((tmp & RADEON_TV_DAC_GDACDET) != 0) {
1322		found = true;
1323		DRM_DEBUG_KMS("S-video TV connection detected\n");
1324	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1325		found = true;
1326		DRM_DEBUG_KMS("Composite TV connection detected\n");
1327	}
1328
1329	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1330	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1331	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1332	WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1333	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1334	WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1335	return found;
1336}
1337
1338static bool radeon_legacy_tv_detect(struct drm_encoder *encoder,
1339				    struct drm_connector *connector)
1340{
1341	struct drm_device *dev = encoder->dev;
1342	struct radeon_device *rdev = dev->dev_private;
1343	uint32_t tv_dac_cntl, dac_cntl2;
1344	uint32_t config_cntl, tv_pre_dac_mux_cntl, tv_master_cntl, tmp;
1345	bool found = false;
1346
1347	if (ASIC_IS_R300(rdev))
1348		return r300_legacy_tv_detect(encoder, connector);
1349
1350	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1351	tv_master_cntl = RREG32(RADEON_TV_MASTER_CNTL);
1352	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1353	config_cntl = RREG32(RADEON_CONFIG_CNTL);
1354	tv_pre_dac_mux_cntl = RREG32(RADEON_TV_PRE_DAC_MUX_CNTL);
1355
1356	tmp = dac_cntl2 & ~RADEON_DAC2_DAC2_CLK_SEL;
1357	WREG32(RADEON_DAC_CNTL2, tmp);
1358
1359	tmp = tv_master_cntl | RADEON_TV_ON;
1360	tmp &= ~(RADEON_TV_ASYNC_RST |
1361		 RADEON_RESTART_PHASE_FIX |
1362		 RADEON_CRT_FIFO_CE_EN |
1363		 RADEON_TV_FIFO_CE_EN |
1364		 RADEON_RE_SYNC_NOW_SEL_MASK);
1365	tmp |= RADEON_TV_FIFO_ASYNC_RST | RADEON_CRT_ASYNC_RST;
1366	WREG32(RADEON_TV_MASTER_CNTL, tmp);
1367
1368	tmp = RADEON_TV_DAC_NBLANK | RADEON_TV_DAC_NHOLD |
1369		RADEON_TV_MONITOR_DETECT_EN | RADEON_TV_DAC_STD_NTSC |
1370		(8 << RADEON_TV_DAC_BGADJ_SHIFT);
1371
1372	if (config_cntl & RADEON_CFG_ATI_REV_ID_MASK)
1373		tmp |= (4 << RADEON_TV_DAC_DACADJ_SHIFT);
1374	else
1375		tmp |= (8 << RADEON_TV_DAC_DACADJ_SHIFT);
1376	WREG32(RADEON_TV_DAC_CNTL, tmp);
1377
1378	tmp = RADEON_C_GRN_EN | RADEON_CMP_BLU_EN |
1379		RADEON_RED_MX_FORCE_DAC_DATA |
1380		RADEON_GRN_MX_FORCE_DAC_DATA |
1381		RADEON_BLU_MX_FORCE_DAC_DATA |
1382		(0x109 << RADEON_TV_FORCE_DAC_DATA_SHIFT);
1383	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tmp);
1384
1385	mdelay(3);
1386	tmp = RREG32(RADEON_TV_DAC_CNTL);
1387	if (tmp & RADEON_TV_DAC_GDACDET) {
1388		found = true;
1389		DRM_DEBUG_KMS("S-video TV connection detected\n");
1390	} else if ((tmp & RADEON_TV_DAC_BDACDET) != 0) {
1391		found = true;
1392		DRM_DEBUG_KMS("Composite TV connection detected\n");
1393	}
1394
1395	WREG32(RADEON_TV_PRE_DAC_MUX_CNTL, tv_pre_dac_mux_cntl);
1396	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1397	WREG32(RADEON_TV_MASTER_CNTL, tv_master_cntl);
1398	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1399	return found;
1400}
1401
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1402static enum drm_connector_status radeon_legacy_tv_dac_detect(struct drm_encoder *encoder,
1403							     struct drm_connector *connector)
1404{
1405	struct drm_device *dev = encoder->dev;
1406	struct radeon_device *rdev = dev->dev_private;
1407	uint32_t crtc2_gen_cntl, tv_dac_cntl, dac_cntl2, dac_ext_cntl;
1408	uint32_t disp_hw_debug, disp_output_cntl, gpiopad_a, pixclks_cntl, tmp;
 
1409	enum drm_connector_status found = connector_status_disconnected;
1410	struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1411	struct radeon_encoder_tv_dac *tv_dac = radeon_encoder->enc_priv;
1412	bool color = true;
1413	struct drm_crtc *crtc;
1414
1415	/* find out if crtc2 is in use or if this encoder is using it */
1416	list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1417		struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1418		if ((radeon_crtc->crtc_id == 1) && crtc->enabled) {
1419			if (encoder->crtc != crtc) {
1420				return connector_status_disconnected;
1421			}
1422		}
1423	}
1424
1425	if (connector->connector_type == DRM_MODE_CONNECTOR_SVIDEO ||
1426	    connector->connector_type == DRM_MODE_CONNECTOR_Composite ||
1427	    connector->connector_type == DRM_MODE_CONNECTOR_9PinDIN) {
1428		bool tv_detect;
1429
1430		if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT))
1431			return connector_status_disconnected;
1432
1433		tv_detect = radeon_legacy_tv_detect(encoder, connector);
1434		if (tv_detect && tv_dac)
1435			found = connector_status_connected;
1436		return found;
1437	}
1438
1439	/* don't probe if the encoder is being used for something else not CRT related */
1440	if (radeon_encoder->active_device && !(radeon_encoder->active_device & ATOM_DEVICE_CRT_SUPPORT)) {
1441		DRM_INFO("not detecting due to %08x\n", radeon_encoder->active_device);
1442		return connector_status_disconnected;
1443	}
1444
 
 
 
 
 
 
 
1445	/* save the regs we need */
1446	pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
1447	gpiopad_a = ASIC_IS_R300(rdev) ? RREG32(RADEON_GPIOPAD_A) : 0;
1448	disp_output_cntl = ASIC_IS_R300(rdev) ? RREG32(RADEON_DISP_OUTPUT_CNTL) : 0;
1449	disp_hw_debug = ASIC_IS_R300(rdev) ? 0 : RREG32(RADEON_DISP_HW_DEBUG);
1450	crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
 
 
 
 
 
 
 
 
1451	tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1452	dac_ext_cntl = RREG32(RADEON_DAC_EXT_CNTL);
1453	dac_cntl2 = RREG32(RADEON_DAC_CNTL2);
1454
1455	tmp = pixclks_cntl & ~(RADEON_PIX2CLK_ALWAYS_ONb
1456			       | RADEON_PIX2CLK_DAC_ALWAYS_ONb);
1457	WREG32_PLL(RADEON_PIXCLKS_CNTL, tmp);
1458
1459	if (ASIC_IS_R300(rdev))
1460		WREG32_P(RADEON_GPIOPAD_A, 1, ~1);
1461
1462	tmp = crtc2_gen_cntl & ~RADEON_CRTC2_PIX_WIDTH_MASK;
1463	tmp |= RADEON_CRTC2_CRT2_ON |
1464		(2 << RADEON_CRTC2_PIX_WIDTH_SHIFT);
1465
1466	WREG32(RADEON_CRTC2_GEN_CNTL, tmp);
1467
1468	if (ASIC_IS_R300(rdev)) {
1469		tmp = disp_output_cntl & ~RADEON_DISP_TVDAC_SOURCE_MASK;
1470		tmp |= RADEON_DISP_TVDAC_SOURCE_CRTC2;
1471		WREG32(RADEON_DISP_OUTPUT_CNTL, tmp);
1472	} else {
1473		tmp = disp_hw_debug & ~RADEON_CRT2_DISP1_SEL;
1474		WREG32(RADEON_DISP_HW_DEBUG, tmp);
 
 
 
 
 
 
 
 
 
 
 
 
1475	}
1476
1477	tmp = RADEON_TV_DAC_NBLANK |
1478		RADEON_TV_DAC_NHOLD |
1479		RADEON_TV_MONITOR_DETECT_EN |
1480		RADEON_TV_DAC_STD_PS2;
1481
1482	WREG32(RADEON_TV_DAC_CNTL, tmp);
1483
1484	tmp = RADEON_DAC2_FORCE_BLANK_OFF_EN |
1485		RADEON_DAC2_FORCE_DATA_EN;
1486
1487	if (color)
1488		tmp |= RADEON_DAC_FORCE_DATA_SEL_RGB;
1489	else
1490		tmp |= RADEON_DAC_FORCE_DATA_SEL_G;
1491
1492	if (ASIC_IS_R300(rdev))
1493		tmp |= (0x1b6 << RADEON_DAC_FORCE_DATA_SHIFT);
1494	else
1495		tmp |= (0x180 << RADEON_DAC_FORCE_DATA_SHIFT);
1496
1497	WREG32(RADEON_DAC_EXT_CNTL, tmp);
1498
1499	tmp = dac_cntl2 | RADEON_DAC2_DAC2_CLK_SEL | RADEON_DAC2_CMP_EN;
1500	WREG32(RADEON_DAC_CNTL2, tmp);
1501
1502	udelay(10000);
1503
1504	if (ASIC_IS_R300(rdev)) {
1505		if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUT_B)
1506			found = connector_status_connected;
1507	} else {
1508		if (RREG32(RADEON_DAC_CNTL2) & RADEON_DAC2_CMP_OUTPUT)
1509			found = connector_status_connected;
1510	}
1511
1512	/* restore regs we used */
1513	WREG32(RADEON_DAC_CNTL2, dac_cntl2);
1514	WREG32(RADEON_DAC_EXT_CNTL, dac_ext_cntl);
1515	WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1516	WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
1517
1518	if (ASIC_IS_R300(rdev)) {
1519		WREG32(RADEON_DISP_OUTPUT_CNTL, disp_output_cntl);
1520		WREG32_P(RADEON_GPIOPAD_A, gpiopad_a, ~1);
1521	} else {
1522		WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
 
 
 
 
 
 
1523	}
 
1524	WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
1525
1526	return found;
1527
1528}
1529
1530static const struct drm_encoder_helper_funcs radeon_legacy_tv_dac_helper_funcs = {
1531	.dpms = radeon_legacy_tv_dac_dpms,
1532	.mode_fixup = radeon_legacy_mode_fixup,
1533	.prepare = radeon_legacy_tv_dac_prepare,
1534	.mode_set = radeon_legacy_tv_dac_mode_set,
1535	.commit = radeon_legacy_tv_dac_commit,
1536	.detect = radeon_legacy_tv_dac_detect,
1537	.disable = radeon_legacy_encoder_disable,
1538};
1539
1540
1541static const struct drm_encoder_funcs radeon_legacy_tv_dac_enc_funcs = {
1542	.destroy = radeon_enc_destroy,
1543};
1544
1545
1546static struct radeon_encoder_int_tmds *radeon_legacy_get_tmds_info(struct radeon_encoder *encoder)
1547{
1548	struct drm_device *dev = encoder->base.dev;
1549	struct radeon_device *rdev = dev->dev_private;
1550	struct radeon_encoder_int_tmds *tmds = NULL;
1551	bool ret;
1552
1553	tmds = kzalloc(sizeof(struct radeon_encoder_int_tmds), GFP_KERNEL);
1554
1555	if (!tmds)
1556		return NULL;
1557
1558	if (rdev->is_atom_bios)
1559		ret = radeon_atombios_get_tmds_info(encoder, tmds);
1560	else
1561		ret = radeon_legacy_get_tmds_info_from_combios(encoder, tmds);
1562
1563	if (ret == false)
1564		radeon_legacy_get_tmds_info_from_table(encoder, tmds);
1565
1566	return tmds;
1567}
1568
1569static struct radeon_encoder_ext_tmds *radeon_legacy_get_ext_tmds_info(struct radeon_encoder *encoder)
1570{
1571	struct drm_device *dev = encoder->base.dev;
1572	struct radeon_device *rdev = dev->dev_private;
1573	struct radeon_encoder_ext_tmds *tmds = NULL;
1574	bool ret;
1575
1576	if (rdev->is_atom_bios)
1577		return NULL;
1578
1579	tmds = kzalloc(sizeof(struct radeon_encoder_ext_tmds), GFP_KERNEL);
1580
1581	if (!tmds)
1582		return NULL;
1583
1584	ret = radeon_legacy_get_ext_tmds_info_from_combios(encoder, tmds);
1585
1586	if (ret == false)
1587		radeon_legacy_get_ext_tmds_info_from_table(encoder, tmds);
1588
1589	return tmds;
1590}
1591
1592void
1593radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1594{
1595	struct radeon_device *rdev = dev->dev_private;
1596	struct drm_encoder *encoder;
1597	struct radeon_encoder *radeon_encoder;
1598
1599	/* see if we already added it */
1600	list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1601		radeon_encoder = to_radeon_encoder(encoder);
1602		if (radeon_encoder->encoder_enum == encoder_enum) {
1603			radeon_encoder->devices |= supported_device;
1604			return;
1605		}
1606
1607	}
1608
1609	/* add a new one */
1610	radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1611	if (!radeon_encoder)
1612		return;
1613
1614	encoder = &radeon_encoder->base;
1615	if (rdev->flags & RADEON_SINGLE_CRTC)
1616		encoder->possible_crtcs = 0x1;
1617	else
1618		encoder->possible_crtcs = 0x3;
1619
1620	radeon_encoder->enc_priv = NULL;
1621
1622	radeon_encoder->encoder_enum = encoder_enum;
1623	radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1624	radeon_encoder->devices = supported_device;
1625	radeon_encoder->rmx_type = RMX_OFF;
1626
1627	switch (radeon_encoder->encoder_id) {
1628	case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1629		encoder->possible_crtcs = 0x1;
1630		drm_encoder_init(dev, encoder, &radeon_legacy_lvds_enc_funcs, DRM_MODE_ENCODER_LVDS);
1631		drm_encoder_helper_add(encoder, &radeon_legacy_lvds_helper_funcs);
1632		if (rdev->is_atom_bios)
1633			radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1634		else
1635			radeon_encoder->enc_priv = radeon_combios_get_lvds_info(radeon_encoder);
1636		radeon_encoder->rmx_type = RMX_FULL;
1637		break;
1638	case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1639		drm_encoder_init(dev, encoder, &radeon_legacy_tmds_int_enc_funcs, DRM_MODE_ENCODER_TMDS);
1640		drm_encoder_helper_add(encoder, &radeon_legacy_tmds_int_helper_funcs);
1641		radeon_encoder->enc_priv = radeon_legacy_get_tmds_info(radeon_encoder);
1642		break;
1643	case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1644		drm_encoder_init(dev, encoder, &radeon_legacy_primary_dac_enc_funcs, DRM_MODE_ENCODER_DAC);
1645		drm_encoder_helper_add(encoder, &radeon_legacy_primary_dac_helper_funcs);
1646		if (rdev->is_atom_bios)
1647			radeon_encoder->enc_priv = radeon_atombios_get_primary_dac_info(radeon_encoder);
1648		else
1649			radeon_encoder->enc_priv = radeon_combios_get_primary_dac_info(radeon_encoder);
1650		break;
1651	case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1652		drm_encoder_init(dev, encoder, &radeon_legacy_tv_dac_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1653		drm_encoder_helper_add(encoder, &radeon_legacy_tv_dac_helper_funcs);
1654		if (rdev->is_atom_bios)
1655			radeon_encoder->enc_priv = radeon_atombios_get_tv_dac_info(radeon_encoder);
1656		else
1657			radeon_encoder->enc_priv = radeon_combios_get_tv_dac_info(radeon_encoder);
1658		break;
1659	case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1660		drm_encoder_init(dev, encoder, &radeon_legacy_tmds_ext_enc_funcs, DRM_MODE_ENCODER_TMDS);
1661		drm_encoder_helper_add(encoder, &radeon_legacy_tmds_ext_helper_funcs);
1662		if (!rdev->is_atom_bios)
1663			radeon_encoder->enc_priv = radeon_legacy_get_ext_tmds_info(radeon_encoder);
1664		break;
1665	}
1666}