1/*
  2 * Copyright 2012 Red Hat Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: Ben Skeggs <bskeggs@redhat.com>
 23 */
 24
 25#include <core/object.h>
 26#include <core/class.h>
 27
 28#include "nouveau_drm.h"
 29#include "nouveau_dma.h"
 30#include "nv10_fence.h"
 31
 32#include "nv50_display.h"
 33
 34static int
 35nv50_fence_context_new(struct nouveau_channel *chan)
 36{
 37	struct drm_device *dev = chan->drm->dev;
 38	struct nv10_fence_priv *priv = chan->drm->fence;
 39	struct nv10_fence_chan *fctx;
 40	struct ttm_mem_reg *mem = &priv->bo->bo.mem;
 41	struct nouveau_object *object;
 42	u32 start = mem->start * PAGE_SIZE;
 43	u32 limit = start + mem->size - 1;
 44	int ret, i;
 45
 46	fctx = chan->fence = kzalloc(sizeof(*fctx), GFP_KERNEL);
 47	if (!fctx)
 48		return -ENOMEM;
 49
 50	nouveau_fence_context_new(&fctx->base);
 51	fctx->base.emit = nv10_fence_emit;
 52	fctx->base.read = nv10_fence_read;
 53	fctx->base.sync = nv17_fence_sync;
 54
 55	ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
 56				 NvSema, 0x003d,
 57				 &(struct nv_dma_class) {
 58					.flags = NV_DMA_TARGET_VRAM |
 59						 NV_DMA_ACCESS_RDWR,
 60					.start = start,
 61					.limit = limit,
 62				 }, sizeof(struct nv_dma_class),
 63				 &object);
 64
 65	/* dma objects for display sync channel semaphore blocks */
 66	for (i = 0; !ret && i < dev->mode_config.num_crtc; i++) {
 67		struct nouveau_bo *bo = nv50_display_crtc_sema(dev, i);
 68		u32 start = bo->bo.mem.start * PAGE_SIZE;
 69		u32 limit = start + bo->bo.mem.size - 1;
 70
 71		ret = nouveau_object_new(nv_object(chan->cli), chan->handle,
 72					 NvEvoSema0 + i, 0x003d,
 73					 &(struct nv_dma_class) {
 74						.flags = NV_DMA_TARGET_VRAM |
 75							 NV_DMA_ACCESS_RDWR,
 76						.start = start,
 77						.limit = limit,
 78					 }, sizeof(struct nv_dma_class),
 79					 &object);
 80	}
 81
 82	if (ret)
 83		nv10_fence_context_del(chan);
 84	return ret;
 85}
 86
 87int
 88nv50_fence_create(struct nouveau_drm *drm)
 89{
 90	struct nv10_fence_priv *priv;
 91	int ret = 0;
 92
 93	priv = drm->fence = kzalloc(sizeof(*priv), GFP_KERNEL);
 94	if (!priv)
 95		return -ENOMEM;
 96
 97	priv->base.dtor = nv10_fence_destroy;
 98	priv->base.resume = nv17_fence_resume;
 99	priv->base.context_new = nv50_fence_context_new;
100	priv->base.context_del = nv10_fence_context_del;
101	spin_lock_init(&priv->lock);
102
103	ret = nouveau_bo_new(drm->dev, 4096, 0x1000, TTM_PL_FLAG_VRAM,
104			     0, 0x0000, NULL, &priv->bo);
105	if (!ret) {
106		ret = nouveau_bo_pin(priv->bo, TTM_PL_FLAG_VRAM);
107		if (!ret) {
108			ret = nouveau_bo_map(priv->bo);
109			if (ret)
110				nouveau_bo_unpin(priv->bo);
111		}
112		if (ret)
113			nouveau_bo_ref(NULL, &priv->bo);
114	}
115
116	if (ret) {
117		nv10_fence_destroy(drm);
118		return ret;
119	}
120
121	nouveau_bo_wr32(priv->bo, 0x000, 0x00000000);
122	return ret;
123}