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1#ifndef DSI_XML
2#define DSI_XML
3
4/* Autogenerated file, DO NOT EDIT manually!
5
6This file was generated by the rules-ng-ng headergen tool in this git repository:
7http://github.com/freedreno/envytools/
8git clone https://github.com/freedreno/envytools.git
9
10The rules-ng-ng source files this header was generated from are:
11- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 647 bytes, from 2013-11-30 14:45:35)
12- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
13- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 17996 bytes, from 2013-12-01 19:10:31)
14- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 1615 bytes, from 2013-11-30 15:00:52)
15- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 22517 bytes, from 2013-12-03 20:59:13)
16- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 11712 bytes, from 2013-08-17 17:13:43)
17- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
18- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1544 bytes, from 2013-08-16 19:17:05)
19- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
20- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 20932 bytes, from 2013-12-01 15:13:04)
21
22Copyright (C) 2013 by the following authors:
23- Rob Clark <robdclark@gmail.com> (robclark)
24
25Permission is hereby granted, free of charge, to any person obtaining
26a copy of this software and associated documentation files (the
27"Software"), to deal in the Software without restriction, including
28without limitation the rights to use, copy, modify, merge, publish,
29distribute, sublicense, and/or sell copies of the Software, and to
30permit persons to whom the Software is furnished to do so, subject to
31the following conditions:
32
33The above copyright notice and this permission notice (including the
34next paragraph) shall be included in all copies or substantial
35portions of the Software.
36
37THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
38EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
39MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
40IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
41LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
42OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
43WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
44*/
45
46
47enum dsi_traffic_mode {
48 NON_BURST_SYNCH_PULSE = 0,
49 NON_BURST_SYNCH_EVENT = 1,
50 BURST_MODE = 2,
51};
52
53enum dsi_dst_format {
54 DST_FORMAT_RGB565 = 0,
55 DST_FORMAT_RGB666 = 1,
56 DST_FORMAT_RGB666_LOOSE = 2,
57 DST_FORMAT_RGB888 = 3,
58};
59
60enum dsi_rgb_swap {
61 SWAP_RGB = 0,
62 SWAP_RBG = 1,
63 SWAP_BGR = 2,
64 SWAP_BRG = 3,
65 SWAP_GRB = 4,
66 SWAP_GBR = 5,
67};
68
69enum dsi_cmd_trigger {
70 TRIGGER_NONE = 0,
71 TRIGGER_TE = 2,
72 TRIGGER_SW = 4,
73 TRIGGER_SW_SEOF = 5,
74 TRIGGER_SW_TE = 6,
75};
76
77#define DSI_IRQ_CMD_DMA_DONE 0x00000001
78#define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
79#define DSI_IRQ_CMD_MDP_DONE 0x00000100
80#define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
81#define DSI_IRQ_VIDEO_DONE 0x00010000
82#define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
83#define DSI_IRQ_ERROR 0x01000000
84#define DSI_IRQ_MASK_ERROR 0x02000000
85#define REG_DSI_CTRL 0x00000000
86#define DSI_CTRL_ENABLE 0x00000001
87#define DSI_CTRL_VID_MODE_EN 0x00000002
88#define DSI_CTRL_CMD_MODE_EN 0x00000004
89#define DSI_CTRL_LANE0 0x00000010
90#define DSI_CTRL_LANE1 0x00000020
91#define DSI_CTRL_LANE2 0x00000040
92#define DSI_CTRL_LANE3 0x00000080
93#define DSI_CTRL_CLK_EN 0x00000100
94#define DSI_CTRL_ECC_CHECK 0x00100000
95#define DSI_CTRL_CRC_CHECK 0x01000000
96
97#define REG_DSI_STATUS0 0x00000004
98#define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
99#define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
100#define DSI_STATUS0_DSI_BUSY 0x00000010
101
102#define REG_DSI_FIFO_STATUS 0x00000008
103
104#define REG_DSI_VID_CFG0 0x0000000c
105#define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
106#define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
107static inline uint32_t DSI_VID_CFG0_VIRT_CHANNEL(uint32_t val)
108{
109 return ((val) << DSI_VID_CFG0_VIRT_CHANNEL__SHIFT) & DSI_VID_CFG0_VIRT_CHANNEL__MASK;
110}
111#define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
112#define DSI_VID_CFG0_DST_FORMAT__SHIFT 4
113static inline uint32_t DSI_VID_CFG0_DST_FORMAT(enum dsi_dst_format val)
114{
115 return ((val) << DSI_VID_CFG0_DST_FORMAT__SHIFT) & DSI_VID_CFG0_DST_FORMAT__MASK;
116}
117#define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
118#define DSI_VID_CFG0_TRAFFIC_MODE__SHIFT 8
119static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val)
120{
121 return ((val) << DSI_VID_CFG0_TRAFFIC_MODE__SHIFT) & DSI_VID_CFG0_TRAFFIC_MODE__MASK;
122}
123#define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
124#define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
125#define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
126#define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
127#define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
128#define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
129
130#define REG_DSI_VID_CFG1 0x0000001c
131#define DSI_VID_CFG1_R_SEL 0x00000010
132#define DSI_VID_CFG1_G_SEL 0x00000100
133#define DSI_VID_CFG1_B_SEL 0x00001000
134#define DSI_VID_CFG1_RGB_SWAP__MASK 0x00070000
135#define DSI_VID_CFG1_RGB_SWAP__SHIFT 16
136static inline uint32_t DSI_VID_CFG1_RGB_SWAP(enum dsi_rgb_swap val)
137{
138 return ((val) << DSI_VID_CFG1_RGB_SWAP__SHIFT) & DSI_VID_CFG1_RGB_SWAP__MASK;
139}
140#define DSI_VID_CFG1_INTERLEAVE_MAX__MASK 0x00f00000
141#define DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT 20
142static inline uint32_t DSI_VID_CFG1_INTERLEAVE_MAX(uint32_t val)
143{
144 return ((val) << DSI_VID_CFG1_INTERLEAVE_MAX__SHIFT) & DSI_VID_CFG1_INTERLEAVE_MAX__MASK;
145}
146
147#define REG_DSI_ACTIVE_H 0x00000020
148#define DSI_ACTIVE_H_START__MASK 0x00000fff
149#define DSI_ACTIVE_H_START__SHIFT 0
150static inline uint32_t DSI_ACTIVE_H_START(uint32_t val)
151{
152 return ((val) << DSI_ACTIVE_H_START__SHIFT) & DSI_ACTIVE_H_START__MASK;
153}
154#define DSI_ACTIVE_H_END__MASK 0x0fff0000
155#define DSI_ACTIVE_H_END__SHIFT 16
156static inline uint32_t DSI_ACTIVE_H_END(uint32_t val)
157{
158 return ((val) << DSI_ACTIVE_H_END__SHIFT) & DSI_ACTIVE_H_END__MASK;
159}
160
161#define REG_DSI_ACTIVE_V 0x00000024
162#define DSI_ACTIVE_V_START__MASK 0x00000fff
163#define DSI_ACTIVE_V_START__SHIFT 0
164static inline uint32_t DSI_ACTIVE_V_START(uint32_t val)
165{
166 return ((val) << DSI_ACTIVE_V_START__SHIFT) & DSI_ACTIVE_V_START__MASK;
167}
168#define DSI_ACTIVE_V_END__MASK 0x0fff0000
169#define DSI_ACTIVE_V_END__SHIFT 16
170static inline uint32_t DSI_ACTIVE_V_END(uint32_t val)
171{
172 return ((val) << DSI_ACTIVE_V_END__SHIFT) & DSI_ACTIVE_V_END__MASK;
173}
174
175#define REG_DSI_TOTAL 0x00000028
176#define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
177#define DSI_TOTAL_H_TOTAL__SHIFT 0
178static inline uint32_t DSI_TOTAL_H_TOTAL(uint32_t val)
179{
180 return ((val) << DSI_TOTAL_H_TOTAL__SHIFT) & DSI_TOTAL_H_TOTAL__MASK;
181}
182#define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
183#define DSI_TOTAL_V_TOTAL__SHIFT 16
184static inline uint32_t DSI_TOTAL_V_TOTAL(uint32_t val)
185{
186 return ((val) << DSI_TOTAL_V_TOTAL__SHIFT) & DSI_TOTAL_V_TOTAL__MASK;
187}
188
189#define REG_DSI_ACTIVE_HSYNC 0x0000002c
190#define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
191#define DSI_ACTIVE_HSYNC_START__SHIFT 0
192static inline uint32_t DSI_ACTIVE_HSYNC_START(uint32_t val)
193{
194 return ((val) << DSI_ACTIVE_HSYNC_START__SHIFT) & DSI_ACTIVE_HSYNC_START__MASK;
195}
196#define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
197#define DSI_ACTIVE_HSYNC_END__SHIFT 16
198static inline uint32_t DSI_ACTIVE_HSYNC_END(uint32_t val)
199{
200 return ((val) << DSI_ACTIVE_HSYNC_END__SHIFT) & DSI_ACTIVE_HSYNC_END__MASK;
201}
202
203#define REG_DSI_ACTIVE_VSYNC 0x00000034
204#define DSI_ACTIVE_VSYNC_START__MASK 0x00000fff
205#define DSI_ACTIVE_VSYNC_START__SHIFT 0
206static inline uint32_t DSI_ACTIVE_VSYNC_START(uint32_t val)
207{
208 return ((val) << DSI_ACTIVE_VSYNC_START__SHIFT) & DSI_ACTIVE_VSYNC_START__MASK;
209}
210#define DSI_ACTIVE_VSYNC_END__MASK 0x0fff0000
211#define DSI_ACTIVE_VSYNC_END__SHIFT 16
212static inline uint32_t DSI_ACTIVE_VSYNC_END(uint32_t val)
213{
214 return ((val) << DSI_ACTIVE_VSYNC_END__SHIFT) & DSI_ACTIVE_VSYNC_END__MASK;
215}
216
217#define REG_DSI_CMD_DMA_CTRL 0x00000038
218#define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
219#define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
220
221#define REG_DSI_CMD_CFG0 0x0000003c
222
223#define REG_DSI_CMD_CFG1 0x00000040
224
225#define REG_DSI_DMA_BASE 0x00000044
226
227#define REG_DSI_DMA_LEN 0x00000048
228
229#define REG_DSI_ACK_ERR_STATUS 0x00000064
230
231static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; }
232
233static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; }
234
235#define REG_DSI_TRIG_CTRL 0x00000080
236#define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x0000000f
237#define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
238static inline uint32_t DSI_TRIG_CTRL_DMA_TRIGGER(enum dsi_cmd_trigger val)
239{
240 return ((val) << DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT) & DSI_TRIG_CTRL_DMA_TRIGGER__MASK;
241}
242#define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x000000f0
243#define DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT 4
244static inline uint32_t DSI_TRIG_CTRL_MDP_TRIGGER(enum dsi_cmd_trigger val)
245{
246 return ((val) << DSI_TRIG_CTRL_MDP_TRIGGER__SHIFT) & DSI_TRIG_CTRL_MDP_TRIGGER__MASK;
247}
248#define DSI_TRIG_CTRL_STREAM 0x00000100
249#define DSI_TRIG_CTRL_TE 0x80000000
250
251#define REG_DSI_TRIG_DMA 0x0000008c
252
253#define REG_DSI_DLN0_PHY_ERR 0x000000b0
254
255#define REG_DSI_TIMEOUT_STATUS 0x000000bc
256
257#define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
258#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
259#define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
260static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE(uint32_t val)
261{
262 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK;
263}
264#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
265#define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT 8
266static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
267{
268 return ((val) << DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__SHIFT) & DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK;
269}
270
271#define REG_DSI_EOT_PACKET_CTRL 0x000000c8
272#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
273#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
274
275#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
276
277#define REG_DSI_ERR_INT_MASK0 0x00000108
278
279#define REG_DSI_INTR_CTRL 0x0000010c
280
281#define REG_DSI_RESET 0x00000114
282
283#define REG_DSI_CLK_CTRL 0x00000118
284
285#define REG_DSI_PHY_RESET 0x00000128
286
287#define REG_DSI_PHY_PLL_CTRL_0 0x00000200
288#define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
289
290#define REG_DSI_PHY_PLL_CTRL_1 0x00000204
291
292#define REG_DSI_PHY_PLL_CTRL_2 0x00000208
293
294#define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
295
296#define REG_DSI_PHY_PLL_CTRL_4 0x00000210
297
298#define REG_DSI_PHY_PLL_CTRL_5 0x00000214
299
300#define REG_DSI_PHY_PLL_CTRL_6 0x00000218
301
302#define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
303
304#define REG_DSI_PHY_PLL_CTRL_8 0x00000220
305
306#define REG_DSI_PHY_PLL_CTRL_9 0x00000224
307
308#define REG_DSI_PHY_PLL_CTRL_10 0x00000228
309
310#define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
311
312#define REG_DSI_PHY_PLL_CTRL_12 0x00000230
313
314#define REG_DSI_PHY_PLL_CTRL_13 0x00000234
315
316#define REG_DSI_PHY_PLL_CTRL_14 0x00000238
317
318#define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
319
320#define REG_DSI_PHY_PLL_CTRL_16 0x00000240
321
322#define REG_DSI_PHY_PLL_CTRL_17 0x00000244
323
324#define REG_DSI_PHY_PLL_CTRL_18 0x00000248
325
326#define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
327
328#define REG_DSI_PHY_PLL_CTRL_20 0x00000250
329
330#define REG_DSI_PHY_PLL_STATUS 0x00000280
331#define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
332
333#define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
334
335#define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
336
337#define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
338
339#define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
340
341#define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
342
343#define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
344
345#define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
346
347#define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
348
349#define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
350
351#define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
352
353#define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
354
355#define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
356
357#define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
358
359#define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
360
361#define REG_DSI_8x60_PHY_CTRL_0 0x00000290
362
363#define REG_DSI_8x60_PHY_CTRL_1 0x00000294
364
365#define REG_DSI_8x60_PHY_CTRL_2 0x00000298
366
367#define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
368
369#define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
370
371#define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
372
373#define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
374
375#define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
376
377#define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
378
379#define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
380
381#define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
382
383#define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
384
385#define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
386
387#define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
388
389#define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
390
391#define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
392#define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
393
394static inline uint32_t REG_DSI_8960_LN(uint32_t i0) { return 0x00000300 + 0x40*i0; }
395
396static inline uint32_t REG_DSI_8960_LN_CFG_0(uint32_t i0) { return 0x00000300 + 0x40*i0; }
397
398static inline uint32_t REG_DSI_8960_LN_CFG_1(uint32_t i0) { return 0x00000304 + 0x40*i0; }
399
400static inline uint32_t REG_DSI_8960_LN_CFG_2(uint32_t i0) { return 0x00000308 + 0x40*i0; }
401
402static inline uint32_t REG_DSI_8960_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000030c + 0x40*i0; }
403
404static inline uint32_t REG_DSI_8960_LN_TEST_STR_0(uint32_t i0) { return 0x00000314 + 0x40*i0; }
405
406static inline uint32_t REG_DSI_8960_LN_TEST_STR_1(uint32_t i0) { return 0x00000318 + 0x40*i0; }
407
408#define REG_DSI_8960_PHY_LNCK_CFG_0 0x00000400
409
410#define REG_DSI_8960_PHY_LNCK_CFG_1 0x00000404
411
412#define REG_DSI_8960_PHY_LNCK_CFG_2 0x00000408
413
414#define REG_DSI_8960_PHY_LNCK_TEST_DATAPATH 0x0000040c
415
416#define REG_DSI_8960_PHY_LNCK_TEST_STR0 0x00000414
417
418#define REG_DSI_8960_PHY_LNCK_TEST_STR1 0x00000418
419
420#define REG_DSI_8960_PHY_TIMING_CTRL_0 0x00000440
421
422#define REG_DSI_8960_PHY_TIMING_CTRL_1 0x00000444
423
424#define REG_DSI_8960_PHY_TIMING_CTRL_2 0x00000448
425
426#define REG_DSI_8960_PHY_TIMING_CTRL_3 0x0000044c
427
428#define REG_DSI_8960_PHY_TIMING_CTRL_4 0x00000450
429
430#define REG_DSI_8960_PHY_TIMING_CTRL_5 0x00000454
431
432#define REG_DSI_8960_PHY_TIMING_CTRL_6 0x00000458
433
434#define REG_DSI_8960_PHY_TIMING_CTRL_7 0x0000045c
435
436#define REG_DSI_8960_PHY_TIMING_CTRL_8 0x00000460
437
438#define REG_DSI_8960_PHY_TIMING_CTRL_9 0x00000464
439
440#define REG_DSI_8960_PHY_TIMING_CTRL_10 0x00000468
441
442#define REG_DSI_8960_PHY_TIMING_CTRL_11 0x0000046c
443
444#define REG_DSI_8960_PHY_CTRL_0 0x00000470
445
446#define REG_DSI_8960_PHY_CTRL_1 0x00000474
447
448#define REG_DSI_8960_PHY_CTRL_2 0x00000478
449
450#define REG_DSI_8960_PHY_CTRL_3 0x0000047c
451
452#define REG_DSI_8960_PHY_STRENGTH_0 0x00000480
453
454#define REG_DSI_8960_PHY_STRENGTH_1 0x00000484
455
456#define REG_DSI_8960_PHY_STRENGTH_2 0x00000488
457
458#define REG_DSI_8960_PHY_BIST_CTRL_0 0x0000048c
459
460#define REG_DSI_8960_PHY_BIST_CTRL_1 0x00000490
461
462#define REG_DSI_8960_PHY_BIST_CTRL_2 0x00000494
463
464#define REG_DSI_8960_PHY_BIST_CTRL_3 0x00000498
465
466#define REG_DSI_8960_PHY_BIST_CTRL_4 0x0000049c
467
468#define REG_DSI_8960_PHY_LDO_CTRL 0x000004b0
469
470#define REG_DSI_8960_PHY_REGULATOR_CTRL_0 0x00000500
471
472#define REG_DSI_8960_PHY_REGULATOR_CTRL_1 0x00000504
473
474#define REG_DSI_8960_PHY_REGULATOR_CTRL_2 0x00000508
475
476#define REG_DSI_8960_PHY_REGULATOR_CTRL_3 0x0000050c
477
478#define REG_DSI_8960_PHY_REGULATOR_CTRL_4 0x00000510
479
480#define REG_DSI_8960_PHY_REGULATOR_CAL_PWR_CFG 0x00000518
481
482#define REG_DSI_8960_PHY_CAL_HW_TRIGGER 0x00000528
483
484#define REG_DSI_8960_PHY_CAL_SW_CFG_0 0x0000052c
485
486#define REG_DSI_8960_PHY_CAL_SW_CFG_1 0x00000530
487
488#define REG_DSI_8960_PHY_CAL_SW_CFG_2 0x00000534
489
490#define REG_DSI_8960_PHY_CAL_HW_CFG_0 0x00000538
491
492#define REG_DSI_8960_PHY_CAL_HW_CFG_1 0x0000053c
493
494#define REG_DSI_8960_PHY_CAL_HW_CFG_2 0x00000540
495
496#define REG_DSI_8960_PHY_CAL_HW_CFG_3 0x00000544
497
498#define REG_DSI_8960_PHY_CAL_HW_CFG_4 0x00000548
499
500#define REG_DSI_8960_PHY_CAL_STATUS 0x00000550
501#define DSI_8960_PHY_CAL_STATUS_CAL_BUSY 0x00000010
502
503
504#endif /* DSI_XML */