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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Author: Jani Nikula <jani.nikula@intel.com>
24 */
25
26#include <drm/drmP.h>
27#include <drm/drm_crtc.h>
28#include <drm/drm_edid.h>
29#include <drm/i915_drm.h>
30#include <linux/slab.h>
31#include "i915_drv.h"
32#include "intel_drv.h"
33#include "intel_dsi.h"
34#include "intel_dsi_cmd.h"
35
36/* the sub-encoders aka panel drivers */
37static const struct intel_dsi_device intel_dsi_devices[] = {
38};
39
40static void band_gap_reset(struct drm_i915_private *dev_priv)
41{
42 mutex_lock(&dev_priv->dpio_lock);
43
44 vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
45 vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
46 vlv_flisdsi_write(dev_priv, 0x0F, 0x0025);
47 udelay(150);
48 vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
49 vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
50
51 mutex_unlock(&dev_priv->dpio_lock);
52}
53
54static struct intel_dsi *intel_attached_dsi(struct drm_connector *connector)
55{
56 return container_of(intel_attached_encoder(connector),
57 struct intel_dsi, base);
58}
59
60static inline bool is_vid_mode(struct intel_dsi *intel_dsi)
61{
62 return intel_dsi->dev.type == INTEL_DSI_VIDEO_MODE;
63}
64
65static inline bool is_cmd_mode(struct intel_dsi *intel_dsi)
66{
67 return intel_dsi->dev.type == INTEL_DSI_COMMAND_MODE;
68}
69
70static void intel_dsi_hot_plug(struct intel_encoder *encoder)
71{
72 DRM_DEBUG_KMS("\n");
73}
74
75static bool intel_dsi_compute_config(struct intel_encoder *encoder,
76 struct intel_crtc_config *config)
77{
78 struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
79 base);
80 struct intel_connector *intel_connector = intel_dsi->attached_connector;
81 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
82 struct drm_display_mode *adjusted_mode = &config->adjusted_mode;
83 struct drm_display_mode *mode = &config->requested_mode;
84
85 DRM_DEBUG_KMS("\n");
86
87 if (fixed_mode)
88 intel_fixed_panel_mode(fixed_mode, adjusted_mode);
89
90 if (intel_dsi->dev.dev_ops->mode_fixup)
91 return intel_dsi->dev.dev_ops->mode_fixup(&intel_dsi->dev,
92 mode, adjusted_mode);
93
94 return true;
95}
96
97static void intel_dsi_pre_pll_enable(struct intel_encoder *encoder)
98{
99 DRM_DEBUG_KMS("\n");
100
101 vlv_enable_dsi_pll(encoder);
102}
103
104static void intel_dsi_device_ready(struct intel_encoder *encoder)
105{
106 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
107 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
108 int pipe = intel_crtc->pipe;
109 u32 val;
110
111 DRM_DEBUG_KMS("\n");
112
113 val = I915_READ(MIPI_PORT_CTRL(pipe));
114 I915_WRITE(MIPI_PORT_CTRL(pipe), val | LP_OUTPUT_HOLD);
115 usleep_range(1000, 1500);
116 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY | ULPS_STATE_EXIT);
117 usleep_range(2000, 2500);
118 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
119 usleep_range(2000, 2500);
120 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
121 usleep_range(2000, 2500);
122 I915_WRITE(MIPI_DEVICE_READY(pipe), DEVICE_READY);
123 usleep_range(2000, 2500);
124}
125static void intel_dsi_pre_enable(struct intel_encoder *encoder)
126{
127 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
128
129 DRM_DEBUG_KMS("\n");
130
131 if (intel_dsi->dev.dev_ops->panel_reset)
132 intel_dsi->dev.dev_ops->panel_reset(&intel_dsi->dev);
133
134 /* put device in ready state */
135 intel_dsi_device_ready(encoder);
136
137 if (intel_dsi->dev.dev_ops->send_otp_cmds)
138 intel_dsi->dev.dev_ops->send_otp_cmds(&intel_dsi->dev);
139}
140
141static void intel_dsi_enable(struct intel_encoder *encoder)
142{
143 struct drm_device *dev = encoder->base.dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
145 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
146 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
147 int pipe = intel_crtc->pipe;
148 u32 temp;
149
150 DRM_DEBUG_KMS("\n");
151
152 if (is_cmd_mode(intel_dsi))
153 I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(pipe), 8 * 4);
154 else {
155 msleep(20); /* XXX */
156 dpi_send_cmd(intel_dsi, TURN_ON);
157 msleep(100);
158
159 /* assert ip_tg_enable signal */
160 temp = I915_READ(MIPI_PORT_CTRL(pipe)) & ~LANE_CONFIGURATION_MASK;
161 temp = temp | intel_dsi->port_bits;
162 I915_WRITE(MIPI_PORT_CTRL(pipe), temp | DPI_ENABLE);
163 POSTING_READ(MIPI_PORT_CTRL(pipe));
164 }
165
166 if (intel_dsi->dev.dev_ops->enable)
167 intel_dsi->dev.dev_ops->enable(&intel_dsi->dev);
168}
169
170static void intel_dsi_disable(struct intel_encoder *encoder)
171{
172 struct drm_device *dev = encoder->base.dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
174 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
175 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
176 int pipe = intel_crtc->pipe;
177 u32 temp;
178
179 DRM_DEBUG_KMS("\n");
180
181 if (is_vid_mode(intel_dsi)) {
182 dpi_send_cmd(intel_dsi, SHUTDOWN);
183 msleep(10);
184
185 /* de-assert ip_tg_enable signal */
186 temp = I915_READ(MIPI_PORT_CTRL(pipe));
187 I915_WRITE(MIPI_PORT_CTRL(pipe), temp & ~DPI_ENABLE);
188 POSTING_READ(MIPI_PORT_CTRL(pipe));
189
190 msleep(2);
191 }
192
193 /* if disable packets are sent before sending shutdown packet then in
194 * some next enable sequence send turn on packet error is observed */
195 if (intel_dsi->dev.dev_ops->disable)
196 intel_dsi->dev.dev_ops->disable(&intel_dsi->dev);
197}
198
199static void intel_dsi_clear_device_ready(struct intel_encoder *encoder)
200{
201 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
202 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
203 int pipe = intel_crtc->pipe;
204 u32 val;
205
206 DRM_DEBUG_KMS("\n");
207
208 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
209 usleep_range(2000, 2500);
210
211 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_EXIT);
212 usleep_range(2000, 2500);
213
214 I915_WRITE(MIPI_DEVICE_READY(pipe), ULPS_STATE_ENTER);
215 usleep_range(2000, 2500);
216
217 val = I915_READ(MIPI_PORT_CTRL(pipe));
218 I915_WRITE(MIPI_PORT_CTRL(pipe), val & ~LP_OUTPUT_HOLD);
219 usleep_range(1000, 1500);
220
221 if (wait_for(((I915_READ(MIPI_PORT_CTRL(pipe)) & AFE_LATCHOUT)
222 == 0x00000), 30))
223 DRM_ERROR("DSI LP not going Low\n");
224
225 I915_WRITE(MIPI_DEVICE_READY(pipe), 0x00);
226 usleep_range(2000, 2500);
227
228 vlv_disable_dsi_pll(encoder);
229}
230static void intel_dsi_post_disable(struct intel_encoder *encoder)
231{
232 struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
233
234 DRM_DEBUG_KMS("\n");
235
236 intel_dsi_clear_device_ready(encoder);
237
238 if (intel_dsi->dev.dev_ops->disable_panel_power)
239 intel_dsi->dev.dev_ops->disable_panel_power(&intel_dsi->dev);
240}
241
242static bool intel_dsi_get_hw_state(struct intel_encoder *encoder,
243 enum pipe *pipe)
244{
245 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
246 enum intel_display_power_domain power_domain;
247 u32 port, func;
248 enum pipe p;
249
250 DRM_DEBUG_KMS("\n");
251
252 power_domain = intel_display_port_power_domain(encoder);
253 if (!intel_display_power_enabled(dev_priv, power_domain))
254 return false;
255
256 /* XXX: this only works for one DSI output */
257 for (p = PIPE_A; p <= PIPE_B; p++) {
258 port = I915_READ(MIPI_PORT_CTRL(p));
259 func = I915_READ(MIPI_DSI_FUNC_PRG(p));
260
261 if ((port & DPI_ENABLE) || (func & CMD_MODE_DATA_WIDTH_MASK)) {
262 if (I915_READ(MIPI_DEVICE_READY(p)) & DEVICE_READY) {
263 *pipe = p;
264 return true;
265 }
266 }
267 }
268
269 return false;
270}
271
272static void intel_dsi_get_config(struct intel_encoder *encoder,
273 struct intel_crtc_config *pipe_config)
274{
275 DRM_DEBUG_KMS("\n");
276
277 /* XXX: read flags, set to adjusted_mode */
278}
279
280static enum drm_mode_status
281intel_dsi_mode_valid(struct drm_connector *connector,
282 struct drm_display_mode *mode)
283{
284 struct intel_connector *intel_connector = to_intel_connector(connector);
285 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
286 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
287
288 DRM_DEBUG_KMS("\n");
289
290 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) {
291 DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n");
292 return MODE_NO_DBLESCAN;
293 }
294
295 if (fixed_mode) {
296 if (mode->hdisplay > fixed_mode->hdisplay)
297 return MODE_PANEL;
298 if (mode->vdisplay > fixed_mode->vdisplay)
299 return MODE_PANEL;
300 }
301
302 return intel_dsi->dev.dev_ops->mode_valid(&intel_dsi->dev, mode);
303}
304
305/* return txclkesc cycles in terms of divider and duration in us */
306static u16 txclkesc(u32 divider, unsigned int us)
307{
308 switch (divider) {
309 case ESCAPE_CLOCK_DIVIDER_1:
310 default:
311 return 20 * us;
312 case ESCAPE_CLOCK_DIVIDER_2:
313 return 10 * us;
314 case ESCAPE_CLOCK_DIVIDER_4:
315 return 5 * us;
316 }
317}
318
319/* return pixels in terms of txbyteclkhs */
320static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count)
321{
322 return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp, 8), lane_count);
323}
324
325static void set_dsi_timings(struct drm_encoder *encoder,
326 const struct drm_display_mode *mode)
327{
328 struct drm_device *dev = encoder->dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
331 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
332 int pipe = intel_crtc->pipe;
333 unsigned int bpp = intel_crtc->config.pipe_bpp;
334 unsigned int lane_count = intel_dsi->lane_count;
335
336 u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp;
337
338 hactive = mode->hdisplay;
339 hfp = mode->hsync_start - mode->hdisplay;
340 hsync = mode->hsync_end - mode->hsync_start;
341 hbp = mode->htotal - mode->hsync_end;
342
343 vfp = mode->vsync_start - mode->vdisplay;
344 vsync = mode->vsync_end - mode->vsync_start;
345 vbp = mode->vtotal - mode->vsync_end;
346
347 /* horizontal values are in terms of high speed byte clock */
348 hactive = txbyteclkhs(hactive, bpp, lane_count);
349 hfp = txbyteclkhs(hfp, bpp, lane_count);
350 hsync = txbyteclkhs(hsync, bpp, lane_count);
351 hbp = txbyteclkhs(hbp, bpp, lane_count);
352
353 I915_WRITE(MIPI_HACTIVE_AREA_COUNT(pipe), hactive);
354 I915_WRITE(MIPI_HFP_COUNT(pipe), hfp);
355
356 /* meaningful for video mode non-burst sync pulse mode only, can be zero
357 * for non-burst sync events and burst modes */
358 I915_WRITE(MIPI_HSYNC_PADDING_COUNT(pipe), hsync);
359 I915_WRITE(MIPI_HBP_COUNT(pipe), hbp);
360
361 /* vertical values are in terms of lines */
362 I915_WRITE(MIPI_VFP_COUNT(pipe), vfp);
363 I915_WRITE(MIPI_VSYNC_PADDING_COUNT(pipe), vsync);
364 I915_WRITE(MIPI_VBP_COUNT(pipe), vbp);
365}
366
367static void intel_dsi_mode_set(struct intel_encoder *intel_encoder)
368{
369 struct drm_encoder *encoder = &intel_encoder->base;
370 struct drm_device *dev = encoder->dev;
371 struct drm_i915_private *dev_priv = dev->dev_private;
372 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
373 struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
374 struct drm_display_mode *adjusted_mode =
375 &intel_crtc->config.adjusted_mode;
376 int pipe = intel_crtc->pipe;
377 unsigned int bpp = intel_crtc->config.pipe_bpp;
378 u32 val, tmp;
379
380 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
381
382 /* XXX: Location of the call */
383 band_gap_reset(dev_priv);
384
385 /* escape clock divider, 20MHz, shared for A and C. device ready must be
386 * off when doing this! txclkesc? */
387 tmp = I915_READ(MIPI_CTRL(0));
388 tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
389 I915_WRITE(MIPI_CTRL(0), tmp | ESCAPE_CLOCK_DIVIDER_1);
390
391 /* read request priority is per pipe */
392 tmp = I915_READ(MIPI_CTRL(pipe));
393 tmp &= ~READ_REQUEST_PRIORITY_MASK;
394 I915_WRITE(MIPI_CTRL(pipe), tmp | READ_REQUEST_PRIORITY_HIGH);
395
396 /* XXX: why here, why like this? handling in irq handler?! */
397 I915_WRITE(MIPI_INTR_STAT(pipe), 0xffffffff);
398 I915_WRITE(MIPI_INTR_EN(pipe), 0xffffffff);
399
400 I915_WRITE(MIPI_DPHY_PARAM(pipe), intel_dsi->dphy_reg);
401
402 I915_WRITE(MIPI_DPI_RESOLUTION(pipe),
403 adjusted_mode->vdisplay << VERTICAL_ADDRESS_SHIFT |
404 adjusted_mode->hdisplay << HORIZONTAL_ADDRESS_SHIFT);
405
406 set_dsi_timings(encoder, adjusted_mode);
407
408 val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
409 if (is_cmd_mode(intel_dsi)) {
410 val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
411 val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
412 } else {
413 val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
414
415 /* XXX: cross-check bpp vs. pixel format? */
416 val |= intel_dsi->pixel_format;
417 }
418 I915_WRITE(MIPI_DSI_FUNC_PRG(pipe), val);
419
420 /* timeouts for recovery. one frame IIUC. if counter expires, EOT and
421 * stop state. */
422
423 /*
424 * In burst mode, value greater than one DPI line Time in byte clock
425 * (txbyteclkhs) To timeout this timer 1+ of the above said value is
426 * recommended.
427 *
428 * In non-burst mode, Value greater than one DPI frame time in byte
429 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
430 * is recommended.
431 *
432 * In DBI only mode, value greater than one DBI frame time in byte
433 * clock(txbyteclkhs) To timeout this timer 1+ of the above said value
434 * is recommended.
435 */
436
437 if (is_vid_mode(intel_dsi) &&
438 intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
439 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
440 txbyteclkhs(adjusted_mode->htotal, bpp,
441 intel_dsi->lane_count) + 1);
442 } else {
443 I915_WRITE(MIPI_HS_TX_TIMEOUT(pipe),
444 txbyteclkhs(adjusted_mode->vtotal *
445 adjusted_mode->htotal,
446 bpp, intel_dsi->lane_count) + 1);
447 }
448 I915_WRITE(MIPI_LP_RX_TIMEOUT(pipe), intel_dsi->lp_rx_timeout);
449 I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(pipe), intel_dsi->turn_arnd_val);
450 I915_WRITE(MIPI_DEVICE_RESET_TIMER(pipe), intel_dsi->rst_timer_val);
451
452 /* dphy stuff */
453
454 /* in terms of low power clock */
455 I915_WRITE(MIPI_INIT_COUNT(pipe), txclkesc(ESCAPE_CLOCK_DIVIDER_1, 100));
456
457 /* recovery disables */
458 I915_WRITE(MIPI_EOT_DISABLE(pipe), intel_dsi->eot_disable);
459
460 /* in terms of txbyteclkhs. actual high to low switch +
461 * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
462 *
463 * XXX: write MIPI_STOP_STATE_STALL?
464 */
465 I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(pipe),
466 intel_dsi->hs_to_lp_count);
467
468 /* XXX: low power clock equivalence in terms of byte clock. the number
469 * of byte clocks occupied in one low power clock. based on txbyteclkhs
470 * and txclkesc. txclkesc time / txbyteclk time * (105 +
471 * MIPI_STOP_STATE_STALL) / 105.???
472 */
473 I915_WRITE(MIPI_LP_BYTECLK(pipe), intel_dsi->lp_byte_clk);
474
475 /* the bw essential for transmitting 16 long packets containing 252
476 * bytes meant for dcs write memory command is programmed in this
477 * register in terms of byte clocks. based on dsi transfer rate and the
478 * number of lanes configured the time taken to transmit 16 long packets
479 * in a dsi stream varies. */
480 I915_WRITE(MIPI_DBI_BW_CTRL(pipe), intel_dsi->bw_timer);
481
482 I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe),
483 intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT |
484 intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
485
486 if (is_vid_mode(intel_dsi))
487 I915_WRITE(MIPI_VIDEO_MODE_FORMAT(pipe),
488 intel_dsi->video_frmt_cfg_bits |
489 intel_dsi->video_mode_format);
490}
491
492static enum drm_connector_status
493intel_dsi_detect(struct drm_connector *connector, bool force)
494{
495 struct intel_dsi *intel_dsi = intel_attached_dsi(connector);
496 struct intel_encoder *intel_encoder = &intel_dsi->base;
497 enum intel_display_power_domain power_domain;
498 enum drm_connector_status connector_status;
499 struct drm_i915_private *dev_priv = intel_encoder->base.dev->dev_private;
500
501 DRM_DEBUG_KMS("\n");
502 power_domain = intel_display_port_power_domain(intel_encoder);
503
504 intel_display_power_get(dev_priv, power_domain);
505 connector_status = intel_dsi->dev.dev_ops->detect(&intel_dsi->dev);
506 intel_display_power_put(dev_priv, power_domain);
507
508 return connector_status;
509}
510
511static int intel_dsi_get_modes(struct drm_connector *connector)
512{
513 struct intel_connector *intel_connector = to_intel_connector(connector);
514 struct drm_display_mode *mode;
515
516 DRM_DEBUG_KMS("\n");
517
518 if (!intel_connector->panel.fixed_mode) {
519 DRM_DEBUG_KMS("no fixed mode\n");
520 return 0;
521 }
522
523 mode = drm_mode_duplicate(connector->dev,
524 intel_connector->panel.fixed_mode);
525 if (!mode) {
526 DRM_DEBUG_KMS("drm_mode_duplicate failed\n");
527 return 0;
528 }
529
530 drm_mode_probed_add(connector, mode);
531 return 1;
532}
533
534static void intel_dsi_destroy(struct drm_connector *connector)
535{
536 struct intel_connector *intel_connector = to_intel_connector(connector);
537
538 DRM_DEBUG_KMS("\n");
539 intel_panel_fini(&intel_connector->panel);
540 drm_connector_cleanup(connector);
541 kfree(connector);
542}
543
544static const struct drm_encoder_funcs intel_dsi_funcs = {
545 .destroy = intel_encoder_destroy,
546};
547
548static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = {
549 .get_modes = intel_dsi_get_modes,
550 .mode_valid = intel_dsi_mode_valid,
551 .best_encoder = intel_best_encoder,
552};
553
554static const struct drm_connector_funcs intel_dsi_connector_funcs = {
555 .dpms = intel_connector_dpms,
556 .detect = intel_dsi_detect,
557 .destroy = intel_dsi_destroy,
558 .fill_modes = drm_helper_probe_single_connector_modes,
559};
560
561bool intel_dsi_init(struct drm_device *dev)
562{
563 struct intel_dsi *intel_dsi;
564 struct intel_encoder *intel_encoder;
565 struct drm_encoder *encoder;
566 struct intel_connector *intel_connector;
567 struct drm_connector *connector;
568 struct drm_display_mode *fixed_mode = NULL;
569 const struct intel_dsi_device *dsi;
570 unsigned int i;
571
572 DRM_DEBUG_KMS("\n");
573
574 intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
575 if (!intel_dsi)
576 return false;
577
578 intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL);
579 if (!intel_connector) {
580 kfree(intel_dsi);
581 return false;
582 }
583
584 intel_encoder = &intel_dsi->base;
585 encoder = &intel_encoder->base;
586 intel_dsi->attached_connector = intel_connector;
587
588 connector = &intel_connector->base;
589
590 drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI);
591
592 /* XXX: very likely not all of these are needed */
593 intel_encoder->hot_plug = intel_dsi_hot_plug;
594 intel_encoder->compute_config = intel_dsi_compute_config;
595 intel_encoder->pre_pll_enable = intel_dsi_pre_pll_enable;
596 intel_encoder->pre_enable = intel_dsi_pre_enable;
597 intel_encoder->enable = intel_dsi_enable;
598 intel_encoder->mode_set = intel_dsi_mode_set;
599 intel_encoder->disable = intel_dsi_disable;
600 intel_encoder->post_disable = intel_dsi_post_disable;
601 intel_encoder->get_hw_state = intel_dsi_get_hw_state;
602 intel_encoder->get_config = intel_dsi_get_config;
603
604 intel_connector->get_hw_state = intel_connector_get_hw_state;
605 intel_connector->unregister = intel_connector_unregister;
606
607 for (i = 0; i < ARRAY_SIZE(intel_dsi_devices); i++) {
608 dsi = &intel_dsi_devices[i];
609 intel_dsi->dev = *dsi;
610
611 if (dsi->dev_ops->init(&intel_dsi->dev))
612 break;
613 }
614
615 if (i == ARRAY_SIZE(intel_dsi_devices)) {
616 DRM_DEBUG_KMS("no device found\n");
617 goto err;
618 }
619
620 intel_encoder->type = INTEL_OUTPUT_DSI;
621 intel_encoder->crtc_mask = (1 << 0); /* XXX */
622
623 intel_encoder->cloneable = 0;
624 drm_connector_init(dev, connector, &intel_dsi_connector_funcs,
625 DRM_MODE_CONNECTOR_DSI);
626
627 drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs);
628
629 connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/
630 connector->interlace_allowed = false;
631 connector->doublescan_allowed = false;
632
633 intel_connector_attach_encoder(intel_connector, intel_encoder);
634
635 drm_sysfs_connector_add(connector);
636
637 fixed_mode = dsi->dev_ops->get_modes(&intel_dsi->dev);
638 if (!fixed_mode) {
639 DRM_DEBUG_KMS("no fixed mode\n");
640 goto err;
641 }
642
643 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
644 intel_panel_init(&intel_connector->panel, fixed_mode, NULL);
645
646 return true;
647
648err:
649 drm_encoder_cleanup(&intel_encoder->base);
650 kfree(intel_dsi);
651 kfree(intel_connector);
652
653 return false;
654}