Loading...
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29
30/*
31 * The Bridge device's PCI config space has information about the
32 * fb aperture size and the amount of pre-reserved memory.
33 * This is all handled in the intel-gtt.ko module. i915.ko only
34 * cares about the vga bit for the vga rbiter.
35 */
36#define INTEL_GMCH_CTRL 0x52
37#define INTEL_GMCH_VGA_DISABLE (1 << 1)
38
39/* PCI config space */
40
41#define HPLLCC 0xc0 /* 855 only */
42#define GC_CLOCK_CONTROL_MASK (0xf << 0)
43#define GC_CLOCK_133_200 (0 << 0)
44#define GC_CLOCK_100_200 (1 << 0)
45#define GC_CLOCK_100_133 (2 << 0)
46#define GC_CLOCK_166_250 (3 << 0)
47#define GCFGC2 0xda
48#define GCFGC 0xf0 /* 915+ only */
49#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
50#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
51#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
52#define GC_DISPLAY_CLOCK_MASK (7 << 4)
53#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
54#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
55#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
56#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
57#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
58#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
59#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
60#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
61#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
62#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
63#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
64#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
65#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
66#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
67#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
68#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
69#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
70#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
71#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
72#define LBB 0xf4
73
74/* Graphics reset regs */
75#define I965_GDRST 0xc0 /* PCI config register */
76#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
77#define GRDOM_FULL (0<<2)
78#define GRDOM_RENDER (1<<2)
79#define GRDOM_MEDIA (3<<2)
80
81#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
82#define GEN6_MBC_SNPCR_SHIFT 21
83#define GEN6_MBC_SNPCR_MASK (3<<21)
84#define GEN6_MBC_SNPCR_MAX (0<<21)
85#define GEN6_MBC_SNPCR_MED (1<<21)
86#define GEN6_MBC_SNPCR_LOW (2<<21)
87#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
88
89#define GEN6_GDRST 0x941c
90#define GEN6_GRDOM_FULL (1 << 0)
91#define GEN6_GRDOM_RENDER (1 << 1)
92#define GEN6_GRDOM_MEDIA (1 << 2)
93#define GEN6_GRDOM_BLT (1 << 3)
94
95/* VGA stuff */
96
97#define VGA_ST01_MDA 0x3ba
98#define VGA_ST01_CGA 0x3da
99
100#define VGA_MSR_WRITE 0x3c2
101#define VGA_MSR_READ 0x3cc
102#define VGA_MSR_MEM_EN (1<<1)
103#define VGA_MSR_CGA_MODE (1<<0)
104
105#define VGA_SR_INDEX 0x3c4
106#define VGA_SR_DATA 0x3c5
107
108#define VGA_AR_INDEX 0x3c0
109#define VGA_AR_VID_EN (1<<5)
110#define VGA_AR_DATA_WRITE 0x3c0
111#define VGA_AR_DATA_READ 0x3c1
112
113#define VGA_GR_INDEX 0x3ce
114#define VGA_GR_DATA 0x3cf
115/* GR05 */
116#define VGA_GR_MEM_READ_MODE_SHIFT 3
117#define VGA_GR_MEM_READ_MODE_PLANE 1
118/* GR06 */
119#define VGA_GR_MEM_MODE_MASK 0xc
120#define VGA_GR_MEM_MODE_SHIFT 2
121#define VGA_GR_MEM_A0000_AFFFF 0
122#define VGA_GR_MEM_A0000_BFFFF 1
123#define VGA_GR_MEM_B0000_B7FFF 2
124#define VGA_GR_MEM_B0000_BFFFF 3
125
126#define VGA_DACMASK 0x3c6
127#define VGA_DACRX 0x3c7
128#define VGA_DACWX 0x3c8
129#define VGA_DACDATA 0x3c9
130
131#define VGA_CR_INDEX_MDA 0x3b4
132#define VGA_CR_DATA_MDA 0x3b5
133#define VGA_CR_INDEX_CGA 0x3d4
134#define VGA_CR_DATA_CGA 0x3d5
135
136/*
137 * Memory interface instructions used by the kernel
138 */
139#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
140
141#define MI_NOOP MI_INSTR(0, 0)
142#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
143#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
144#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
145#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
146#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
147#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
148#define MI_FLUSH MI_INSTR(0x04, 0)
149#define MI_READ_FLUSH (1 << 0)
150#define MI_EXE_FLUSH (1 << 1)
151#define MI_NO_WRITE_FLUSH (1 << 2)
152#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
153#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
154#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
155#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
156#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
157#define MI_SUSPEND_FLUSH_EN (1<<0)
158#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
159#define MI_OVERLAY_FLIP MI_INSTR(0x11,0)
160#define MI_OVERLAY_CONTINUE (0x0<<21)
161#define MI_OVERLAY_ON (0x1<<21)
162#define MI_OVERLAY_OFF (0x2<<21)
163#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
164#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
165#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
166#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
167#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
168#define MI_MM_SPACE_GTT (1<<8)
169#define MI_MM_SPACE_PHYSICAL (0<<8)
170#define MI_SAVE_EXT_STATE_EN (1<<3)
171#define MI_RESTORE_EXT_STATE_EN (1<<2)
172#define MI_FORCE_RESTORE (1<<1)
173#define MI_RESTORE_INHIBIT (1<<0)
174#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
175#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
176#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
177#define MI_STORE_DWORD_INDEX_SHIFT 2
178/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
179 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
180 * simply ignores the register load under certain conditions.
181 * - One can actually load arbitrary many arbitrary registers: Simply issue x
182 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
183 */
184#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
185#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
186#define MI_INVALIDATE_TLB (1<<18)
187#define MI_INVALIDATE_BSD (1<<7)
188#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
189#define MI_BATCH_NON_SECURE (1)
190#define MI_BATCH_NON_SECURE_I965 (1<<8)
191#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
192#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
193#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
194#define MI_SEMAPHORE_UPDATE (1<<21)
195#define MI_SEMAPHORE_COMPARE (1<<20)
196#define MI_SEMAPHORE_REGISTER (1<<18)
197/*
198 * 3D instructions used by the kernel
199 */
200#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
201
202#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
203#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
204#define SC_UPDATE_SCISSOR (0x1<<1)
205#define SC_ENABLE_MASK (0x1<<0)
206#define SC_ENABLE (0x1<<0)
207#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
208#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
209#define SCI_YMIN_MASK (0xffff<<16)
210#define SCI_XMIN_MASK (0xffff<<0)
211#define SCI_YMAX_MASK (0xffff<<16)
212#define SCI_XMAX_MASK (0xffff<<0)
213#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
214#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
215#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
216#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
217#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
218#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
219#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
220#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
221#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
222#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
223#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
224#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
225#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
226#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
227#define BLT_DEPTH_8 (0<<24)
228#define BLT_DEPTH_16_565 (1<<24)
229#define BLT_DEPTH_16_1555 (2<<24)
230#define BLT_DEPTH_32 (3<<24)
231#define BLT_ROP_GXCOPY (0xcc<<16)
232#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
233#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
234#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
235#define ASYNC_FLIP (1<<22)
236#define DISPLAY_PLANE_A (0<<20)
237#define DISPLAY_PLANE_B (1<<20)
238#define GFX_OP_PIPE_CONTROL ((0x3<<29)|(0x3<<27)|(0x2<<24)|2)
239#define PIPE_CONTROL_QW_WRITE (1<<14)
240#define PIPE_CONTROL_DEPTH_STALL (1<<13)
241#define PIPE_CONTROL_WC_FLUSH (1<<12)
242#define PIPE_CONTROL_IS_FLUSH (1<<11) /* MBZ on Ironlake */
243#define PIPE_CONTROL_TC_FLUSH (1<<10) /* GM45+ only */
244#define PIPE_CONTROL_ISP_DIS (1<<9)
245#define PIPE_CONTROL_NOTIFY (1<<8)
246#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
247#define PIPE_CONTROL_STALL_EN (1<<1) /* in addr word, Ironlake+ only */
248
249
250/*
251 * Reset registers
252 */
253#define DEBUG_RESET_I830 0x6070
254#define DEBUG_RESET_FULL (1<<7)
255#define DEBUG_RESET_RENDER (1<<8)
256#define DEBUG_RESET_DISPLAY (1<<9)
257
258
259/*
260 * Fence registers
261 */
262#define FENCE_REG_830_0 0x2000
263#define FENCE_REG_945_8 0x3000
264#define I830_FENCE_START_MASK 0x07f80000
265#define I830_FENCE_TILING_Y_SHIFT 12
266#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
267#define I830_FENCE_PITCH_SHIFT 4
268#define I830_FENCE_REG_VALID (1<<0)
269#define I915_FENCE_MAX_PITCH_VAL 4
270#define I830_FENCE_MAX_PITCH_VAL 6
271#define I830_FENCE_MAX_SIZE_VAL (1<<8)
272
273#define I915_FENCE_START_MASK 0x0ff00000
274#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
275
276#define FENCE_REG_965_0 0x03000
277#define I965_FENCE_PITCH_SHIFT 2
278#define I965_FENCE_TILING_Y_SHIFT 1
279#define I965_FENCE_REG_VALID (1<<0)
280#define I965_FENCE_MAX_PITCH_VAL 0x0400
281
282#define FENCE_REG_SANDYBRIDGE_0 0x100000
283#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
284
285/*
286 * Instruction and interrupt control regs
287 */
288#define PGTBL_ER 0x02024
289#define RENDER_RING_BASE 0x02000
290#define BSD_RING_BASE 0x04000
291#define GEN6_BSD_RING_BASE 0x12000
292#define BLT_RING_BASE 0x22000
293#define RING_TAIL(base) ((base)+0x30)
294#define RING_HEAD(base) ((base)+0x34)
295#define RING_START(base) ((base)+0x38)
296#define RING_CTL(base) ((base)+0x3c)
297#define RING_SYNC_0(base) ((base)+0x40)
298#define RING_SYNC_1(base) ((base)+0x44)
299#define RING_MAX_IDLE(base) ((base)+0x54)
300#define RING_HWS_PGA(base) ((base)+0x80)
301#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
302#define RENDER_HWS_PGA_GEN7 (0x04080)
303#define BSD_HWS_PGA_GEN7 (0x04180)
304#define BLT_HWS_PGA_GEN7 (0x04280)
305#define RING_ACTHD(base) ((base)+0x74)
306#define RING_NOPID(base) ((base)+0x94)
307#define RING_IMR(base) ((base)+0xa8)
308#define TAIL_ADDR 0x001FFFF8
309#define HEAD_WRAP_COUNT 0xFFE00000
310#define HEAD_WRAP_ONE 0x00200000
311#define HEAD_ADDR 0x001FFFFC
312#define RING_NR_PAGES 0x001FF000
313#define RING_REPORT_MASK 0x00000006
314#define RING_REPORT_64K 0x00000002
315#define RING_REPORT_128K 0x00000004
316#define RING_NO_REPORT 0x00000000
317#define RING_VALID_MASK 0x00000001
318#define RING_VALID 0x00000001
319#define RING_INVALID 0x00000000
320#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
321#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
322#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
323#if 0
324#define PRB0_TAIL 0x02030
325#define PRB0_HEAD 0x02034
326#define PRB0_START 0x02038
327#define PRB0_CTL 0x0203c
328#define PRB1_TAIL 0x02040 /* 915+ only */
329#define PRB1_HEAD 0x02044 /* 915+ only */
330#define PRB1_START 0x02048 /* 915+ only */
331#define PRB1_CTL 0x0204c /* 915+ only */
332#endif
333#define IPEIR_I965 0x02064
334#define IPEHR_I965 0x02068
335#define INSTDONE_I965 0x0206c
336#define INSTPS 0x02070 /* 965+ only */
337#define INSTDONE1 0x0207c /* 965+ only */
338#define ACTHD_I965 0x02074
339#define HWS_PGA 0x02080
340#define HWS_ADDRESS_MASK 0xfffff000
341#define HWS_START_ADDRESS_SHIFT 4
342#define PWRCTXA 0x2088 /* 965GM+ only */
343#define PWRCTX_EN (1<<0)
344#define IPEIR 0x02088
345#define IPEHR 0x0208c
346#define INSTDONE 0x02090
347#define NOPID 0x02094
348#define HWSTAM 0x02098
349#define VCS_INSTDONE 0x1206C
350#define VCS_IPEIR 0x12064
351#define VCS_IPEHR 0x12068
352#define VCS_ACTHD 0x12074
353#define BCS_INSTDONE 0x2206C
354#define BCS_IPEIR 0x22064
355#define BCS_IPEHR 0x22068
356#define BCS_ACTHD 0x22074
357
358#define ERROR_GEN6 0x040a0
359
360/* GM45+ chicken bits -- debug workaround bits that may be required
361 * for various sorts of correct behavior. The top 16 bits of each are
362 * the enables for writing to the corresponding low bit.
363 */
364#define _3D_CHICKEN 0x02084
365#define _3D_CHICKEN2 0x0208c
366/* Disables pipelining of read flushes past the SF-WIZ interface.
367 * Required on all Ironlake steppings according to the B-Spec, but the
368 * particular danger of not doing so is not specified.
369 */
370# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
371#define _3D_CHICKEN3 0x02090
372
373#define MI_MODE 0x0209c
374# define VS_TIMER_DISPATCH (1 << 6)
375# define MI_FLUSH_ENABLE (1 << 11)
376
377#define GFX_MODE 0x02520
378#define GFX_MODE_GEN7 0x0229c
379#define GFX_RUN_LIST_ENABLE (1<<15)
380#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
381#define GFX_SURFACE_FAULT_ENABLE (1<<12)
382#define GFX_REPLAY_MODE (1<<11)
383#define GFX_PSMI_GRANULARITY (1<<10)
384#define GFX_PPGTT_ENABLE (1<<9)
385
386#define GFX_MODE_ENABLE(bit) (((bit) << 16) | (bit))
387#define GFX_MODE_DISABLE(bit) (((bit) << 16) | (0))
388
389#define SCPD0 0x0209c /* 915+ only */
390#define IER 0x020a0
391#define IIR 0x020a4
392#define IMR 0x020a8
393#define ISR 0x020ac
394#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
395#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
396#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
397#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
398#define I915_HWB_OOM_INTERRUPT (1<<13)
399#define I915_SYNC_STATUS_INTERRUPT (1<<12)
400#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
401#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
402#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
403#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
404#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
405#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
406#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
407#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
408#define I915_DEBUG_INTERRUPT (1<<2)
409#define I915_USER_INTERRUPT (1<<1)
410#define I915_ASLE_INTERRUPT (1<<0)
411#define I915_BSD_USER_INTERRUPT (1<<25)
412#define EIR 0x020b0
413#define EMR 0x020b4
414#define ESR 0x020b8
415#define GM45_ERROR_PAGE_TABLE (1<<5)
416#define GM45_ERROR_MEM_PRIV (1<<4)
417#define I915_ERROR_PAGE_TABLE (1<<4)
418#define GM45_ERROR_CP_PRIV (1<<3)
419#define I915_ERROR_MEMORY_REFRESH (1<<1)
420#define I915_ERROR_INSTRUCTION (1<<0)
421#define INSTPM 0x020c0
422#define INSTPM_SELF_EN (1<<12) /* 915GM only */
423#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
424 will not assert AGPBUSY# and will only
425 be delivered when out of C3. */
426#define ACTHD 0x020c8
427#define FW_BLC 0x020d8
428#define FW_BLC2 0x020dc
429#define FW_BLC_SELF 0x020e0 /* 915+ only */
430#define FW_BLC_SELF_EN_MASK (1<<31)
431#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
432#define FW_BLC_SELF_EN (1<<15) /* 945 only */
433#define MM_BURST_LENGTH 0x00700000
434#define MM_FIFO_WATERMARK 0x0001F000
435#define LM_BURST_LENGTH 0x00000700
436#define LM_FIFO_WATERMARK 0x0000001F
437#define MI_ARB_STATE 0x020e4 /* 915+ only */
438#define MI_ARB_MASK_SHIFT 16 /* shift for enable bits */
439
440/* Make render/texture TLB fetches lower priorty than associated data
441 * fetches. This is not turned on by default
442 */
443#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
444
445/* Isoch request wait on GTT enable (Display A/B/C streams).
446 * Make isoch requests stall on the TLB update. May cause
447 * display underruns (test mode only)
448 */
449#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
450
451/* Block grant count for isoch requests when block count is
452 * set to a finite value.
453 */
454#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
455#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
456#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
457#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
458#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
459
460/* Enable render writes to complete in C2/C3/C4 power states.
461 * If this isn't enabled, render writes are prevented in low
462 * power states. That seems bad to me.
463 */
464#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
465
466/* This acknowledges an async flip immediately instead
467 * of waiting for 2TLB fetches.
468 */
469#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
470
471/* Enables non-sequential data reads through arbiter
472 */
473#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
474
475/* Disable FSB snooping of cacheable write cycles from binner/render
476 * command stream
477 */
478#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
479
480/* Arbiter time slice for non-isoch streams */
481#define MI_ARB_TIME_SLICE_MASK (7 << 5)
482#define MI_ARB_TIME_SLICE_1 (0 << 5)
483#define MI_ARB_TIME_SLICE_2 (1 << 5)
484#define MI_ARB_TIME_SLICE_4 (2 << 5)
485#define MI_ARB_TIME_SLICE_6 (3 << 5)
486#define MI_ARB_TIME_SLICE_8 (4 << 5)
487#define MI_ARB_TIME_SLICE_10 (5 << 5)
488#define MI_ARB_TIME_SLICE_14 (6 << 5)
489#define MI_ARB_TIME_SLICE_16 (7 << 5)
490
491/* Low priority grace period page size */
492#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
493#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
494
495/* Disable display A/B trickle feed */
496#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
497
498/* Set display plane priority */
499#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
500#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
501
502#define CACHE_MODE_0 0x02120 /* 915+ only */
503#define CM0_MASK_SHIFT 16
504#define CM0_IZ_OPT_DISABLE (1<<6)
505#define CM0_ZR_OPT_DISABLE (1<<5)
506#define CM0_DEPTH_EVICT_DISABLE (1<<4)
507#define CM0_COLOR_EVICT_DISABLE (1<<3)
508#define CM0_DEPTH_WRITE_DISABLE (1<<1)
509#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
510#define BB_ADDR 0x02140 /* 8 bytes */
511#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
512#define ECOSKPD 0x021d0
513#define ECO_GATING_CX_ONLY (1<<3)
514#define ECO_FLIP_DONE (1<<0)
515
516/* GEN6 interrupt control */
517#define GEN6_RENDER_HWSTAM 0x2098
518#define GEN6_RENDER_IMR 0x20a8
519#define GEN6_RENDER_CONTEXT_SWITCH_INTERRUPT (1 << 8)
520#define GEN6_RENDER_PPGTT_PAGE_FAULT (1 << 7)
521#define GEN6_RENDER_TIMEOUT_COUNTER_EXPIRED (1 << 6)
522#define GEN6_RENDER_L3_PARITY_ERROR (1 << 5)
523#define GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT (1 << 4)
524#define GEN6_RENDER_COMMAND_PARSER_MASTER_ERROR (1 << 3)
525#define GEN6_RENDER_SYNC_STATUS (1 << 2)
526#define GEN6_RENDER_DEBUG_INTERRUPT (1 << 1)
527#define GEN6_RENDER_USER_INTERRUPT (1 << 0)
528
529#define GEN6_BLITTER_HWSTAM 0x22098
530#define GEN6_BLITTER_IMR 0x220a8
531#define GEN6_BLITTER_MI_FLUSH_DW_NOTIFY_INTERRUPT (1 << 26)
532#define GEN6_BLITTER_COMMAND_PARSER_MASTER_ERROR (1 << 25)
533#define GEN6_BLITTER_SYNC_STATUS (1 << 24)
534#define GEN6_BLITTER_USER_INTERRUPT (1 << 22)
535
536#define GEN6_BLITTER_ECOSKPD 0x221d0
537#define GEN6_BLITTER_LOCK_SHIFT 16
538#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
539
540#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
541#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK (1 << 16)
542#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE (1 << 0)
543#define GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE 0
544#define GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR (1 << 3)
545
546#define GEN6_BSD_HWSTAM 0x12098
547#define GEN6_BSD_IMR 0x120a8
548#define GEN6_BSD_USER_INTERRUPT (1 << 12)
549
550#define GEN6_BSD_RNCID 0x12198
551
552/*
553 * Framebuffer compression (915+ only)
554 */
555
556#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
557#define FBC_LL_BASE 0x03204 /* 4k page aligned */
558#define FBC_CONTROL 0x03208
559#define FBC_CTL_EN (1<<31)
560#define FBC_CTL_PERIODIC (1<<30)
561#define FBC_CTL_INTERVAL_SHIFT (16)
562#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
563#define FBC_CTL_C3_IDLE (1<<13)
564#define FBC_CTL_STRIDE_SHIFT (5)
565#define FBC_CTL_FENCENO (1<<0)
566#define FBC_COMMAND 0x0320c
567#define FBC_CMD_COMPRESS (1<<0)
568#define FBC_STATUS 0x03210
569#define FBC_STAT_COMPRESSING (1<<31)
570#define FBC_STAT_COMPRESSED (1<<30)
571#define FBC_STAT_MODIFIED (1<<29)
572#define FBC_STAT_CURRENT_LINE (1<<0)
573#define FBC_CONTROL2 0x03214
574#define FBC_CTL_FENCE_DBL (0<<4)
575#define FBC_CTL_IDLE_IMM (0<<2)
576#define FBC_CTL_IDLE_FULL (1<<2)
577#define FBC_CTL_IDLE_LINE (2<<2)
578#define FBC_CTL_IDLE_DEBUG (3<<2)
579#define FBC_CTL_CPU_FENCE (1<<1)
580#define FBC_CTL_PLANEA (0<<0)
581#define FBC_CTL_PLANEB (1<<0)
582#define FBC_FENCE_OFF 0x0321b
583#define FBC_TAG 0x03300
584
585#define FBC_LL_SIZE (1536)
586
587/* Framebuffer compression for GM45+ */
588#define DPFC_CB_BASE 0x3200
589#define DPFC_CONTROL 0x3208
590#define DPFC_CTL_EN (1<<31)
591#define DPFC_CTL_PLANEA (0<<30)
592#define DPFC_CTL_PLANEB (1<<30)
593#define DPFC_CTL_FENCE_EN (1<<29)
594#define DPFC_CTL_PERSISTENT_MODE (1<<25)
595#define DPFC_SR_EN (1<<10)
596#define DPFC_CTL_LIMIT_1X (0<<6)
597#define DPFC_CTL_LIMIT_2X (1<<6)
598#define DPFC_CTL_LIMIT_4X (2<<6)
599#define DPFC_RECOMP_CTL 0x320c
600#define DPFC_RECOMP_STALL_EN (1<<27)
601#define DPFC_RECOMP_STALL_WM_SHIFT (16)
602#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
603#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
604#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
605#define DPFC_STATUS 0x3210
606#define DPFC_INVAL_SEG_SHIFT (16)
607#define DPFC_INVAL_SEG_MASK (0x07ff0000)
608#define DPFC_COMP_SEG_SHIFT (0)
609#define DPFC_COMP_SEG_MASK (0x000003ff)
610#define DPFC_STATUS2 0x3214
611#define DPFC_FENCE_YOFF 0x3218
612#define DPFC_CHICKEN 0x3224
613#define DPFC_HT_MODIFY (1<<31)
614
615/* Framebuffer compression for Ironlake */
616#define ILK_DPFC_CB_BASE 0x43200
617#define ILK_DPFC_CONTROL 0x43208
618/* The bit 28-8 is reserved */
619#define DPFC_RESERVED (0x1FFFFF00)
620#define ILK_DPFC_RECOMP_CTL 0x4320c
621#define ILK_DPFC_STATUS 0x43210
622#define ILK_DPFC_FENCE_YOFF 0x43218
623#define ILK_DPFC_CHICKEN 0x43224
624#define ILK_FBC_RT_BASE 0x2128
625#define ILK_FBC_RT_VALID (1<<0)
626
627#define ILK_DISPLAY_CHICKEN1 0x42000
628#define ILK_FBCQ_DIS (1<<22)
629#define ILK_PABSTRETCH_DIS (1<<21)
630
631
632/*
633 * Framebuffer compression for Sandybridge
634 *
635 * The following two registers are of type GTTMMADR
636 */
637#define SNB_DPFC_CTL_SA 0x100100
638#define SNB_CPU_FENCE_ENABLE (1<<29)
639#define DPFC_CPU_FENCE_OFFSET 0x100104
640
641
642/*
643 * GPIO regs
644 */
645#define GPIOA 0x5010
646#define GPIOB 0x5014
647#define GPIOC 0x5018
648#define GPIOD 0x501c
649#define GPIOE 0x5020
650#define GPIOF 0x5024
651#define GPIOG 0x5028
652#define GPIOH 0x502c
653# define GPIO_CLOCK_DIR_MASK (1 << 0)
654# define GPIO_CLOCK_DIR_IN (0 << 1)
655# define GPIO_CLOCK_DIR_OUT (1 << 1)
656# define GPIO_CLOCK_VAL_MASK (1 << 2)
657# define GPIO_CLOCK_VAL_OUT (1 << 3)
658# define GPIO_CLOCK_VAL_IN (1 << 4)
659# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
660# define GPIO_DATA_DIR_MASK (1 << 8)
661# define GPIO_DATA_DIR_IN (0 << 9)
662# define GPIO_DATA_DIR_OUT (1 << 9)
663# define GPIO_DATA_VAL_MASK (1 << 10)
664# define GPIO_DATA_VAL_OUT (1 << 11)
665# define GPIO_DATA_VAL_IN (1 << 12)
666# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
667
668#define GMBUS0 0x5100 /* clock/port select */
669#define GMBUS_RATE_100KHZ (0<<8)
670#define GMBUS_RATE_50KHZ (1<<8)
671#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
672#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
673#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
674#define GMBUS_PORT_DISABLED 0
675#define GMBUS_PORT_SSC 1
676#define GMBUS_PORT_VGADDC 2
677#define GMBUS_PORT_PANEL 3
678#define GMBUS_PORT_DPC 4 /* HDMIC */
679#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
680 /* 6 reserved */
681#define GMBUS_PORT_DPD 7 /* HDMID */
682#define GMBUS_NUM_PORTS 8
683#define GMBUS1 0x5104 /* command/status */
684#define GMBUS_SW_CLR_INT (1<<31)
685#define GMBUS_SW_RDY (1<<30)
686#define GMBUS_ENT (1<<29) /* enable timeout */
687#define GMBUS_CYCLE_NONE (0<<25)
688#define GMBUS_CYCLE_WAIT (1<<25)
689#define GMBUS_CYCLE_INDEX (2<<25)
690#define GMBUS_CYCLE_STOP (4<<25)
691#define GMBUS_BYTE_COUNT_SHIFT 16
692#define GMBUS_SLAVE_INDEX_SHIFT 8
693#define GMBUS_SLAVE_ADDR_SHIFT 1
694#define GMBUS_SLAVE_READ (1<<0)
695#define GMBUS_SLAVE_WRITE (0<<0)
696#define GMBUS2 0x5108 /* status */
697#define GMBUS_INUSE (1<<15)
698#define GMBUS_HW_WAIT_PHASE (1<<14)
699#define GMBUS_STALL_TIMEOUT (1<<13)
700#define GMBUS_INT (1<<12)
701#define GMBUS_HW_RDY (1<<11)
702#define GMBUS_SATOER (1<<10)
703#define GMBUS_ACTIVE (1<<9)
704#define GMBUS3 0x510c /* data buffer bytes 3-0 */
705#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
706#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
707#define GMBUS_NAK_EN (1<<3)
708#define GMBUS_IDLE_EN (1<<2)
709#define GMBUS_HW_WAIT_EN (1<<1)
710#define GMBUS_HW_RDY_EN (1<<0)
711#define GMBUS5 0x5120 /* byte index */
712#define GMBUS_2BYTE_INDEX_EN (1<<31)
713
714/*
715 * Clock control & power management
716 */
717
718#define VGA0 0x6000
719#define VGA1 0x6004
720#define VGA_PD 0x6010
721#define VGA0_PD_P2_DIV_4 (1 << 7)
722#define VGA0_PD_P1_DIV_2 (1 << 5)
723#define VGA0_PD_P1_SHIFT 0
724#define VGA0_PD_P1_MASK (0x1f << 0)
725#define VGA1_PD_P2_DIV_4 (1 << 15)
726#define VGA1_PD_P1_DIV_2 (1 << 13)
727#define VGA1_PD_P1_SHIFT 8
728#define VGA1_PD_P1_MASK (0x1f << 8)
729#define _DPLL_A 0x06014
730#define _DPLL_B 0x06018
731#define DPLL(pipe) _PIPE(pipe, _DPLL_A, _DPLL_B)
732#define DPLL_VCO_ENABLE (1 << 31)
733#define DPLL_DVO_HIGH_SPEED (1 << 30)
734#define DPLL_SYNCLOCK_ENABLE (1 << 29)
735#define DPLL_VGA_MODE_DIS (1 << 28)
736#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
737#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
738#define DPLL_MODE_MASK (3 << 26)
739#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
740#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
741#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
742#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
743#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
744#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
745#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
746
747#define SRX_INDEX 0x3c4
748#define SRX_DATA 0x3c5
749#define SR01 1
750#define SR01_SCREEN_OFF (1<<5)
751
752#define PPCR 0x61204
753#define PPCR_ON (1<<0)
754
755#define DVOB 0x61140
756#define DVOB_ON (1<<31)
757#define DVOC 0x61160
758#define DVOC_ON (1<<31)
759#define LVDS 0x61180
760#define LVDS_ON (1<<31)
761
762/* Scratch pad debug 0 reg:
763 */
764#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
765/*
766 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
767 * this field (only one bit may be set).
768 */
769#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
770#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
771#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
772/* i830, required in DVO non-gang */
773#define PLL_P2_DIVIDE_BY_4 (1 << 23)
774#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
775#define PLL_REF_INPUT_DREFCLK (0 << 13)
776#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
777#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
778#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
779#define PLL_REF_INPUT_MASK (3 << 13)
780#define PLL_LOAD_PULSE_PHASE_SHIFT 9
781/* Ironlake */
782# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
783# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
784# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
785# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
786# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
787
788/*
789 * Parallel to Serial Load Pulse phase selection.
790 * Selects the phase for the 10X DPLL clock for the PCIe
791 * digital display port. The range is 4 to 13; 10 or more
792 * is just a flip delay. The default is 6
793 */
794#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
795#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
796/*
797 * SDVO multiplier for 945G/GM. Not used on 965.
798 */
799#define SDVO_MULTIPLIER_MASK 0x000000ff
800#define SDVO_MULTIPLIER_SHIFT_HIRES 4
801#define SDVO_MULTIPLIER_SHIFT_VGA 0
802#define _DPLL_A_MD 0x0601c /* 965+ only */
803/*
804 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
805 *
806 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
807 */
808#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
809#define DPLL_MD_UDI_DIVIDER_SHIFT 24
810/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
811#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
812#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
813/*
814 * SDVO/UDI pixel multiplier.
815 *
816 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
817 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
818 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
819 * dummy bytes in the datastream at an increased clock rate, with both sides of
820 * the link knowing how many bytes are fill.
821 *
822 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
823 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
824 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
825 * through an SDVO command.
826 *
827 * This register field has values of multiplication factor minus 1, with
828 * a maximum multiplier of 5 for SDVO.
829 */
830#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
831#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
832/*
833 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
834 * This best be set to the default value (3) or the CRT won't work. No,
835 * I don't entirely understand what this does...
836 */
837#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
838#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
839#define _DPLL_B_MD 0x06020 /* 965+ only */
840#define DPLL_MD(pipe) _PIPE(pipe, _DPLL_A_MD, _DPLL_B_MD)
841#define _FPA0 0x06040
842#define _FPA1 0x06044
843#define _FPB0 0x06048
844#define _FPB1 0x0604c
845#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
846#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
847#define FP_N_DIV_MASK 0x003f0000
848#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
849#define FP_N_DIV_SHIFT 16
850#define FP_M1_DIV_MASK 0x00003f00
851#define FP_M1_DIV_SHIFT 8
852#define FP_M2_DIV_MASK 0x0000003f
853#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
854#define FP_M2_DIV_SHIFT 0
855#define DPLL_TEST 0x606c
856#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
857#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
858#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
859#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
860#define DPLLB_TEST_N_BYPASS (1 << 19)
861#define DPLLB_TEST_M_BYPASS (1 << 18)
862#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
863#define DPLLA_TEST_N_BYPASS (1 << 3)
864#define DPLLA_TEST_M_BYPASS (1 << 2)
865#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
866#define D_STATE 0x6104
867#define DSTATE_GFX_RESET_I830 (1<<6)
868#define DSTATE_PLL_D3_OFF (1<<3)
869#define DSTATE_GFX_CLOCK_GATING (1<<1)
870#define DSTATE_DOT_CLOCK_GATING (1<<0)
871#define DSPCLK_GATE_D 0x6200
872# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
873# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
874# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
875# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
876# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
877# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
878# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
879# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
880# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
881# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
882# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
883# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
884# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
885# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
886# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
887# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
888# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
889# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
890# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
891# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
892# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
893# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
894# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
895# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
896# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
897# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
898# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
899# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
900/**
901 * This bit must be set on the 830 to prevent hangs when turning off the
902 * overlay scaler.
903 */
904# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
905# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
906# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
907# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
908# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
909
910#define RENCLK_GATE_D1 0x6204
911# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
912# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
913# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
914# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
915# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
916# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
917# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
918# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
919# define MAG_CLOCK_GATE_DISABLE (1 << 5)
920/** This bit must be unset on 855,865 */
921# define MECI_CLOCK_GATE_DISABLE (1 << 4)
922# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
923# define MEC_CLOCK_GATE_DISABLE (1 << 2)
924# define MECO_CLOCK_GATE_DISABLE (1 << 1)
925/** This bit must be set on 855,865. */
926# define SV_CLOCK_GATE_DISABLE (1 << 0)
927# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
928# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
929# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
930# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
931# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
932# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
933# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
934# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
935# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
936# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
937# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
938# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
939# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
940# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
941# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
942# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
943# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
944
945# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
946/** This bit must always be set on 965G/965GM */
947# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
948# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
949# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
950# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
951# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
952# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
953/** This bit must always be set on 965G */
954# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
955# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
956# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
957# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
958# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
959# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
960# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
961# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
962# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
963# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
964# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
965# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
966# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
967# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
968# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
969# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
970# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
971# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
972# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
973
974#define RENCLK_GATE_D2 0x6208
975#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
976#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
977#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
978#define RAMCLK_GATE_D 0x6210 /* CRL only */
979#define DEUC 0x6214 /* CRL only */
980
981/*
982 * Palette regs
983 */
984
985#define _PALETTE_A 0x0a000
986#define _PALETTE_B 0x0a800
987#define PALETTE(pipe) _PIPE(pipe, _PALETTE_A, _PALETTE_B)
988
989/* MCH MMIO space */
990
991/*
992 * MCHBAR mirror.
993 *
994 * This mirrors the MCHBAR MMIO space whose location is determined by
995 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
996 * every way. It is not accessible from the CP register read instructions.
997 *
998 */
999#define MCHBAR_MIRROR_BASE 0x10000
1000
1001#define MCHBAR_MIRROR_BASE_SNB 0x140000
1002
1003/** 915-945 and GM965 MCH register controlling DRAM channel access */
1004#define DCC 0x10200
1005#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1006#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1007#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1008#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1009#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1010#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1011
1012/** Pineview MCH register contains DDR3 setting */
1013#define CSHRDDR3CTL 0x101a8
1014#define CSHRDDR3CTL_DDR3 (1 << 2)
1015
1016/** 965 MCH register controlling DRAM channel configuration */
1017#define C0DRB3 0x10206
1018#define C1DRB3 0x10606
1019
1020/* Clocking configuration register */
1021#define CLKCFG 0x10c00
1022#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1023#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1024#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1025#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1026#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1027#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1028/* Note, below two are guess */
1029#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1030#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1031#define CLKCFG_FSB_MASK (7 << 0)
1032#define CLKCFG_MEM_533 (1 << 4)
1033#define CLKCFG_MEM_667 (2 << 4)
1034#define CLKCFG_MEM_800 (3 << 4)
1035#define CLKCFG_MEM_MASK (7 << 4)
1036
1037#define TSC1 0x11001
1038#define TSE (1<<0)
1039#define TR1 0x11006
1040#define TSFS 0x11020
1041#define TSFS_SLOPE_MASK 0x0000ff00
1042#define TSFS_SLOPE_SHIFT 8
1043#define TSFS_INTR_MASK 0x000000ff
1044
1045#define CRSTANDVID 0x11100
1046#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1047#define PXVFREQ_PX_MASK 0x7f000000
1048#define PXVFREQ_PX_SHIFT 24
1049#define VIDFREQ_BASE 0x11110
1050#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1051#define VIDFREQ2 0x11114
1052#define VIDFREQ3 0x11118
1053#define VIDFREQ4 0x1111c
1054#define VIDFREQ_P0_MASK 0x1f000000
1055#define VIDFREQ_P0_SHIFT 24
1056#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1057#define VIDFREQ_P0_CSCLK_SHIFT 20
1058#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1059#define VIDFREQ_P0_CRCLK_SHIFT 16
1060#define VIDFREQ_P1_MASK 0x00001f00
1061#define VIDFREQ_P1_SHIFT 8
1062#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1063#define VIDFREQ_P1_CSCLK_SHIFT 4
1064#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1065#define INTTOEXT_BASE_ILK 0x11300
1066#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1067#define INTTOEXT_MAP3_SHIFT 24
1068#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1069#define INTTOEXT_MAP2_SHIFT 16
1070#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1071#define INTTOEXT_MAP1_SHIFT 8
1072#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1073#define INTTOEXT_MAP0_SHIFT 0
1074#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1075#define MEMSWCTL 0x11170 /* Ironlake only */
1076#define MEMCTL_CMD_MASK 0xe000
1077#define MEMCTL_CMD_SHIFT 13
1078#define MEMCTL_CMD_RCLK_OFF 0
1079#define MEMCTL_CMD_RCLK_ON 1
1080#define MEMCTL_CMD_CHFREQ 2
1081#define MEMCTL_CMD_CHVID 3
1082#define MEMCTL_CMD_VMMOFF 4
1083#define MEMCTL_CMD_VMMON 5
1084#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1085 when command complete */
1086#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1087#define MEMCTL_FREQ_SHIFT 8
1088#define MEMCTL_SFCAVM (1<<7)
1089#define MEMCTL_TGT_VID_MASK 0x007f
1090#define MEMIHYST 0x1117c
1091#define MEMINTREN 0x11180 /* 16 bits */
1092#define MEMINT_RSEXIT_EN (1<<8)
1093#define MEMINT_CX_SUPR_EN (1<<7)
1094#define MEMINT_CONT_BUSY_EN (1<<6)
1095#define MEMINT_AVG_BUSY_EN (1<<5)
1096#define MEMINT_EVAL_CHG_EN (1<<4)
1097#define MEMINT_MON_IDLE_EN (1<<3)
1098#define MEMINT_UP_EVAL_EN (1<<2)
1099#define MEMINT_DOWN_EVAL_EN (1<<1)
1100#define MEMINT_SW_CMD_EN (1<<0)
1101#define MEMINTRSTR 0x11182 /* 16 bits */
1102#define MEM_RSEXIT_MASK 0xc000
1103#define MEM_RSEXIT_SHIFT 14
1104#define MEM_CONT_BUSY_MASK 0x3000
1105#define MEM_CONT_BUSY_SHIFT 12
1106#define MEM_AVG_BUSY_MASK 0x0c00
1107#define MEM_AVG_BUSY_SHIFT 10
1108#define MEM_EVAL_CHG_MASK 0x0300
1109#define MEM_EVAL_BUSY_SHIFT 8
1110#define MEM_MON_IDLE_MASK 0x00c0
1111#define MEM_MON_IDLE_SHIFT 6
1112#define MEM_UP_EVAL_MASK 0x0030
1113#define MEM_UP_EVAL_SHIFT 4
1114#define MEM_DOWN_EVAL_MASK 0x000c
1115#define MEM_DOWN_EVAL_SHIFT 2
1116#define MEM_SW_CMD_MASK 0x0003
1117#define MEM_INT_STEER_GFX 0
1118#define MEM_INT_STEER_CMR 1
1119#define MEM_INT_STEER_SMI 2
1120#define MEM_INT_STEER_SCI 3
1121#define MEMINTRSTS 0x11184
1122#define MEMINT_RSEXIT (1<<7)
1123#define MEMINT_CONT_BUSY (1<<6)
1124#define MEMINT_AVG_BUSY (1<<5)
1125#define MEMINT_EVAL_CHG (1<<4)
1126#define MEMINT_MON_IDLE (1<<3)
1127#define MEMINT_UP_EVAL (1<<2)
1128#define MEMINT_DOWN_EVAL (1<<1)
1129#define MEMINT_SW_CMD (1<<0)
1130#define MEMMODECTL 0x11190
1131#define MEMMODE_BOOST_EN (1<<31)
1132#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1133#define MEMMODE_BOOST_FREQ_SHIFT 24
1134#define MEMMODE_IDLE_MODE_MASK 0x00030000
1135#define MEMMODE_IDLE_MODE_SHIFT 16
1136#define MEMMODE_IDLE_MODE_EVAL 0
1137#define MEMMODE_IDLE_MODE_CONT 1
1138#define MEMMODE_HWIDLE_EN (1<<15)
1139#define MEMMODE_SWMODE_EN (1<<14)
1140#define MEMMODE_RCLK_GATE (1<<13)
1141#define MEMMODE_HW_UPDATE (1<<12)
1142#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1143#define MEMMODE_FSTART_SHIFT 8
1144#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1145#define MEMMODE_FMAX_SHIFT 4
1146#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1147#define RCBMAXAVG 0x1119c
1148#define MEMSWCTL2 0x1119e /* Cantiga only */
1149#define SWMEMCMD_RENDER_OFF (0 << 13)
1150#define SWMEMCMD_RENDER_ON (1 << 13)
1151#define SWMEMCMD_SWFREQ (2 << 13)
1152#define SWMEMCMD_TARVID (3 << 13)
1153#define SWMEMCMD_VRM_OFF (4 << 13)
1154#define SWMEMCMD_VRM_ON (5 << 13)
1155#define CMDSTS (1<<12)
1156#define SFCAVM (1<<11)
1157#define SWFREQ_MASK 0x0380 /* P0-7 */
1158#define SWFREQ_SHIFT 7
1159#define TARVID_MASK 0x001f
1160#define MEMSTAT_CTG 0x111a0
1161#define RCBMINAVG 0x111a0
1162#define RCUPEI 0x111b0
1163#define RCDNEI 0x111b4
1164#define RSTDBYCTL 0x111b8
1165#define RS1EN (1<<31)
1166#define RS2EN (1<<30)
1167#define RS3EN (1<<29)
1168#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1169#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1170#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1171#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1172#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1173#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1174#define RSX_STATUS_MASK (7<<20)
1175#define RSX_STATUS_ON (0<<20)
1176#define RSX_STATUS_RC1 (1<<20)
1177#define RSX_STATUS_RC1E (2<<20)
1178#define RSX_STATUS_RS1 (3<<20)
1179#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1180#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1181#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1182#define RSX_STATUS_RSVD2 (7<<20)
1183#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1184#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1185#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1186#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1187#define RS1CONTSAV_MASK (3<<14)
1188#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1189#define RS1CONTSAV_RSVD (1<<14)
1190#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1191#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1192#define NORMSLEXLAT_MASK (3<<12)
1193#define SLOW_RS123 (0<<12)
1194#define SLOW_RS23 (1<<12)
1195#define SLOW_RS3 (2<<12)
1196#define NORMAL_RS123 (3<<12)
1197#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1198#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1199#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1200#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1201#define RS_CSTATE_MASK (3<<4)
1202#define RS_CSTATE_C367_RS1 (0<<4)
1203#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1204#define RS_CSTATE_RSVD (2<<4)
1205#define RS_CSTATE_C367_RS2 (3<<4)
1206#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1207#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1208#define VIDCTL 0x111c0
1209#define VIDSTS 0x111c8
1210#define VIDSTART 0x111cc /* 8 bits */
1211#define MEMSTAT_ILK 0x111f8
1212#define MEMSTAT_VID_MASK 0x7f00
1213#define MEMSTAT_VID_SHIFT 8
1214#define MEMSTAT_PSTATE_MASK 0x00f8
1215#define MEMSTAT_PSTATE_SHIFT 3
1216#define MEMSTAT_MON_ACTV (1<<2)
1217#define MEMSTAT_SRC_CTL_MASK 0x0003
1218#define MEMSTAT_SRC_CTL_CORE 0
1219#define MEMSTAT_SRC_CTL_TRB 1
1220#define MEMSTAT_SRC_CTL_THM 2
1221#define MEMSTAT_SRC_CTL_STDBY 3
1222#define RCPREVBSYTUPAVG 0x113b8
1223#define RCPREVBSYTDNAVG 0x113bc
1224#define PMMISC 0x11214
1225#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1226#define SDEW 0x1124c
1227#define CSIEW0 0x11250
1228#define CSIEW1 0x11254
1229#define CSIEW2 0x11258
1230#define PEW 0x1125c
1231#define DEW 0x11270
1232#define MCHAFE 0x112c0
1233#define CSIEC 0x112e0
1234#define DMIEC 0x112e4
1235#define DDREC 0x112e8
1236#define PEG0EC 0x112ec
1237#define PEG1EC 0x112f0
1238#define GFXEC 0x112f4
1239#define RPPREVBSYTUPAVG 0x113b8
1240#define RPPREVBSYTDNAVG 0x113bc
1241#define ECR 0x11600
1242#define ECR_GPFE (1<<31)
1243#define ECR_IMONE (1<<30)
1244#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1245#define OGW0 0x11608
1246#define OGW1 0x1160c
1247#define EG0 0x11610
1248#define EG1 0x11614
1249#define EG2 0x11618
1250#define EG3 0x1161c
1251#define EG4 0x11620
1252#define EG5 0x11624
1253#define EG6 0x11628
1254#define EG7 0x1162c
1255#define PXW 0x11664
1256#define PXWL 0x11680
1257#define LCFUSE02 0x116c0
1258#define LCFUSE_HIV_MASK 0x000000ff
1259#define CSIPLL0 0x12c10
1260#define DDRMPLL1 0X12c20
1261#define PEG_BAND_GAP_DATA 0x14d68
1262
1263#define GEN6_GT_PERF_STATUS 0x145948
1264#define GEN6_RP_STATE_LIMITS 0x145994
1265#define GEN6_RP_STATE_CAP 0x145998
1266
1267/*
1268 * Logical Context regs
1269 */
1270#define CCID 0x2180
1271#define CCID_EN (1<<0)
1272/*
1273 * Overlay regs
1274 */
1275
1276#define OVADD 0x30000
1277#define DOVSTA 0x30008
1278#define OC_BUF (0x3<<20)
1279#define OGAMC5 0x30010
1280#define OGAMC4 0x30014
1281#define OGAMC3 0x30018
1282#define OGAMC2 0x3001c
1283#define OGAMC1 0x30020
1284#define OGAMC0 0x30024
1285
1286/*
1287 * Display engine regs
1288 */
1289
1290/* Pipe A timing regs */
1291#define _HTOTAL_A 0x60000
1292#define _HBLANK_A 0x60004
1293#define _HSYNC_A 0x60008
1294#define _VTOTAL_A 0x6000c
1295#define _VBLANK_A 0x60010
1296#define _VSYNC_A 0x60014
1297#define _PIPEASRC 0x6001c
1298#define _BCLRPAT_A 0x60020
1299
1300/* Pipe B timing regs */
1301#define _HTOTAL_B 0x61000
1302#define _HBLANK_B 0x61004
1303#define _HSYNC_B 0x61008
1304#define _VTOTAL_B 0x6100c
1305#define _VBLANK_B 0x61010
1306#define _VSYNC_B 0x61014
1307#define _PIPEBSRC 0x6101c
1308#define _BCLRPAT_B 0x61020
1309
1310#define HTOTAL(pipe) _PIPE(pipe, _HTOTAL_A, _HTOTAL_B)
1311#define HBLANK(pipe) _PIPE(pipe, _HBLANK_A, _HBLANK_B)
1312#define HSYNC(pipe) _PIPE(pipe, _HSYNC_A, _HSYNC_B)
1313#define VTOTAL(pipe) _PIPE(pipe, _VTOTAL_A, _VTOTAL_B)
1314#define VBLANK(pipe) _PIPE(pipe, _VBLANK_A, _VBLANK_B)
1315#define VSYNC(pipe) _PIPE(pipe, _VSYNC_A, _VSYNC_B)
1316#define BCLRPAT(pipe) _PIPE(pipe, _BCLRPAT_A, _BCLRPAT_B)
1317
1318/* VGA port control */
1319#define ADPA 0x61100
1320#define ADPA_DAC_ENABLE (1<<31)
1321#define ADPA_DAC_DISABLE 0
1322#define ADPA_PIPE_SELECT_MASK (1<<30)
1323#define ADPA_PIPE_A_SELECT 0
1324#define ADPA_PIPE_B_SELECT (1<<30)
1325#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
1326#define ADPA_USE_VGA_HVPOLARITY (1<<15)
1327#define ADPA_SETS_HVPOLARITY 0
1328#define ADPA_VSYNC_CNTL_DISABLE (1<<11)
1329#define ADPA_VSYNC_CNTL_ENABLE 0
1330#define ADPA_HSYNC_CNTL_DISABLE (1<<10)
1331#define ADPA_HSYNC_CNTL_ENABLE 0
1332#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
1333#define ADPA_VSYNC_ACTIVE_LOW 0
1334#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
1335#define ADPA_HSYNC_ACTIVE_LOW 0
1336#define ADPA_DPMS_MASK (~(3<<10))
1337#define ADPA_DPMS_ON (0<<10)
1338#define ADPA_DPMS_SUSPEND (1<<10)
1339#define ADPA_DPMS_STANDBY (2<<10)
1340#define ADPA_DPMS_OFF (3<<10)
1341
1342
1343/* Hotplug control (945+ only) */
1344#define PORT_HOTPLUG_EN 0x61110
1345#define HDMIB_HOTPLUG_INT_EN (1 << 29)
1346#define DPB_HOTPLUG_INT_EN (1 << 29)
1347#define HDMIC_HOTPLUG_INT_EN (1 << 28)
1348#define DPC_HOTPLUG_INT_EN (1 << 28)
1349#define HDMID_HOTPLUG_INT_EN (1 << 27)
1350#define DPD_HOTPLUG_INT_EN (1 << 27)
1351#define SDVOB_HOTPLUG_INT_EN (1 << 26)
1352#define SDVOC_HOTPLUG_INT_EN (1 << 25)
1353#define TV_HOTPLUG_INT_EN (1 << 18)
1354#define CRT_HOTPLUG_INT_EN (1 << 9)
1355#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
1356#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
1357/* must use period 64 on GM45 according to docs */
1358#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
1359#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
1360#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
1361#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
1362#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
1363#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
1364#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
1365#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
1366#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
1367#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
1368#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
1369#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
1370
1371#define PORT_HOTPLUG_STAT 0x61114
1372#define HDMIB_HOTPLUG_INT_STATUS (1 << 29)
1373#define DPB_HOTPLUG_INT_STATUS (1 << 29)
1374#define HDMIC_HOTPLUG_INT_STATUS (1 << 28)
1375#define DPC_HOTPLUG_INT_STATUS (1 << 28)
1376#define HDMID_HOTPLUG_INT_STATUS (1 << 27)
1377#define DPD_HOTPLUG_INT_STATUS (1 << 27)
1378#define CRT_HOTPLUG_INT_STATUS (1 << 11)
1379#define TV_HOTPLUG_INT_STATUS (1 << 10)
1380#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
1381#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
1382#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
1383#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
1384#define SDVOC_HOTPLUG_INT_STATUS (1 << 7)
1385#define SDVOB_HOTPLUG_INT_STATUS (1 << 6)
1386
1387/* SDVO port control */
1388#define SDVOB 0x61140
1389#define SDVOC 0x61160
1390#define SDVO_ENABLE (1 << 31)
1391#define SDVO_PIPE_B_SELECT (1 << 30)
1392#define SDVO_STALL_SELECT (1 << 29)
1393#define SDVO_INTERRUPT_ENABLE (1 << 26)
1394/**
1395 * 915G/GM SDVO pixel multiplier.
1396 *
1397 * Programmed value is multiplier - 1, up to 5x.
1398 *
1399 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
1400 */
1401#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
1402#define SDVO_PORT_MULTIPLY_SHIFT 23
1403#define SDVO_PHASE_SELECT_MASK (15 << 19)
1404#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
1405#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
1406#define SDVOC_GANG_MODE (1 << 16)
1407#define SDVO_ENCODING_SDVO (0x0 << 10)
1408#define SDVO_ENCODING_HDMI (0x2 << 10)
1409/** Requird for HDMI operation */
1410#define SDVO_NULL_PACKETS_DURING_VSYNC (1 << 9)
1411#define SDVO_COLOR_RANGE_16_235 (1 << 8)
1412#define SDVO_BORDER_ENABLE (1 << 7)
1413#define SDVO_AUDIO_ENABLE (1 << 6)
1414/** New with 965, default is to be set */
1415#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
1416/** New with 965, default is to be set */
1417#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
1418#define SDVOB_PCIE_CONCURRENCY (1 << 3)
1419#define SDVO_DETECTED (1 << 2)
1420/* Bits to be preserved when writing */
1421#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | (1 << 26))
1422#define SDVOC_PRESERVE_MASK ((1 << 17) | (1 << 26))
1423
1424/* DVO port control */
1425#define DVOA 0x61120
1426#define DVOB 0x61140
1427#define DVOC 0x61160
1428#define DVO_ENABLE (1 << 31)
1429#define DVO_PIPE_B_SELECT (1 << 30)
1430#define DVO_PIPE_STALL_UNUSED (0 << 28)
1431#define DVO_PIPE_STALL (1 << 28)
1432#define DVO_PIPE_STALL_TV (2 << 28)
1433#define DVO_PIPE_STALL_MASK (3 << 28)
1434#define DVO_USE_VGA_SYNC (1 << 15)
1435#define DVO_DATA_ORDER_I740 (0 << 14)
1436#define DVO_DATA_ORDER_FP (1 << 14)
1437#define DVO_VSYNC_DISABLE (1 << 11)
1438#define DVO_HSYNC_DISABLE (1 << 10)
1439#define DVO_VSYNC_TRISTATE (1 << 9)
1440#define DVO_HSYNC_TRISTATE (1 << 8)
1441#define DVO_BORDER_ENABLE (1 << 7)
1442#define DVO_DATA_ORDER_GBRG (1 << 6)
1443#define DVO_DATA_ORDER_RGGB (0 << 6)
1444#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
1445#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
1446#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
1447#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
1448#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
1449#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
1450#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
1451#define DVO_PRESERVE_MASK (0x7<<24)
1452#define DVOA_SRCDIM 0x61124
1453#define DVOB_SRCDIM 0x61144
1454#define DVOC_SRCDIM 0x61164
1455#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
1456#define DVO_SRCDIM_VERTICAL_SHIFT 0
1457
1458/* LVDS port control */
1459#define LVDS 0x61180
1460/*
1461 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
1462 * the DPLL semantics change when the LVDS is assigned to that pipe.
1463 */
1464#define LVDS_PORT_EN (1 << 31)
1465/* Selects pipe B for LVDS data. Must be set on pre-965. */
1466#define LVDS_PIPEB_SELECT (1 << 30)
1467#define LVDS_PIPE_MASK (1 << 30)
1468#define LVDS_PIPE(pipe) ((pipe) << 30)
1469/* LVDS dithering flag on 965/g4x platform */
1470#define LVDS_ENABLE_DITHER (1 << 25)
1471/* LVDS sync polarity flags. Set to invert (i.e. negative) */
1472#define LVDS_VSYNC_POLARITY (1 << 21)
1473#define LVDS_HSYNC_POLARITY (1 << 20)
1474
1475/* Enable border for unscaled (or aspect-scaled) display */
1476#define LVDS_BORDER_ENABLE (1 << 15)
1477/*
1478 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
1479 * pixel.
1480 */
1481#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
1482#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
1483#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
1484/*
1485 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
1486 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
1487 * on.
1488 */
1489#define LVDS_A3_POWER_MASK (3 << 6)
1490#define LVDS_A3_POWER_DOWN (0 << 6)
1491#define LVDS_A3_POWER_UP (3 << 6)
1492/*
1493 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
1494 * is set.
1495 */
1496#define LVDS_CLKB_POWER_MASK (3 << 4)
1497#define LVDS_CLKB_POWER_DOWN (0 << 4)
1498#define LVDS_CLKB_POWER_UP (3 << 4)
1499/*
1500 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
1501 * setting for whether we are in dual-channel mode. The B3 pair will
1502 * additionally only be powered up when LVDS_A3_POWER_UP is set.
1503 */
1504#define LVDS_B0B3_POWER_MASK (3 << 2)
1505#define LVDS_B0B3_POWER_DOWN (0 << 2)
1506#define LVDS_B0B3_POWER_UP (3 << 2)
1507
1508/* Video Data Island Packet control */
1509#define VIDEO_DIP_DATA 0x61178
1510#define VIDEO_DIP_CTL 0x61170
1511#define VIDEO_DIP_ENABLE (1 << 31)
1512#define VIDEO_DIP_PORT_B (1 << 29)
1513#define VIDEO_DIP_PORT_C (2 << 29)
1514#define VIDEO_DIP_ENABLE_AVI (1 << 21)
1515#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
1516#define VIDEO_DIP_ENABLE_SPD (8 << 21)
1517#define VIDEO_DIP_SELECT_AVI (0 << 19)
1518#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
1519#define VIDEO_DIP_SELECT_SPD (3 << 19)
1520#define VIDEO_DIP_SELECT_MASK (3 << 19)
1521#define VIDEO_DIP_FREQ_ONCE (0 << 16)
1522#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
1523#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
1524
1525/* Panel power sequencing */
1526#define PP_STATUS 0x61200
1527#define PP_ON (1 << 31)
1528/*
1529 * Indicates that all dependencies of the panel are on:
1530 *
1531 * - PLL enabled
1532 * - pipe enabled
1533 * - LVDS/DVOB/DVOC on
1534 */
1535#define PP_READY (1 << 30)
1536#define PP_SEQUENCE_NONE (0 << 28)
1537#define PP_SEQUENCE_ON (1 << 28)
1538#define PP_SEQUENCE_OFF (2 << 28)
1539#define PP_SEQUENCE_MASK 0x30000000
1540#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
1541#define PP_SEQUENCE_STATE_ON_IDLE (1 << 3)
1542#define PP_SEQUENCE_STATE_MASK 0x0000000f
1543#define PP_CONTROL 0x61204
1544#define POWER_TARGET_ON (1 << 0)
1545#define PP_ON_DELAYS 0x61208
1546#define PP_OFF_DELAYS 0x6120c
1547#define PP_DIVISOR 0x61210
1548
1549/* Panel fitting */
1550#define PFIT_CONTROL 0x61230
1551#define PFIT_ENABLE (1 << 31)
1552#define PFIT_PIPE_MASK (3 << 29)
1553#define PFIT_PIPE_SHIFT 29
1554#define VERT_INTERP_DISABLE (0 << 10)
1555#define VERT_INTERP_BILINEAR (1 << 10)
1556#define VERT_INTERP_MASK (3 << 10)
1557#define VERT_AUTO_SCALE (1 << 9)
1558#define HORIZ_INTERP_DISABLE (0 << 6)
1559#define HORIZ_INTERP_BILINEAR (1 << 6)
1560#define HORIZ_INTERP_MASK (3 << 6)
1561#define HORIZ_AUTO_SCALE (1 << 5)
1562#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
1563#define PFIT_FILTER_FUZZY (0 << 24)
1564#define PFIT_SCALING_AUTO (0 << 26)
1565#define PFIT_SCALING_PROGRAMMED (1 << 26)
1566#define PFIT_SCALING_PILLAR (2 << 26)
1567#define PFIT_SCALING_LETTER (3 << 26)
1568#define PFIT_PGM_RATIOS 0x61234
1569#define PFIT_VERT_SCALE_MASK 0xfff00000
1570#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1571/* Pre-965 */
1572#define PFIT_VERT_SCALE_SHIFT 20
1573#define PFIT_VERT_SCALE_MASK 0xfff00000
1574#define PFIT_HORIZ_SCALE_SHIFT 4
1575#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
1576/* 965+ */
1577#define PFIT_VERT_SCALE_SHIFT_965 16
1578#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
1579#define PFIT_HORIZ_SCALE_SHIFT_965 0
1580#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
1581
1582#define PFIT_AUTO_RATIOS 0x61238
1583
1584/* Backlight control */
1585#define BLC_PWM_CTL 0x61254
1586#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
1587#define BLC_PWM_CTL2 0x61250 /* 965+ only */
1588#define BLM_COMBINATION_MODE (1 << 30)
1589/*
1590 * This is the most significant 15 bits of the number of backlight cycles in a
1591 * complete cycle of the modulated backlight control.
1592 *
1593 * The actual value is this field multiplied by two.
1594 */
1595#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
1596#define BLM_LEGACY_MODE (1 << 16)
1597/*
1598 * This is the number of cycles out of the backlight modulation cycle for which
1599 * the backlight is on.
1600 *
1601 * This field must be no greater than the number of cycles in the complete
1602 * backlight modulation cycle.
1603 */
1604#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
1605#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
1606
1607#define BLC_HIST_CTL 0x61260
1608
1609/* TV port control */
1610#define TV_CTL 0x68000
1611/** Enables the TV encoder */
1612# define TV_ENC_ENABLE (1 << 31)
1613/** Sources the TV encoder input from pipe B instead of A. */
1614# define TV_ENC_PIPEB_SELECT (1 << 30)
1615/** Outputs composite video (DAC A only) */
1616# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
1617/** Outputs SVideo video (DAC B/C) */
1618# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
1619/** Outputs Component video (DAC A/B/C) */
1620# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
1621/** Outputs Composite and SVideo (DAC A/B/C) */
1622# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
1623# define TV_TRILEVEL_SYNC (1 << 21)
1624/** Enables slow sync generation (945GM only) */
1625# define TV_SLOW_SYNC (1 << 20)
1626/** Selects 4x oversampling for 480i and 576p */
1627# define TV_OVERSAMPLE_4X (0 << 18)
1628/** Selects 2x oversampling for 720p and 1080i */
1629# define TV_OVERSAMPLE_2X (1 << 18)
1630/** Selects no oversampling for 1080p */
1631# define TV_OVERSAMPLE_NONE (2 << 18)
1632/** Selects 8x oversampling */
1633# define TV_OVERSAMPLE_8X (3 << 18)
1634/** Selects progressive mode rather than interlaced */
1635# define TV_PROGRESSIVE (1 << 17)
1636/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
1637# define TV_PAL_BURST (1 << 16)
1638/** Field for setting delay of Y compared to C */
1639# define TV_YC_SKEW_MASK (7 << 12)
1640/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
1641# define TV_ENC_SDP_FIX (1 << 11)
1642/**
1643 * Enables a fix for the 915GM only.
1644 *
1645 * Not sure what it does.
1646 */
1647# define TV_ENC_C0_FIX (1 << 10)
1648/** Bits that must be preserved by software */
1649# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
1650# define TV_FUSE_STATE_MASK (3 << 4)
1651/** Read-only state that reports all features enabled */
1652# define TV_FUSE_STATE_ENABLED (0 << 4)
1653/** Read-only state that reports that Macrovision is disabled in hardware*/
1654# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
1655/** Read-only state that reports that TV-out is disabled in hardware. */
1656# define TV_FUSE_STATE_DISABLED (2 << 4)
1657/** Normal operation */
1658# define TV_TEST_MODE_NORMAL (0 << 0)
1659/** Encoder test pattern 1 - combo pattern */
1660# define TV_TEST_MODE_PATTERN_1 (1 << 0)
1661/** Encoder test pattern 2 - full screen vertical 75% color bars */
1662# define TV_TEST_MODE_PATTERN_2 (2 << 0)
1663/** Encoder test pattern 3 - full screen horizontal 75% color bars */
1664# define TV_TEST_MODE_PATTERN_3 (3 << 0)
1665/** Encoder test pattern 4 - random noise */
1666# define TV_TEST_MODE_PATTERN_4 (4 << 0)
1667/** Encoder test pattern 5 - linear color ramps */
1668# define TV_TEST_MODE_PATTERN_5 (5 << 0)
1669/**
1670 * This test mode forces the DACs to 50% of full output.
1671 *
1672 * This is used for load detection in combination with TVDAC_SENSE_MASK
1673 */
1674# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
1675# define TV_TEST_MODE_MASK (7 << 0)
1676
1677#define TV_DAC 0x68004
1678# define TV_DAC_SAVE 0x00ffff00
1679/**
1680 * Reports that DAC state change logic has reported change (RO).
1681 *
1682 * This gets cleared when TV_DAC_STATE_EN is cleared
1683*/
1684# define TVDAC_STATE_CHG (1 << 31)
1685# define TVDAC_SENSE_MASK (7 << 28)
1686/** Reports that DAC A voltage is above the detect threshold */
1687# define TVDAC_A_SENSE (1 << 30)
1688/** Reports that DAC B voltage is above the detect threshold */
1689# define TVDAC_B_SENSE (1 << 29)
1690/** Reports that DAC C voltage is above the detect threshold */
1691# define TVDAC_C_SENSE (1 << 28)
1692/**
1693 * Enables DAC state detection logic, for load-based TV detection.
1694 *
1695 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
1696 * to off, for load detection to work.
1697 */
1698# define TVDAC_STATE_CHG_EN (1 << 27)
1699/** Sets the DAC A sense value to high */
1700# define TVDAC_A_SENSE_CTL (1 << 26)
1701/** Sets the DAC B sense value to high */
1702# define TVDAC_B_SENSE_CTL (1 << 25)
1703/** Sets the DAC C sense value to high */
1704# define TVDAC_C_SENSE_CTL (1 << 24)
1705/** Overrides the ENC_ENABLE and DAC voltage levels */
1706# define DAC_CTL_OVERRIDE (1 << 7)
1707/** Sets the slew rate. Must be preserved in software */
1708# define ENC_TVDAC_SLEW_FAST (1 << 6)
1709# define DAC_A_1_3_V (0 << 4)
1710# define DAC_A_1_1_V (1 << 4)
1711# define DAC_A_0_7_V (2 << 4)
1712# define DAC_A_MASK (3 << 4)
1713# define DAC_B_1_3_V (0 << 2)
1714# define DAC_B_1_1_V (1 << 2)
1715# define DAC_B_0_7_V (2 << 2)
1716# define DAC_B_MASK (3 << 2)
1717# define DAC_C_1_3_V (0 << 0)
1718# define DAC_C_1_1_V (1 << 0)
1719# define DAC_C_0_7_V (2 << 0)
1720# define DAC_C_MASK (3 << 0)
1721
1722/**
1723 * CSC coefficients are stored in a floating point format with 9 bits of
1724 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
1725 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
1726 * -1 (0x3) being the only legal negative value.
1727 */
1728#define TV_CSC_Y 0x68010
1729# define TV_RY_MASK 0x07ff0000
1730# define TV_RY_SHIFT 16
1731# define TV_GY_MASK 0x00000fff
1732# define TV_GY_SHIFT 0
1733
1734#define TV_CSC_Y2 0x68014
1735# define TV_BY_MASK 0x07ff0000
1736# define TV_BY_SHIFT 16
1737/**
1738 * Y attenuation for component video.
1739 *
1740 * Stored in 1.9 fixed point.
1741 */
1742# define TV_AY_MASK 0x000003ff
1743# define TV_AY_SHIFT 0
1744
1745#define TV_CSC_U 0x68018
1746# define TV_RU_MASK 0x07ff0000
1747# define TV_RU_SHIFT 16
1748# define TV_GU_MASK 0x000007ff
1749# define TV_GU_SHIFT 0
1750
1751#define TV_CSC_U2 0x6801c
1752# define TV_BU_MASK 0x07ff0000
1753# define TV_BU_SHIFT 16
1754/**
1755 * U attenuation for component video.
1756 *
1757 * Stored in 1.9 fixed point.
1758 */
1759# define TV_AU_MASK 0x000003ff
1760# define TV_AU_SHIFT 0
1761
1762#define TV_CSC_V 0x68020
1763# define TV_RV_MASK 0x0fff0000
1764# define TV_RV_SHIFT 16
1765# define TV_GV_MASK 0x000007ff
1766# define TV_GV_SHIFT 0
1767
1768#define TV_CSC_V2 0x68024
1769# define TV_BV_MASK 0x07ff0000
1770# define TV_BV_SHIFT 16
1771/**
1772 * V attenuation for component video.
1773 *
1774 * Stored in 1.9 fixed point.
1775 */
1776# define TV_AV_MASK 0x000007ff
1777# define TV_AV_SHIFT 0
1778
1779#define TV_CLR_KNOBS 0x68028
1780/** 2s-complement brightness adjustment */
1781# define TV_BRIGHTNESS_MASK 0xff000000
1782# define TV_BRIGHTNESS_SHIFT 24
1783/** Contrast adjustment, as a 2.6 unsigned floating point number */
1784# define TV_CONTRAST_MASK 0x00ff0000
1785# define TV_CONTRAST_SHIFT 16
1786/** Saturation adjustment, as a 2.6 unsigned floating point number */
1787# define TV_SATURATION_MASK 0x0000ff00
1788# define TV_SATURATION_SHIFT 8
1789/** Hue adjustment, as an integer phase angle in degrees */
1790# define TV_HUE_MASK 0x000000ff
1791# define TV_HUE_SHIFT 0
1792
1793#define TV_CLR_LEVEL 0x6802c
1794/** Controls the DAC level for black */
1795# define TV_BLACK_LEVEL_MASK 0x01ff0000
1796# define TV_BLACK_LEVEL_SHIFT 16
1797/** Controls the DAC level for blanking */
1798# define TV_BLANK_LEVEL_MASK 0x000001ff
1799# define TV_BLANK_LEVEL_SHIFT 0
1800
1801#define TV_H_CTL_1 0x68030
1802/** Number of pixels in the hsync. */
1803# define TV_HSYNC_END_MASK 0x1fff0000
1804# define TV_HSYNC_END_SHIFT 16
1805/** Total number of pixels minus one in the line (display and blanking). */
1806# define TV_HTOTAL_MASK 0x00001fff
1807# define TV_HTOTAL_SHIFT 0
1808
1809#define TV_H_CTL_2 0x68034
1810/** Enables the colorburst (needed for non-component color) */
1811# define TV_BURST_ENA (1 << 31)
1812/** Offset of the colorburst from the start of hsync, in pixels minus one. */
1813# define TV_HBURST_START_SHIFT 16
1814# define TV_HBURST_START_MASK 0x1fff0000
1815/** Length of the colorburst */
1816# define TV_HBURST_LEN_SHIFT 0
1817# define TV_HBURST_LEN_MASK 0x0001fff
1818
1819#define TV_H_CTL_3 0x68038
1820/** End of hblank, measured in pixels minus one from start of hsync */
1821# define TV_HBLANK_END_SHIFT 16
1822# define TV_HBLANK_END_MASK 0x1fff0000
1823/** Start of hblank, measured in pixels minus one from start of hsync */
1824# define TV_HBLANK_START_SHIFT 0
1825# define TV_HBLANK_START_MASK 0x0001fff
1826
1827#define TV_V_CTL_1 0x6803c
1828/** XXX */
1829# define TV_NBR_END_SHIFT 16
1830# define TV_NBR_END_MASK 0x07ff0000
1831/** XXX */
1832# define TV_VI_END_F1_SHIFT 8
1833# define TV_VI_END_F1_MASK 0x00003f00
1834/** XXX */
1835# define TV_VI_END_F2_SHIFT 0
1836# define TV_VI_END_F2_MASK 0x0000003f
1837
1838#define TV_V_CTL_2 0x68040
1839/** Length of vsync, in half lines */
1840# define TV_VSYNC_LEN_MASK 0x07ff0000
1841# define TV_VSYNC_LEN_SHIFT 16
1842/** Offset of the start of vsync in field 1, measured in one less than the
1843 * number of half lines.
1844 */
1845# define TV_VSYNC_START_F1_MASK 0x00007f00
1846# define TV_VSYNC_START_F1_SHIFT 8
1847/**
1848 * Offset of the start of vsync in field 2, measured in one less than the
1849 * number of half lines.
1850 */
1851# define TV_VSYNC_START_F2_MASK 0x0000007f
1852# define TV_VSYNC_START_F2_SHIFT 0
1853
1854#define TV_V_CTL_3 0x68044
1855/** Enables generation of the equalization signal */
1856# define TV_EQUAL_ENA (1 << 31)
1857/** Length of vsync, in half lines */
1858# define TV_VEQ_LEN_MASK 0x007f0000
1859# define TV_VEQ_LEN_SHIFT 16
1860/** Offset of the start of equalization in field 1, measured in one less than
1861 * the number of half lines.
1862 */
1863# define TV_VEQ_START_F1_MASK 0x0007f00
1864# define TV_VEQ_START_F1_SHIFT 8
1865/**
1866 * Offset of the start of equalization in field 2, measured in one less than
1867 * the number of half lines.
1868 */
1869# define TV_VEQ_START_F2_MASK 0x000007f
1870# define TV_VEQ_START_F2_SHIFT 0
1871
1872#define TV_V_CTL_4 0x68048
1873/**
1874 * Offset to start of vertical colorburst, measured in one less than the
1875 * number of lines from vertical start.
1876 */
1877# define TV_VBURST_START_F1_MASK 0x003f0000
1878# define TV_VBURST_START_F1_SHIFT 16
1879/**
1880 * Offset to the end of vertical colorburst, measured in one less than the
1881 * number of lines from the start of NBR.
1882 */
1883# define TV_VBURST_END_F1_MASK 0x000000ff
1884# define TV_VBURST_END_F1_SHIFT 0
1885
1886#define TV_V_CTL_5 0x6804c
1887/**
1888 * Offset to start of vertical colorburst, measured in one less than the
1889 * number of lines from vertical start.
1890 */
1891# define TV_VBURST_START_F2_MASK 0x003f0000
1892# define TV_VBURST_START_F2_SHIFT 16
1893/**
1894 * Offset to the end of vertical colorburst, measured in one less than the
1895 * number of lines from the start of NBR.
1896 */
1897# define TV_VBURST_END_F2_MASK 0x000000ff
1898# define TV_VBURST_END_F2_SHIFT 0
1899
1900#define TV_V_CTL_6 0x68050
1901/**
1902 * Offset to start of vertical colorburst, measured in one less than the
1903 * number of lines from vertical start.
1904 */
1905# define TV_VBURST_START_F3_MASK 0x003f0000
1906# define TV_VBURST_START_F3_SHIFT 16
1907/**
1908 * Offset to the end of vertical colorburst, measured in one less than the
1909 * number of lines from the start of NBR.
1910 */
1911# define TV_VBURST_END_F3_MASK 0x000000ff
1912# define TV_VBURST_END_F3_SHIFT 0
1913
1914#define TV_V_CTL_7 0x68054
1915/**
1916 * Offset to start of vertical colorburst, measured in one less than the
1917 * number of lines from vertical start.
1918 */
1919# define TV_VBURST_START_F4_MASK 0x003f0000
1920# define TV_VBURST_START_F4_SHIFT 16
1921/**
1922 * Offset to the end of vertical colorburst, measured in one less than the
1923 * number of lines from the start of NBR.
1924 */
1925# define TV_VBURST_END_F4_MASK 0x000000ff
1926# define TV_VBURST_END_F4_SHIFT 0
1927
1928#define TV_SC_CTL_1 0x68060
1929/** Turns on the first subcarrier phase generation DDA */
1930# define TV_SC_DDA1_EN (1 << 31)
1931/** Turns on the first subcarrier phase generation DDA */
1932# define TV_SC_DDA2_EN (1 << 30)
1933/** Turns on the first subcarrier phase generation DDA */
1934# define TV_SC_DDA3_EN (1 << 29)
1935/** Sets the subcarrier DDA to reset frequency every other field */
1936# define TV_SC_RESET_EVERY_2 (0 << 24)
1937/** Sets the subcarrier DDA to reset frequency every fourth field */
1938# define TV_SC_RESET_EVERY_4 (1 << 24)
1939/** Sets the subcarrier DDA to reset frequency every eighth field */
1940# define TV_SC_RESET_EVERY_8 (2 << 24)
1941/** Sets the subcarrier DDA to never reset the frequency */
1942# define TV_SC_RESET_NEVER (3 << 24)
1943/** Sets the peak amplitude of the colorburst.*/
1944# define TV_BURST_LEVEL_MASK 0x00ff0000
1945# define TV_BURST_LEVEL_SHIFT 16
1946/** Sets the increment of the first subcarrier phase generation DDA */
1947# define TV_SCDDA1_INC_MASK 0x00000fff
1948# define TV_SCDDA1_INC_SHIFT 0
1949
1950#define TV_SC_CTL_2 0x68064
1951/** Sets the rollover for the second subcarrier phase generation DDA */
1952# define TV_SCDDA2_SIZE_MASK 0x7fff0000
1953# define TV_SCDDA2_SIZE_SHIFT 16
1954/** Sets the increent of the second subcarrier phase generation DDA */
1955# define TV_SCDDA2_INC_MASK 0x00007fff
1956# define TV_SCDDA2_INC_SHIFT 0
1957
1958#define TV_SC_CTL_3 0x68068
1959/** Sets the rollover for the third subcarrier phase generation DDA */
1960# define TV_SCDDA3_SIZE_MASK 0x7fff0000
1961# define TV_SCDDA3_SIZE_SHIFT 16
1962/** Sets the increent of the third subcarrier phase generation DDA */
1963# define TV_SCDDA3_INC_MASK 0x00007fff
1964# define TV_SCDDA3_INC_SHIFT 0
1965
1966#define TV_WIN_POS 0x68070
1967/** X coordinate of the display from the start of horizontal active */
1968# define TV_XPOS_MASK 0x1fff0000
1969# define TV_XPOS_SHIFT 16
1970/** Y coordinate of the display from the start of vertical active (NBR) */
1971# define TV_YPOS_MASK 0x00000fff
1972# define TV_YPOS_SHIFT 0
1973
1974#define TV_WIN_SIZE 0x68074
1975/** Horizontal size of the display window, measured in pixels*/
1976# define TV_XSIZE_MASK 0x1fff0000
1977# define TV_XSIZE_SHIFT 16
1978/**
1979 * Vertical size of the display window, measured in pixels.
1980 *
1981 * Must be even for interlaced modes.
1982 */
1983# define TV_YSIZE_MASK 0x00000fff
1984# define TV_YSIZE_SHIFT 0
1985
1986#define TV_FILTER_CTL_1 0x68080
1987/**
1988 * Enables automatic scaling calculation.
1989 *
1990 * If set, the rest of the registers are ignored, and the calculated values can
1991 * be read back from the register.
1992 */
1993# define TV_AUTO_SCALE (1 << 31)
1994/**
1995 * Disables the vertical filter.
1996 *
1997 * This is required on modes more than 1024 pixels wide */
1998# define TV_V_FILTER_BYPASS (1 << 29)
1999/** Enables adaptive vertical filtering */
2000# define TV_VADAPT (1 << 28)
2001# define TV_VADAPT_MODE_MASK (3 << 26)
2002/** Selects the least adaptive vertical filtering mode */
2003# define TV_VADAPT_MODE_LEAST (0 << 26)
2004/** Selects the moderately adaptive vertical filtering mode */
2005# define TV_VADAPT_MODE_MODERATE (1 << 26)
2006/** Selects the most adaptive vertical filtering mode */
2007# define TV_VADAPT_MODE_MOST (3 << 26)
2008/**
2009 * Sets the horizontal scaling factor.
2010 *
2011 * This should be the fractional part of the horizontal scaling factor divided
2012 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2013 *
2014 * (src width - 1) / ((oversample * dest width) - 1)
2015 */
2016# define TV_HSCALE_FRAC_MASK 0x00003fff
2017# define TV_HSCALE_FRAC_SHIFT 0
2018
2019#define TV_FILTER_CTL_2 0x68084
2020/**
2021 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2022 *
2023 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2024 */
2025# define TV_VSCALE_INT_MASK 0x00038000
2026# define TV_VSCALE_INT_SHIFT 15
2027/**
2028 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2029 *
2030 * \sa TV_VSCALE_INT_MASK
2031 */
2032# define TV_VSCALE_FRAC_MASK 0x00007fff
2033# define TV_VSCALE_FRAC_SHIFT 0
2034
2035#define TV_FILTER_CTL_3 0x68088
2036/**
2037 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2038 *
2039 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2040 *
2041 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2042 */
2043# define TV_VSCALE_IP_INT_MASK 0x00038000
2044# define TV_VSCALE_IP_INT_SHIFT 15
2045/**
2046 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2047 *
2048 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2049 *
2050 * \sa TV_VSCALE_IP_INT_MASK
2051 */
2052# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
2053# define TV_VSCALE_IP_FRAC_SHIFT 0
2054
2055#define TV_CC_CONTROL 0x68090
2056# define TV_CC_ENABLE (1 << 31)
2057/**
2058 * Specifies which field to send the CC data in.
2059 *
2060 * CC data is usually sent in field 0.
2061 */
2062# define TV_CC_FID_MASK (1 << 27)
2063# define TV_CC_FID_SHIFT 27
2064/** Sets the horizontal position of the CC data. Usually 135. */
2065# define TV_CC_HOFF_MASK 0x03ff0000
2066# define TV_CC_HOFF_SHIFT 16
2067/** Sets the vertical position of the CC data. Usually 21 */
2068# define TV_CC_LINE_MASK 0x0000003f
2069# define TV_CC_LINE_SHIFT 0
2070
2071#define TV_CC_DATA 0x68094
2072# define TV_CC_RDY (1 << 31)
2073/** Second word of CC data to be transmitted. */
2074# define TV_CC_DATA_2_MASK 0x007f0000
2075# define TV_CC_DATA_2_SHIFT 16
2076/** First word of CC data to be transmitted. */
2077# define TV_CC_DATA_1_MASK 0x0000007f
2078# define TV_CC_DATA_1_SHIFT 0
2079
2080#define TV_H_LUMA_0 0x68100
2081#define TV_H_LUMA_59 0x681ec
2082#define TV_H_CHROMA_0 0x68200
2083#define TV_H_CHROMA_59 0x682ec
2084#define TV_V_LUMA_0 0x68300
2085#define TV_V_LUMA_42 0x683a8
2086#define TV_V_CHROMA_0 0x68400
2087#define TV_V_CHROMA_42 0x684a8
2088
2089/* Display Port */
2090#define DP_A 0x64000 /* eDP */
2091#define DP_B 0x64100
2092#define DP_C 0x64200
2093#define DP_D 0x64300
2094
2095#define DP_PORT_EN (1 << 31)
2096#define DP_PIPEB_SELECT (1 << 30)
2097#define DP_PIPE_MASK (1 << 30)
2098
2099/* Link training mode - select a suitable mode for each stage */
2100#define DP_LINK_TRAIN_PAT_1 (0 << 28)
2101#define DP_LINK_TRAIN_PAT_2 (1 << 28)
2102#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
2103#define DP_LINK_TRAIN_OFF (3 << 28)
2104#define DP_LINK_TRAIN_MASK (3 << 28)
2105#define DP_LINK_TRAIN_SHIFT 28
2106
2107/* CPT Link training mode */
2108#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
2109#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
2110#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
2111#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
2112#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
2113#define DP_LINK_TRAIN_SHIFT_CPT 8
2114
2115/* Signal voltages. These are mostly controlled by the other end */
2116#define DP_VOLTAGE_0_4 (0 << 25)
2117#define DP_VOLTAGE_0_6 (1 << 25)
2118#define DP_VOLTAGE_0_8 (2 << 25)
2119#define DP_VOLTAGE_1_2 (3 << 25)
2120#define DP_VOLTAGE_MASK (7 << 25)
2121#define DP_VOLTAGE_SHIFT 25
2122
2123/* Signal pre-emphasis levels, like voltages, the other end tells us what
2124 * they want
2125 */
2126#define DP_PRE_EMPHASIS_0 (0 << 22)
2127#define DP_PRE_EMPHASIS_3_5 (1 << 22)
2128#define DP_PRE_EMPHASIS_6 (2 << 22)
2129#define DP_PRE_EMPHASIS_9_5 (3 << 22)
2130#define DP_PRE_EMPHASIS_MASK (7 << 22)
2131#define DP_PRE_EMPHASIS_SHIFT 22
2132
2133/* How many wires to use. I guess 3 was too hard */
2134#define DP_PORT_WIDTH_1 (0 << 19)
2135#define DP_PORT_WIDTH_2 (1 << 19)
2136#define DP_PORT_WIDTH_4 (3 << 19)
2137#define DP_PORT_WIDTH_MASK (7 << 19)
2138
2139/* Mystic DPCD version 1.1 special mode */
2140#define DP_ENHANCED_FRAMING (1 << 18)
2141
2142/* eDP */
2143#define DP_PLL_FREQ_270MHZ (0 << 16)
2144#define DP_PLL_FREQ_160MHZ (1 << 16)
2145#define DP_PLL_FREQ_MASK (3 << 16)
2146
2147/** locked once port is enabled */
2148#define DP_PORT_REVERSAL (1 << 15)
2149
2150/* eDP */
2151#define DP_PLL_ENABLE (1 << 14)
2152
2153/** sends the clock on lane 15 of the PEG for debug */
2154#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
2155
2156#define DP_SCRAMBLING_DISABLE (1 << 12)
2157#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
2158
2159/** limit RGB values to avoid confusing TVs */
2160#define DP_COLOR_RANGE_16_235 (1 << 8)
2161
2162/** Turn on the audio link */
2163#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
2164
2165/** vs and hs sync polarity */
2166#define DP_SYNC_VS_HIGH (1 << 4)
2167#define DP_SYNC_HS_HIGH (1 << 3)
2168
2169/** A fantasy */
2170#define DP_DETECTED (1 << 2)
2171
2172/** The aux channel provides a way to talk to the
2173 * signal sink for DDC etc. Max packet size supported
2174 * is 20 bytes in each direction, hence the 5 fixed
2175 * data registers
2176 */
2177#define DPA_AUX_CH_CTL 0x64010
2178#define DPA_AUX_CH_DATA1 0x64014
2179#define DPA_AUX_CH_DATA2 0x64018
2180#define DPA_AUX_CH_DATA3 0x6401c
2181#define DPA_AUX_CH_DATA4 0x64020
2182#define DPA_AUX_CH_DATA5 0x64024
2183
2184#define DPB_AUX_CH_CTL 0x64110
2185#define DPB_AUX_CH_DATA1 0x64114
2186#define DPB_AUX_CH_DATA2 0x64118
2187#define DPB_AUX_CH_DATA3 0x6411c
2188#define DPB_AUX_CH_DATA4 0x64120
2189#define DPB_AUX_CH_DATA5 0x64124
2190
2191#define DPC_AUX_CH_CTL 0x64210
2192#define DPC_AUX_CH_DATA1 0x64214
2193#define DPC_AUX_CH_DATA2 0x64218
2194#define DPC_AUX_CH_DATA3 0x6421c
2195#define DPC_AUX_CH_DATA4 0x64220
2196#define DPC_AUX_CH_DATA5 0x64224
2197
2198#define DPD_AUX_CH_CTL 0x64310
2199#define DPD_AUX_CH_DATA1 0x64314
2200#define DPD_AUX_CH_DATA2 0x64318
2201#define DPD_AUX_CH_DATA3 0x6431c
2202#define DPD_AUX_CH_DATA4 0x64320
2203#define DPD_AUX_CH_DATA5 0x64324
2204
2205#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
2206#define DP_AUX_CH_CTL_DONE (1 << 30)
2207#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
2208#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
2209#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
2210#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
2211#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
2212#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
2213#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
2214#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
2215#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
2216#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
2217#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
2218#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
2219#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
2220#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
2221#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
2222#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
2223#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
2224#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
2225#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
2226
2227/*
2228 * Computing GMCH M and N values for the Display Port link
2229 *
2230 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
2231 *
2232 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
2233 *
2234 * The GMCH value is used internally
2235 *
2236 * bytes_per_pixel is the number of bytes coming out of the plane,
2237 * which is after the LUTs, so we want the bytes for our color format.
2238 * For our current usage, this is always 3, one byte for R, G and B.
2239 */
2240#define _PIPEA_GMCH_DATA_M 0x70050
2241#define _PIPEB_GMCH_DATA_M 0x71050
2242
2243/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
2244#define PIPE_GMCH_DATA_M_TU_SIZE_MASK (0x3f << 25)
2245#define PIPE_GMCH_DATA_M_TU_SIZE_SHIFT 25
2246
2247#define PIPE_GMCH_DATA_M_MASK (0xffffff)
2248
2249#define _PIPEA_GMCH_DATA_N 0x70054
2250#define _PIPEB_GMCH_DATA_N 0x71054
2251#define PIPE_GMCH_DATA_N_MASK (0xffffff)
2252
2253/*
2254 * Computing Link M and N values for the Display Port link
2255 *
2256 * Link M / N = pixel_clock / ls_clk
2257 *
2258 * (the DP spec calls pixel_clock the 'strm_clk')
2259 *
2260 * The Link value is transmitted in the Main Stream
2261 * Attributes and VB-ID.
2262 */
2263
2264#define _PIPEA_DP_LINK_M 0x70060
2265#define _PIPEB_DP_LINK_M 0x71060
2266#define PIPEA_DP_LINK_M_MASK (0xffffff)
2267
2268#define _PIPEA_DP_LINK_N 0x70064
2269#define _PIPEB_DP_LINK_N 0x71064
2270#define PIPEA_DP_LINK_N_MASK (0xffffff)
2271
2272#define PIPE_GMCH_DATA_M(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_M, _PIPEB_GMCH_DATA_M)
2273#define PIPE_GMCH_DATA_N(pipe) _PIPE(pipe, _PIPEA_GMCH_DATA_N, _PIPEB_GMCH_DATA_N)
2274#define PIPE_DP_LINK_M(pipe) _PIPE(pipe, _PIPEA_DP_LINK_M, _PIPEB_DP_LINK_M)
2275#define PIPE_DP_LINK_N(pipe) _PIPE(pipe, _PIPEA_DP_LINK_N, _PIPEB_DP_LINK_N)
2276
2277/* Display & cursor control */
2278
2279/* Pipe A */
2280#define _PIPEADSL 0x70000
2281#define DSL_LINEMASK 0x00000fff
2282#define _PIPEACONF 0x70008
2283#define PIPECONF_ENABLE (1<<31)
2284#define PIPECONF_DISABLE 0
2285#define PIPECONF_DOUBLE_WIDE (1<<30)
2286#define I965_PIPECONF_ACTIVE (1<<30)
2287#define PIPECONF_SINGLE_WIDE 0
2288#define PIPECONF_PIPE_UNLOCKED 0
2289#define PIPECONF_PIPE_LOCKED (1<<25)
2290#define PIPECONF_PALETTE 0
2291#define PIPECONF_GAMMA (1<<24)
2292#define PIPECONF_FORCE_BORDER (1<<25)
2293#define PIPECONF_PROGRESSIVE (0 << 21)
2294#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
2295#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21)
2296#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
2297#define PIPECONF_BPP_MASK (0x000000e0)
2298#define PIPECONF_BPP_8 (0<<5)
2299#define PIPECONF_BPP_10 (1<<5)
2300#define PIPECONF_BPP_6 (2<<5)
2301#define PIPECONF_BPP_12 (3<<5)
2302#define PIPECONF_DITHER_EN (1<<4)
2303#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
2304#define PIPECONF_DITHER_TYPE_SP (0<<2)
2305#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
2306#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
2307#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
2308#define _PIPEASTAT 0x70024
2309#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
2310#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
2311#define PIPE_CRC_DONE_ENABLE (1UL<<28)
2312#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
2313#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
2314#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
2315#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
2316#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
2317#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
2318#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
2319#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
2320#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
2321#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
2322#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
2323#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
2324#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
2325#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
2326#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
2327#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
2328#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
2329#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
2330#define PIPE_DPST_EVENT_STATUS (1UL<<7)
2331#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
2332#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
2333#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
2334#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
2335#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
2336#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
2337#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
2338#define PIPE_BPC_MASK (7 << 5) /* Ironlake */
2339#define PIPE_8BPC (0 << 5)
2340#define PIPE_10BPC (1 << 5)
2341#define PIPE_6BPC (2 << 5)
2342#define PIPE_12BPC (3 << 5)
2343
2344#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
2345#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF)
2346#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
2347#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
2348#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
2349#define PIPESTAT(pipe) _PIPE(pipe, _PIPEASTAT, _PIPEBSTAT)
2350
2351#define DSPARB 0x70030
2352#define DSPARB_CSTART_MASK (0x7f << 7)
2353#define DSPARB_CSTART_SHIFT 7
2354#define DSPARB_BSTART_MASK (0x7f)
2355#define DSPARB_BSTART_SHIFT 0
2356#define DSPARB_BEND_SHIFT 9 /* on 855 */
2357#define DSPARB_AEND_SHIFT 0
2358
2359#define DSPFW1 0x70034
2360#define DSPFW_SR_SHIFT 23
2361#define DSPFW_SR_MASK (0x1ff<<23)
2362#define DSPFW_CURSORB_SHIFT 16
2363#define DSPFW_CURSORB_MASK (0x3f<<16)
2364#define DSPFW_PLANEB_SHIFT 8
2365#define DSPFW_PLANEB_MASK (0x7f<<8)
2366#define DSPFW_PLANEA_MASK (0x7f)
2367#define DSPFW2 0x70038
2368#define DSPFW_CURSORA_MASK 0x00003f00
2369#define DSPFW_CURSORA_SHIFT 8
2370#define DSPFW_PLANEC_MASK (0x7f)
2371#define DSPFW3 0x7003c
2372#define DSPFW_HPLL_SR_EN (1<<31)
2373#define DSPFW_CURSOR_SR_SHIFT 24
2374#define PINEVIEW_SELF_REFRESH_EN (1<<30)
2375#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
2376#define DSPFW_HPLL_CURSOR_SHIFT 16
2377#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
2378#define DSPFW_HPLL_SR_MASK (0x1ff)
2379
2380/* FIFO watermark sizes etc */
2381#define G4X_FIFO_LINE_SIZE 64
2382#define I915_FIFO_LINE_SIZE 64
2383#define I830_FIFO_LINE_SIZE 32
2384
2385#define G4X_FIFO_SIZE 127
2386#define I965_FIFO_SIZE 512
2387#define I945_FIFO_SIZE 127
2388#define I915_FIFO_SIZE 95
2389#define I855GM_FIFO_SIZE 127 /* In cachelines */
2390#define I830_FIFO_SIZE 95
2391
2392#define G4X_MAX_WM 0x3f
2393#define I915_MAX_WM 0x3f
2394
2395#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
2396#define PINEVIEW_FIFO_LINE_SIZE 64
2397#define PINEVIEW_MAX_WM 0x1ff
2398#define PINEVIEW_DFT_WM 0x3f
2399#define PINEVIEW_DFT_HPLLOFF_WM 0
2400#define PINEVIEW_GUARD_WM 10
2401#define PINEVIEW_CURSOR_FIFO 64
2402#define PINEVIEW_CURSOR_MAX_WM 0x3f
2403#define PINEVIEW_CURSOR_DFT_WM 0
2404#define PINEVIEW_CURSOR_GUARD_WM 5
2405
2406#define I965_CURSOR_FIFO 64
2407#define I965_CURSOR_MAX_WM 32
2408#define I965_CURSOR_DFT_WM 8
2409
2410/* define the Watermark register on Ironlake */
2411#define WM0_PIPEA_ILK 0x45100
2412#define WM0_PIPE_PLANE_MASK (0x7f<<16)
2413#define WM0_PIPE_PLANE_SHIFT 16
2414#define WM0_PIPE_SPRITE_MASK (0x3f<<8)
2415#define WM0_PIPE_SPRITE_SHIFT 8
2416#define WM0_PIPE_CURSOR_MASK (0x1f)
2417
2418#define WM0_PIPEB_ILK 0x45104
2419#define WM1_LP_ILK 0x45108
2420#define WM1_LP_SR_EN (1<<31)
2421#define WM1_LP_LATENCY_SHIFT 24
2422#define WM1_LP_LATENCY_MASK (0x7f<<24)
2423#define WM1_LP_FBC_MASK (0xf<<20)
2424#define WM1_LP_FBC_SHIFT 20
2425#define WM1_LP_SR_MASK (0x1ff<<8)
2426#define WM1_LP_SR_SHIFT 8
2427#define WM1_LP_CURSOR_MASK (0x3f)
2428#define WM2_LP_ILK 0x4510c
2429#define WM2_LP_EN (1<<31)
2430#define WM3_LP_ILK 0x45110
2431#define WM3_LP_EN (1<<31)
2432#define WM1S_LP_ILK 0x45120
2433#define WM1S_LP_EN (1<<31)
2434
2435/* Memory latency timer register */
2436#define MLTR_ILK 0x11222
2437#define MLTR_WM1_SHIFT 0
2438#define MLTR_WM2_SHIFT 8
2439/* the unit of memory self-refresh latency time is 0.5us */
2440#define ILK_SRLT_MASK 0x3f
2441#define ILK_LATENCY(shift) (I915_READ(MLTR_ILK) >> (shift) & ILK_SRLT_MASK)
2442#define ILK_READ_WM1_LATENCY() ILK_LATENCY(MLTR_WM1_SHIFT)
2443#define ILK_READ_WM2_LATENCY() ILK_LATENCY(MLTR_WM2_SHIFT)
2444
2445/* define the fifo size on Ironlake */
2446#define ILK_DISPLAY_FIFO 128
2447#define ILK_DISPLAY_MAXWM 64
2448#define ILK_DISPLAY_DFTWM 8
2449#define ILK_CURSOR_FIFO 32
2450#define ILK_CURSOR_MAXWM 16
2451#define ILK_CURSOR_DFTWM 8
2452
2453#define ILK_DISPLAY_SR_FIFO 512
2454#define ILK_DISPLAY_MAX_SRWM 0x1ff
2455#define ILK_DISPLAY_DFT_SRWM 0x3f
2456#define ILK_CURSOR_SR_FIFO 64
2457#define ILK_CURSOR_MAX_SRWM 0x3f
2458#define ILK_CURSOR_DFT_SRWM 8
2459
2460#define ILK_FIFO_LINE_SIZE 64
2461
2462/* define the WM info on Sandybridge */
2463#define SNB_DISPLAY_FIFO 128
2464#define SNB_DISPLAY_MAXWM 0x7f /* bit 16:22 */
2465#define SNB_DISPLAY_DFTWM 8
2466#define SNB_CURSOR_FIFO 32
2467#define SNB_CURSOR_MAXWM 0x1f /* bit 4:0 */
2468#define SNB_CURSOR_DFTWM 8
2469
2470#define SNB_DISPLAY_SR_FIFO 512
2471#define SNB_DISPLAY_MAX_SRWM 0x1ff /* bit 16:8 */
2472#define SNB_DISPLAY_DFT_SRWM 0x3f
2473#define SNB_CURSOR_SR_FIFO 64
2474#define SNB_CURSOR_MAX_SRWM 0x3f /* bit 5:0 */
2475#define SNB_CURSOR_DFT_SRWM 8
2476
2477#define SNB_FBC_MAX_SRWM 0xf /* bit 23:20 */
2478
2479#define SNB_FIFO_LINE_SIZE 64
2480
2481
2482/* the address where we get all kinds of latency value */
2483#define SSKPD 0x5d10
2484#define SSKPD_WM_MASK 0x3f
2485#define SSKPD_WM0_SHIFT 0
2486#define SSKPD_WM1_SHIFT 8
2487#define SSKPD_WM2_SHIFT 16
2488#define SSKPD_WM3_SHIFT 24
2489
2490#define SNB_LATENCY(shift) (I915_READ(MCHBAR_MIRROR_BASE_SNB + SSKPD) >> (shift) & SSKPD_WM_MASK)
2491#define SNB_READ_WM0_LATENCY() SNB_LATENCY(SSKPD_WM0_SHIFT)
2492#define SNB_READ_WM1_LATENCY() SNB_LATENCY(SSKPD_WM1_SHIFT)
2493#define SNB_READ_WM2_LATENCY() SNB_LATENCY(SSKPD_WM2_SHIFT)
2494#define SNB_READ_WM3_LATENCY() SNB_LATENCY(SSKPD_WM3_SHIFT)
2495
2496/*
2497 * The two pipe frame counter registers are not synchronized, so
2498 * reading a stable value is somewhat tricky. The following code
2499 * should work:
2500 *
2501 * do {
2502 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2503 * PIPE_FRAME_HIGH_SHIFT;
2504 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
2505 * PIPE_FRAME_LOW_SHIFT);
2506 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
2507 * PIPE_FRAME_HIGH_SHIFT);
2508 * } while (high1 != high2);
2509 * frame = (high1 << 8) | low1;
2510 */
2511#define _PIPEAFRAMEHIGH 0x70040
2512#define PIPE_FRAME_HIGH_MASK 0x0000ffff
2513#define PIPE_FRAME_HIGH_SHIFT 0
2514#define _PIPEAFRAMEPIXEL 0x70044
2515#define PIPE_FRAME_LOW_MASK 0xff000000
2516#define PIPE_FRAME_LOW_SHIFT 24
2517#define PIPE_PIXEL_MASK 0x00ffffff
2518#define PIPE_PIXEL_SHIFT 0
2519/* GM45+ just has to be different */
2520#define _PIPEA_FRMCOUNT_GM45 0x70040
2521#define _PIPEA_FLIPCOUNT_GM45 0x70044
2522#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
2523
2524/* Cursor A & B regs */
2525#define _CURACNTR 0x70080
2526/* Old style CUR*CNTR flags (desktop 8xx) */
2527#define CURSOR_ENABLE 0x80000000
2528#define CURSOR_GAMMA_ENABLE 0x40000000
2529#define CURSOR_STRIDE_MASK 0x30000000
2530#define CURSOR_FORMAT_SHIFT 24
2531#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
2532#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
2533#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
2534#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
2535#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
2536#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
2537/* New style CUR*CNTR flags */
2538#define CURSOR_MODE 0x27
2539#define CURSOR_MODE_DISABLE 0x00
2540#define CURSOR_MODE_64_32B_AX 0x07
2541#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
2542#define MCURSOR_PIPE_SELECT (1 << 28)
2543#define MCURSOR_PIPE_A 0x00
2544#define MCURSOR_PIPE_B (1 << 28)
2545#define MCURSOR_GAMMA_ENABLE (1 << 26)
2546#define _CURABASE 0x70084
2547#define _CURAPOS 0x70088
2548#define CURSOR_POS_MASK 0x007FF
2549#define CURSOR_POS_SIGN 0x8000
2550#define CURSOR_X_SHIFT 0
2551#define CURSOR_Y_SHIFT 16
2552#define CURSIZE 0x700a0
2553#define _CURBCNTR 0x700c0
2554#define _CURBBASE 0x700c4
2555#define _CURBPOS 0x700c8
2556
2557#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
2558#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
2559#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
2560
2561/* Display A control */
2562#define _DSPACNTR 0x70180
2563#define DISPLAY_PLANE_ENABLE (1<<31)
2564#define DISPLAY_PLANE_DISABLE 0
2565#define DISPPLANE_GAMMA_ENABLE (1<<30)
2566#define DISPPLANE_GAMMA_DISABLE 0
2567#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
2568#define DISPPLANE_8BPP (0x2<<26)
2569#define DISPPLANE_15_16BPP (0x4<<26)
2570#define DISPPLANE_16BPP (0x5<<26)
2571#define DISPPLANE_32BPP_NO_ALPHA (0x6<<26)
2572#define DISPPLANE_32BPP (0x7<<26)
2573#define DISPPLANE_32BPP_30BIT_NO_ALPHA (0xa<<26)
2574#define DISPPLANE_STEREO_ENABLE (1<<25)
2575#define DISPPLANE_STEREO_DISABLE 0
2576#define DISPPLANE_SEL_PIPE_SHIFT 24
2577#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
2578#define DISPPLANE_SEL_PIPE_A 0
2579#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
2580#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
2581#define DISPPLANE_SRC_KEY_DISABLE 0
2582#define DISPPLANE_LINE_DOUBLE (1<<20)
2583#define DISPPLANE_NO_LINE_DOUBLE 0
2584#define DISPPLANE_STEREO_POLARITY_FIRST 0
2585#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
2586#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
2587#define DISPPLANE_TILED (1<<10)
2588#define _DSPAADDR 0x70184
2589#define _DSPASTRIDE 0x70188
2590#define _DSPAPOS 0x7018C /* reserved */
2591#define _DSPASIZE 0x70190
2592#define _DSPASURF 0x7019C /* 965+ only */
2593#define _DSPATILEOFF 0x701A4 /* 965+ only */
2594
2595#define DSPCNTR(plane) _PIPE(plane, _DSPACNTR, _DSPBCNTR)
2596#define DSPADDR(plane) _PIPE(plane, _DSPAADDR, _DSPBADDR)
2597#define DSPSTRIDE(plane) _PIPE(plane, _DSPASTRIDE, _DSPBSTRIDE)
2598#define DSPPOS(plane) _PIPE(plane, _DSPAPOS, _DSPBPOS)
2599#define DSPSIZE(plane) _PIPE(plane, _DSPASIZE, _DSPBSIZE)
2600#define DSPSURF(plane) _PIPE(plane, _DSPASURF, _DSPBSURF)
2601#define DSPTILEOFF(plane) _PIPE(plane, _DSPATILEOFF, _DSPBTILEOFF)
2602
2603/* VBIOS flags */
2604#define SWF00 0x71410
2605#define SWF01 0x71414
2606#define SWF02 0x71418
2607#define SWF03 0x7141c
2608#define SWF04 0x71420
2609#define SWF05 0x71424
2610#define SWF06 0x71428
2611#define SWF10 0x70410
2612#define SWF11 0x70414
2613#define SWF14 0x71420
2614#define SWF30 0x72414
2615#define SWF31 0x72418
2616#define SWF32 0x7241c
2617
2618/* Pipe B */
2619#define _PIPEBDSL 0x71000
2620#define _PIPEBCONF 0x71008
2621#define _PIPEBSTAT 0x71024
2622#define _PIPEBFRAMEHIGH 0x71040
2623#define _PIPEBFRAMEPIXEL 0x71044
2624#define _PIPEB_FRMCOUNT_GM45 0x71040
2625#define _PIPEB_FLIPCOUNT_GM45 0x71044
2626
2627
2628/* Display B control */
2629#define _DSPBCNTR 0x71180
2630#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
2631#define DISPPLANE_ALPHA_TRANS_DISABLE 0
2632#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
2633#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
2634#define _DSPBADDR 0x71184
2635#define _DSPBSTRIDE 0x71188
2636#define _DSPBPOS 0x7118C
2637#define _DSPBSIZE 0x71190
2638#define _DSPBSURF 0x7119C
2639#define _DSPBTILEOFF 0x711A4
2640
2641/* VBIOS regs */
2642#define VGACNTRL 0x71400
2643# define VGA_DISP_DISABLE (1 << 31)
2644# define VGA_2X_MODE (1 << 30)
2645# define VGA_PIPE_B_SELECT (1 << 29)
2646
2647/* Ironlake */
2648
2649#define CPU_VGACNTRL 0x41000
2650
2651#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
2652#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
2653#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
2654#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
2655#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
2656#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
2657#define DIGITAL_PORTA_NO_DETECT (0 << 0)
2658#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
2659#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
2660
2661/* refresh rate hardware control */
2662#define RR_HW_CTL 0x45300
2663#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
2664#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
2665
2666#define FDI_PLL_BIOS_0 0x46000
2667#define FDI_PLL_FB_CLOCK_MASK 0xff
2668#define FDI_PLL_BIOS_1 0x46004
2669#define FDI_PLL_BIOS_2 0x46008
2670#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
2671#define DISPLAY_PORT_PLL_BIOS_1 0x46010
2672#define DISPLAY_PORT_PLL_BIOS_2 0x46014
2673
2674#define PCH_DSPCLK_GATE_D 0x42020
2675# define DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
2676# define DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
2677# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7)
2678# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5)
2679
2680#define PCH_3DCGDIS0 0x46020
2681# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
2682# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
2683
2684#define PCH_3DCGDIS1 0x46024
2685# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
2686
2687#define FDI_PLL_FREQ_CTL 0x46030
2688#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
2689#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
2690#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
2691
2692
2693#define _PIPEA_DATA_M1 0x60030
2694#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
2695#define TU_SIZE_MASK 0x7e000000
2696#define PIPE_DATA_M1_OFFSET 0
2697#define _PIPEA_DATA_N1 0x60034
2698#define PIPE_DATA_N1_OFFSET 0
2699
2700#define _PIPEA_DATA_M2 0x60038
2701#define PIPE_DATA_M2_OFFSET 0
2702#define _PIPEA_DATA_N2 0x6003c
2703#define PIPE_DATA_N2_OFFSET 0
2704
2705#define _PIPEA_LINK_M1 0x60040
2706#define PIPE_LINK_M1_OFFSET 0
2707#define _PIPEA_LINK_N1 0x60044
2708#define PIPE_LINK_N1_OFFSET 0
2709
2710#define _PIPEA_LINK_M2 0x60048
2711#define PIPE_LINK_M2_OFFSET 0
2712#define _PIPEA_LINK_N2 0x6004c
2713#define PIPE_LINK_N2_OFFSET 0
2714
2715/* PIPEB timing regs are same start from 0x61000 */
2716
2717#define _PIPEB_DATA_M1 0x61030
2718#define _PIPEB_DATA_N1 0x61034
2719
2720#define _PIPEB_DATA_M2 0x61038
2721#define _PIPEB_DATA_N2 0x6103c
2722
2723#define _PIPEB_LINK_M1 0x61040
2724#define _PIPEB_LINK_N1 0x61044
2725
2726#define _PIPEB_LINK_M2 0x61048
2727#define _PIPEB_LINK_N2 0x6104c
2728
2729#define PIPE_DATA_M1(pipe) _PIPE(pipe, _PIPEA_DATA_M1, _PIPEB_DATA_M1)
2730#define PIPE_DATA_N1(pipe) _PIPE(pipe, _PIPEA_DATA_N1, _PIPEB_DATA_N1)
2731#define PIPE_DATA_M2(pipe) _PIPE(pipe, _PIPEA_DATA_M2, _PIPEB_DATA_M2)
2732#define PIPE_DATA_N2(pipe) _PIPE(pipe, _PIPEA_DATA_N2, _PIPEB_DATA_N2)
2733#define PIPE_LINK_M1(pipe) _PIPE(pipe, _PIPEA_LINK_M1, _PIPEB_LINK_M1)
2734#define PIPE_LINK_N1(pipe) _PIPE(pipe, _PIPEA_LINK_N1, _PIPEB_LINK_N1)
2735#define PIPE_LINK_M2(pipe) _PIPE(pipe, _PIPEA_LINK_M2, _PIPEB_LINK_M2)
2736#define PIPE_LINK_N2(pipe) _PIPE(pipe, _PIPEA_LINK_N2, _PIPEB_LINK_N2)
2737
2738/* CPU panel fitter */
2739/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
2740#define _PFA_CTL_1 0x68080
2741#define _PFB_CTL_1 0x68880
2742#define PF_ENABLE (1<<31)
2743#define PF_FILTER_MASK (3<<23)
2744#define PF_FILTER_PROGRAMMED (0<<23)
2745#define PF_FILTER_MED_3x3 (1<<23)
2746#define PF_FILTER_EDGE_ENHANCE (2<<23)
2747#define PF_FILTER_EDGE_SOFTEN (3<<23)
2748#define _PFA_WIN_SZ 0x68074
2749#define _PFB_WIN_SZ 0x68874
2750#define _PFA_WIN_POS 0x68070
2751#define _PFB_WIN_POS 0x68870
2752#define _PFA_VSCALE 0x68084
2753#define _PFB_VSCALE 0x68884
2754#define _PFA_HSCALE 0x68090
2755#define _PFB_HSCALE 0x68890
2756
2757#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
2758#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
2759#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
2760#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
2761#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
2762
2763/* legacy palette */
2764#define _LGC_PALETTE_A 0x4a000
2765#define _LGC_PALETTE_B 0x4a800
2766#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
2767
2768/* interrupts */
2769#define DE_MASTER_IRQ_CONTROL (1 << 31)
2770#define DE_SPRITEB_FLIP_DONE (1 << 29)
2771#define DE_SPRITEA_FLIP_DONE (1 << 28)
2772#define DE_PLANEB_FLIP_DONE (1 << 27)
2773#define DE_PLANEA_FLIP_DONE (1 << 26)
2774#define DE_PCU_EVENT (1 << 25)
2775#define DE_GTT_FAULT (1 << 24)
2776#define DE_POISON (1 << 23)
2777#define DE_PERFORM_COUNTER (1 << 22)
2778#define DE_PCH_EVENT (1 << 21)
2779#define DE_AUX_CHANNEL_A (1 << 20)
2780#define DE_DP_A_HOTPLUG (1 << 19)
2781#define DE_GSE (1 << 18)
2782#define DE_PIPEB_VBLANK (1 << 15)
2783#define DE_PIPEB_EVEN_FIELD (1 << 14)
2784#define DE_PIPEB_ODD_FIELD (1 << 13)
2785#define DE_PIPEB_LINE_COMPARE (1 << 12)
2786#define DE_PIPEB_VSYNC (1 << 11)
2787#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
2788#define DE_PIPEA_VBLANK (1 << 7)
2789#define DE_PIPEA_EVEN_FIELD (1 << 6)
2790#define DE_PIPEA_ODD_FIELD (1 << 5)
2791#define DE_PIPEA_LINE_COMPARE (1 << 4)
2792#define DE_PIPEA_VSYNC (1 << 3)
2793#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
2794
2795/* More Ivybridge lolz */
2796#define DE_ERR_DEBUG_IVB (1<<30)
2797#define DE_GSE_IVB (1<<29)
2798#define DE_PCH_EVENT_IVB (1<<28)
2799#define DE_DP_A_HOTPLUG_IVB (1<<27)
2800#define DE_AUX_CHANNEL_A_IVB (1<<26)
2801#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
2802#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
2803#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
2804#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
2805#define DE_PIPEB_VBLANK_IVB (1<<5)
2806#define DE_PIPEA_VBLANK_IVB (1<<0)
2807
2808#define DEISR 0x44000
2809#define DEIMR 0x44004
2810#define DEIIR 0x44008
2811#define DEIER 0x4400c
2812
2813/* GT interrupt */
2814#define GT_PIPE_NOTIFY (1 << 4)
2815#define GT_SYNC_STATUS (1 << 2)
2816#define GT_USER_INTERRUPT (1 << 0)
2817#define GT_BSD_USER_INTERRUPT (1 << 5)
2818#define GT_GEN6_BSD_USER_INTERRUPT (1 << 12)
2819#define GT_BLT_USER_INTERRUPT (1 << 22)
2820
2821#define GTISR 0x44010
2822#define GTIMR 0x44014
2823#define GTIIR 0x44018
2824#define GTIER 0x4401c
2825
2826#define ILK_DISPLAY_CHICKEN2 0x42004
2827/* Required on all Ironlake and Sandybridge according to the B-Spec. */
2828#define ILK_ELPIN_409_SELECT (1 << 25)
2829#define ILK_DPARB_GATE (1<<22)
2830#define ILK_VSDPFD_FULL (1<<21)
2831#define ILK_DISPLAY_CHICKEN_FUSES 0x42014
2832#define ILK_INTERNAL_GRAPHICS_DISABLE (1<<31)
2833#define ILK_INTERNAL_DISPLAY_DISABLE (1<<30)
2834#define ILK_DISPLAY_DEBUG_DISABLE (1<<29)
2835#define ILK_HDCP_DISABLE (1<<25)
2836#define ILK_eDP_A_DISABLE (1<<24)
2837#define ILK_DESKTOP (1<<23)
2838#define ILK_DSPCLK_GATE 0x42020
2839#define IVB_VRHUNIT_CLK_GATE (1<<28)
2840#define ILK_DPARB_CLK_GATE (1<<5)
2841#define ILK_DPFD_CLK_GATE (1<<7)
2842
2843/* According to spec this bit 7/8/9 of 0x42020 should be set to enable FBC */
2844#define ILK_CLK_FBC (1<<7)
2845#define ILK_DPFC_DIS1 (1<<8)
2846#define ILK_DPFC_DIS2 (1<<9)
2847
2848#define DISP_ARB_CTL 0x45000
2849#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
2850#define DISP_FBC_WM_DIS (1<<15)
2851
2852/* PCH */
2853
2854/* south display engine interrupt */
2855#define SDE_AUDIO_POWER_D (1 << 27)
2856#define SDE_AUDIO_POWER_C (1 << 26)
2857#define SDE_AUDIO_POWER_B (1 << 25)
2858#define SDE_AUDIO_POWER_SHIFT (25)
2859#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
2860#define SDE_GMBUS (1 << 24)
2861#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
2862#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
2863#define SDE_AUDIO_HDCP_MASK (3 << 22)
2864#define SDE_AUDIO_TRANSB (1 << 21)
2865#define SDE_AUDIO_TRANSA (1 << 20)
2866#define SDE_AUDIO_TRANS_MASK (3 << 20)
2867#define SDE_POISON (1 << 19)
2868/* 18 reserved */
2869#define SDE_FDI_RXB (1 << 17)
2870#define SDE_FDI_RXA (1 << 16)
2871#define SDE_FDI_MASK (3 << 16)
2872#define SDE_AUXD (1 << 15)
2873#define SDE_AUXC (1 << 14)
2874#define SDE_AUXB (1 << 13)
2875#define SDE_AUX_MASK (7 << 13)
2876/* 12 reserved */
2877#define SDE_CRT_HOTPLUG (1 << 11)
2878#define SDE_PORTD_HOTPLUG (1 << 10)
2879#define SDE_PORTC_HOTPLUG (1 << 9)
2880#define SDE_PORTB_HOTPLUG (1 << 8)
2881#define SDE_SDVOB_HOTPLUG (1 << 6)
2882#define SDE_HOTPLUG_MASK (0xf << 8)
2883#define SDE_TRANSB_CRC_DONE (1 << 5)
2884#define SDE_TRANSB_CRC_ERR (1 << 4)
2885#define SDE_TRANSB_FIFO_UNDER (1 << 3)
2886#define SDE_TRANSA_CRC_DONE (1 << 2)
2887#define SDE_TRANSA_CRC_ERR (1 << 1)
2888#define SDE_TRANSA_FIFO_UNDER (1 << 0)
2889#define SDE_TRANS_MASK (0x3f)
2890/* CPT */
2891#define SDE_CRT_HOTPLUG_CPT (1 << 19)
2892#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
2893#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
2894#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
2895#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
2896 SDE_PORTD_HOTPLUG_CPT | \
2897 SDE_PORTC_HOTPLUG_CPT | \
2898 SDE_PORTB_HOTPLUG_CPT)
2899
2900#define SDEISR 0xc4000
2901#define SDEIMR 0xc4004
2902#define SDEIIR 0xc4008
2903#define SDEIER 0xc400c
2904
2905/* digital port hotplug */
2906#define PCH_PORT_HOTPLUG 0xc4030
2907#define PORTD_HOTPLUG_ENABLE (1 << 20)
2908#define PORTD_PULSE_DURATION_2ms (0)
2909#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
2910#define PORTD_PULSE_DURATION_6ms (2 << 18)
2911#define PORTD_PULSE_DURATION_100ms (3 << 18)
2912#define PORTD_HOTPLUG_NO_DETECT (0)
2913#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
2914#define PORTD_HOTPLUG_LONG_DETECT (1 << 17)
2915#define PORTC_HOTPLUG_ENABLE (1 << 12)
2916#define PORTC_PULSE_DURATION_2ms (0)
2917#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
2918#define PORTC_PULSE_DURATION_6ms (2 << 10)
2919#define PORTC_PULSE_DURATION_100ms (3 << 10)
2920#define PORTC_HOTPLUG_NO_DETECT (0)
2921#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
2922#define PORTC_HOTPLUG_LONG_DETECT (1 << 9)
2923#define PORTB_HOTPLUG_ENABLE (1 << 4)
2924#define PORTB_PULSE_DURATION_2ms (0)
2925#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
2926#define PORTB_PULSE_DURATION_6ms (2 << 2)
2927#define PORTB_PULSE_DURATION_100ms (3 << 2)
2928#define PORTB_HOTPLUG_NO_DETECT (0)
2929#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
2930#define PORTB_HOTPLUG_LONG_DETECT (1 << 1)
2931
2932#define PCH_GPIOA 0xc5010
2933#define PCH_GPIOB 0xc5014
2934#define PCH_GPIOC 0xc5018
2935#define PCH_GPIOD 0xc501c
2936#define PCH_GPIOE 0xc5020
2937#define PCH_GPIOF 0xc5024
2938
2939#define PCH_GMBUS0 0xc5100
2940#define PCH_GMBUS1 0xc5104
2941#define PCH_GMBUS2 0xc5108
2942#define PCH_GMBUS3 0xc510c
2943#define PCH_GMBUS4 0xc5110
2944#define PCH_GMBUS5 0xc5120
2945
2946#define _PCH_DPLL_A 0xc6014
2947#define _PCH_DPLL_B 0xc6018
2948#define PCH_DPLL(pipe) _PIPE(pipe, _PCH_DPLL_A, _PCH_DPLL_B)
2949
2950#define _PCH_FPA0 0xc6040
2951#define FP_CB_TUNE (0x3<<22)
2952#define _PCH_FPA1 0xc6044
2953#define _PCH_FPB0 0xc6048
2954#define _PCH_FPB1 0xc604c
2955#define PCH_FP0(pipe) _PIPE(pipe, _PCH_FPA0, _PCH_FPB0)
2956#define PCH_FP1(pipe) _PIPE(pipe, _PCH_FPA1, _PCH_FPB1)
2957
2958#define PCH_DPLL_TEST 0xc606c
2959
2960#define PCH_DREF_CONTROL 0xC6200
2961#define DREF_CONTROL_MASK 0x7fc3
2962#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
2963#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
2964#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
2965#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
2966#define DREF_SSC_SOURCE_DISABLE (0<<11)
2967#define DREF_SSC_SOURCE_ENABLE (2<<11)
2968#define DREF_SSC_SOURCE_MASK (3<<11)
2969#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
2970#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
2971#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
2972#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
2973#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
2974#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
2975#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
2976#define DREF_SSC4_DOWNSPREAD (0<<6)
2977#define DREF_SSC4_CENTERSPREAD (1<<6)
2978#define DREF_SSC1_DISABLE (0<<1)
2979#define DREF_SSC1_ENABLE (1<<1)
2980#define DREF_SSC4_DISABLE (0)
2981#define DREF_SSC4_ENABLE (1)
2982
2983#define PCH_RAWCLK_FREQ 0xc6204
2984#define FDL_TP1_TIMER_SHIFT 12
2985#define FDL_TP1_TIMER_MASK (3<<12)
2986#define FDL_TP2_TIMER_SHIFT 10
2987#define FDL_TP2_TIMER_MASK (3<<10)
2988#define RAWCLK_FREQ_MASK 0x3ff
2989
2990#define PCH_DPLL_TMR_CFG 0xc6208
2991
2992#define PCH_SSC4_PARMS 0xc6210
2993#define PCH_SSC4_AUX_PARMS 0xc6214
2994
2995#define PCH_DPLL_SEL 0xc7000
2996#define TRANSA_DPLL_ENABLE (1<<3)
2997#define TRANSA_DPLLB_SEL (1<<0)
2998#define TRANSA_DPLLA_SEL 0
2999#define TRANSB_DPLL_ENABLE (1<<7)
3000#define TRANSB_DPLLB_SEL (1<<4)
3001#define TRANSB_DPLLA_SEL (0)
3002#define TRANSC_DPLL_ENABLE (1<<11)
3003#define TRANSC_DPLLB_SEL (1<<8)
3004#define TRANSC_DPLLA_SEL (0)
3005
3006/* transcoder */
3007
3008#define _TRANS_HTOTAL_A 0xe0000
3009#define TRANS_HTOTAL_SHIFT 16
3010#define TRANS_HACTIVE_SHIFT 0
3011#define _TRANS_HBLANK_A 0xe0004
3012#define TRANS_HBLANK_END_SHIFT 16
3013#define TRANS_HBLANK_START_SHIFT 0
3014#define _TRANS_HSYNC_A 0xe0008
3015#define TRANS_HSYNC_END_SHIFT 16
3016#define TRANS_HSYNC_START_SHIFT 0
3017#define _TRANS_VTOTAL_A 0xe000c
3018#define TRANS_VTOTAL_SHIFT 16
3019#define TRANS_VACTIVE_SHIFT 0
3020#define _TRANS_VBLANK_A 0xe0010
3021#define TRANS_VBLANK_END_SHIFT 16
3022#define TRANS_VBLANK_START_SHIFT 0
3023#define _TRANS_VSYNC_A 0xe0014
3024#define TRANS_VSYNC_END_SHIFT 16
3025#define TRANS_VSYNC_START_SHIFT 0
3026
3027#define _TRANSA_DATA_M1 0xe0030
3028#define _TRANSA_DATA_N1 0xe0034
3029#define _TRANSA_DATA_M2 0xe0038
3030#define _TRANSA_DATA_N2 0xe003c
3031#define _TRANSA_DP_LINK_M1 0xe0040
3032#define _TRANSA_DP_LINK_N1 0xe0044
3033#define _TRANSA_DP_LINK_M2 0xe0048
3034#define _TRANSA_DP_LINK_N2 0xe004c
3035
3036/* Per-transcoder DIP controls */
3037
3038#define _VIDEO_DIP_CTL_A 0xe0200
3039#define _VIDEO_DIP_DATA_A 0xe0208
3040#define _VIDEO_DIP_GCP_A 0xe0210
3041
3042#define _VIDEO_DIP_CTL_B 0xe1200
3043#define _VIDEO_DIP_DATA_B 0xe1208
3044#define _VIDEO_DIP_GCP_B 0xe1210
3045
3046#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
3047#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
3048#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
3049
3050#define _TRANS_HTOTAL_B 0xe1000
3051#define _TRANS_HBLANK_B 0xe1004
3052#define _TRANS_HSYNC_B 0xe1008
3053#define _TRANS_VTOTAL_B 0xe100c
3054#define _TRANS_VBLANK_B 0xe1010
3055#define _TRANS_VSYNC_B 0xe1014
3056
3057#define TRANS_HTOTAL(pipe) _PIPE(pipe, _TRANS_HTOTAL_A, _TRANS_HTOTAL_B)
3058#define TRANS_HBLANK(pipe) _PIPE(pipe, _TRANS_HBLANK_A, _TRANS_HBLANK_B)
3059#define TRANS_HSYNC(pipe) _PIPE(pipe, _TRANS_HSYNC_A, _TRANS_HSYNC_B)
3060#define TRANS_VTOTAL(pipe) _PIPE(pipe, _TRANS_VTOTAL_A, _TRANS_VTOTAL_B)
3061#define TRANS_VBLANK(pipe) _PIPE(pipe, _TRANS_VBLANK_A, _TRANS_VBLANK_B)
3062#define TRANS_VSYNC(pipe) _PIPE(pipe, _TRANS_VSYNC_A, _TRANS_VSYNC_B)
3063
3064#define _TRANSB_DATA_M1 0xe1030
3065#define _TRANSB_DATA_N1 0xe1034
3066#define _TRANSB_DATA_M2 0xe1038
3067#define _TRANSB_DATA_N2 0xe103c
3068#define _TRANSB_DP_LINK_M1 0xe1040
3069#define _TRANSB_DP_LINK_N1 0xe1044
3070#define _TRANSB_DP_LINK_M2 0xe1048
3071#define _TRANSB_DP_LINK_N2 0xe104c
3072
3073#define TRANSDATA_M1(pipe) _PIPE(pipe, _TRANSA_DATA_M1, _TRANSB_DATA_M1)
3074#define TRANSDATA_N1(pipe) _PIPE(pipe, _TRANSA_DATA_N1, _TRANSB_DATA_N1)
3075#define TRANSDATA_M2(pipe) _PIPE(pipe, _TRANSA_DATA_M2, _TRANSB_DATA_M2)
3076#define TRANSDATA_N2(pipe) _PIPE(pipe, _TRANSA_DATA_N2, _TRANSB_DATA_N2)
3077#define TRANSDPLINK_M1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M1, _TRANSB_DP_LINK_M1)
3078#define TRANSDPLINK_N1(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N1, _TRANSB_DP_LINK_N1)
3079#define TRANSDPLINK_M2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_M2, _TRANSB_DP_LINK_M2)
3080#define TRANSDPLINK_N2(pipe) _PIPE(pipe, _TRANSA_DP_LINK_N2, _TRANSB_DP_LINK_N2)
3081
3082#define _TRANSACONF 0xf0008
3083#define _TRANSBCONF 0xf1008
3084#define TRANSCONF(plane) _PIPE(plane, _TRANSACONF, _TRANSBCONF)
3085#define TRANS_DISABLE (0<<31)
3086#define TRANS_ENABLE (1<<31)
3087#define TRANS_STATE_MASK (1<<30)
3088#define TRANS_STATE_DISABLE (0<<30)
3089#define TRANS_STATE_ENABLE (1<<30)
3090#define TRANS_FSYNC_DELAY_HB1 (0<<27)
3091#define TRANS_FSYNC_DELAY_HB2 (1<<27)
3092#define TRANS_FSYNC_DELAY_HB3 (2<<27)
3093#define TRANS_FSYNC_DELAY_HB4 (3<<27)
3094#define TRANS_DP_AUDIO_ONLY (1<<26)
3095#define TRANS_DP_VIDEO_AUDIO (0<<26)
3096#define TRANS_PROGRESSIVE (0<<21)
3097#define TRANS_8BPC (0<<5)
3098#define TRANS_10BPC (1<<5)
3099#define TRANS_6BPC (2<<5)
3100#define TRANS_12BPC (3<<5)
3101
3102#define _TRANSA_CHICKEN2 0xf0064
3103#define _TRANSB_CHICKEN2 0xf1064
3104#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
3105#define TRANS_AUTOTRAIN_GEN_STALL_DIS (1<<31)
3106
3107#define SOUTH_CHICKEN1 0xc2000
3108#define FDIA_PHASE_SYNC_SHIFT_OVR 19
3109#define FDIA_PHASE_SYNC_SHIFT_EN 18
3110#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
3111#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
3112#define SOUTH_CHICKEN2 0xc2004
3113#define DPLS_EDP_PPS_FIX_DIS (1<<0)
3114
3115#define _FDI_RXA_CHICKEN 0xc200c
3116#define _FDI_RXB_CHICKEN 0xc2010
3117#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
3118#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
3119#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
3120
3121#define SOUTH_DSPCLK_GATE_D 0xc2020
3122#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
3123
3124/* CPU: FDI_TX */
3125#define _FDI_TXA_CTL 0x60100
3126#define _FDI_TXB_CTL 0x61100
3127#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
3128#define FDI_TX_DISABLE (0<<31)
3129#define FDI_TX_ENABLE (1<<31)
3130#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
3131#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
3132#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
3133#define FDI_LINK_TRAIN_NONE (3<<28)
3134#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
3135#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
3136#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
3137#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
3138#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
3139#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
3140#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
3141#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
3142/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
3143 SNB has different settings. */
3144/* SNB A-stepping */
3145#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3146#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3147#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3148#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3149/* SNB B-stepping */
3150#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
3151#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
3152#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
3153#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
3154#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
3155#define FDI_DP_PORT_WIDTH_X1 (0<<19)
3156#define FDI_DP_PORT_WIDTH_X2 (1<<19)
3157#define FDI_DP_PORT_WIDTH_X3 (2<<19)
3158#define FDI_DP_PORT_WIDTH_X4 (3<<19)
3159#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
3160/* Ironlake: hardwired to 1 */
3161#define FDI_TX_PLL_ENABLE (1<<14)
3162
3163/* Ivybridge has different bits for lolz */
3164#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
3165#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
3166#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
3167#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
3168
3169/* both Tx and Rx */
3170#define FDI_LINK_TRAIN_AUTO (1<<10)
3171#define FDI_SCRAMBLING_ENABLE (0<<7)
3172#define FDI_SCRAMBLING_DISABLE (1<<7)
3173
3174/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
3175#define _FDI_RXA_CTL 0xf000c
3176#define _FDI_RXB_CTL 0xf100c
3177#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
3178#define FDI_RX_ENABLE (1<<31)
3179/* train, dp width same as FDI_TX */
3180#define FDI_FS_ERRC_ENABLE (1<<27)
3181#define FDI_FE_ERRC_ENABLE (1<<26)
3182#define FDI_DP_PORT_WIDTH_X8 (7<<19)
3183#define FDI_8BPC (0<<16)
3184#define FDI_10BPC (1<<16)
3185#define FDI_6BPC (2<<16)
3186#define FDI_12BPC (3<<16)
3187#define FDI_LINK_REVERSE_OVERWRITE (1<<15)
3188#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
3189#define FDI_RX_PLL_ENABLE (1<<13)
3190#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
3191#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
3192#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
3193#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
3194#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
3195#define FDI_PCDCLK (1<<4)
3196/* CPT */
3197#define FDI_AUTO_TRAINING (1<<10)
3198#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
3199#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
3200#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
3201#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
3202#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
3203
3204#define _FDI_RXA_MISC 0xf0010
3205#define _FDI_RXB_MISC 0xf1010
3206#define _FDI_RXA_TUSIZE1 0xf0030
3207#define _FDI_RXA_TUSIZE2 0xf0038
3208#define _FDI_RXB_TUSIZE1 0xf1030
3209#define _FDI_RXB_TUSIZE2 0xf1038
3210#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
3211#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
3212#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
3213
3214/* FDI_RX interrupt register format */
3215#define FDI_RX_INTER_LANE_ALIGN (1<<10)
3216#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
3217#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
3218#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
3219#define FDI_RX_FS_CODE_ERR (1<<6)
3220#define FDI_RX_FE_CODE_ERR (1<<5)
3221#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
3222#define FDI_RX_HDCP_LINK_FAIL (1<<3)
3223#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
3224#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
3225#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
3226
3227#define _FDI_RXA_IIR 0xf0014
3228#define _FDI_RXA_IMR 0xf0018
3229#define _FDI_RXB_IIR 0xf1014
3230#define _FDI_RXB_IMR 0xf1018
3231#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
3232#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
3233
3234#define FDI_PLL_CTL_1 0xfe000
3235#define FDI_PLL_CTL_2 0xfe004
3236
3237/* CRT */
3238#define PCH_ADPA 0xe1100
3239#define ADPA_TRANS_SELECT_MASK (1<<30)
3240#define ADPA_TRANS_A_SELECT 0
3241#define ADPA_TRANS_B_SELECT (1<<30)
3242#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
3243#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
3244#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
3245#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
3246#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
3247#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
3248#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
3249#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
3250#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
3251#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
3252#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
3253#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
3254#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
3255#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
3256#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
3257#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
3258#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
3259#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
3260#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
3261
3262/* or SDVOB */
3263#define HDMIB 0xe1140
3264#define PORT_ENABLE (1 << 31)
3265#define TRANSCODER_A (0)
3266#define TRANSCODER_B (1 << 30)
3267#define TRANSCODER(pipe) ((pipe) << 30)
3268#define TRANSCODER_MASK (1 << 30)
3269#define COLOR_FORMAT_8bpc (0)
3270#define COLOR_FORMAT_12bpc (3 << 26)
3271#define SDVOB_HOTPLUG_ENABLE (1 << 23)
3272#define SDVO_ENCODING (0)
3273#define TMDS_ENCODING (2 << 10)
3274#define NULL_PACKET_VSYNC_ENABLE (1 << 9)
3275/* CPT */
3276#define HDMI_MODE_SELECT (1 << 9)
3277#define DVI_MODE_SELECT (0)
3278#define SDVOB_BORDER_ENABLE (1 << 7)
3279#define AUDIO_ENABLE (1 << 6)
3280#define VSYNC_ACTIVE_HIGH (1 << 4)
3281#define HSYNC_ACTIVE_HIGH (1 << 3)
3282#define PORT_DETECTED (1 << 2)
3283
3284/* PCH SDVOB multiplex with HDMIB */
3285#define PCH_SDVOB HDMIB
3286
3287#define HDMIC 0xe1150
3288#define HDMID 0xe1160
3289
3290#define PCH_LVDS 0xe1180
3291#define LVDS_DETECTED (1 << 1)
3292
3293#define BLC_PWM_CPU_CTL2 0x48250
3294#define PWM_ENABLE (1 << 31)
3295#define PWM_PIPE_A (0 << 29)
3296#define PWM_PIPE_B (1 << 29)
3297#define BLC_PWM_CPU_CTL 0x48254
3298
3299#define BLC_PWM_PCH_CTL1 0xc8250
3300#define PWM_PCH_ENABLE (1 << 31)
3301#define PWM_POLARITY_ACTIVE_LOW (1 << 29)
3302#define PWM_POLARITY_ACTIVE_HIGH (0 << 29)
3303#define PWM_POLARITY_ACTIVE_LOW2 (1 << 28)
3304#define PWM_POLARITY_ACTIVE_HIGH2 (0 << 28)
3305
3306#define BLC_PWM_PCH_CTL2 0xc8254
3307
3308#define PCH_PP_STATUS 0xc7200
3309#define PCH_PP_CONTROL 0xc7204
3310#define PANEL_UNLOCK_REGS (0xabcd << 16)
3311#define EDP_FORCE_VDD (1 << 3)
3312#define EDP_BLC_ENABLE (1 << 2)
3313#define PANEL_POWER_RESET (1 << 1)
3314#define PANEL_POWER_OFF (0 << 0)
3315#define PANEL_POWER_ON (1 << 0)
3316#define PCH_PP_ON_DELAYS 0xc7208
3317#define EDP_PANEL (1 << 30)
3318#define PCH_PP_OFF_DELAYS 0xc720c
3319#define PCH_PP_DIVISOR 0xc7210
3320
3321#define PCH_DP_B 0xe4100
3322#define PCH_DPB_AUX_CH_CTL 0xe4110
3323#define PCH_DPB_AUX_CH_DATA1 0xe4114
3324#define PCH_DPB_AUX_CH_DATA2 0xe4118
3325#define PCH_DPB_AUX_CH_DATA3 0xe411c
3326#define PCH_DPB_AUX_CH_DATA4 0xe4120
3327#define PCH_DPB_AUX_CH_DATA5 0xe4124
3328
3329#define PCH_DP_C 0xe4200
3330#define PCH_DPC_AUX_CH_CTL 0xe4210
3331#define PCH_DPC_AUX_CH_DATA1 0xe4214
3332#define PCH_DPC_AUX_CH_DATA2 0xe4218
3333#define PCH_DPC_AUX_CH_DATA3 0xe421c
3334#define PCH_DPC_AUX_CH_DATA4 0xe4220
3335#define PCH_DPC_AUX_CH_DATA5 0xe4224
3336
3337#define PCH_DP_D 0xe4300
3338#define PCH_DPD_AUX_CH_CTL 0xe4310
3339#define PCH_DPD_AUX_CH_DATA1 0xe4314
3340#define PCH_DPD_AUX_CH_DATA2 0xe4318
3341#define PCH_DPD_AUX_CH_DATA3 0xe431c
3342#define PCH_DPD_AUX_CH_DATA4 0xe4320
3343#define PCH_DPD_AUX_CH_DATA5 0xe4324
3344
3345/* CPT */
3346#define PORT_TRANS_A_SEL_CPT 0
3347#define PORT_TRANS_B_SEL_CPT (1<<29)
3348#define PORT_TRANS_C_SEL_CPT (2<<29)
3349#define PORT_TRANS_SEL_MASK (3<<29)
3350#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
3351
3352#define TRANS_DP_CTL_A 0xe0300
3353#define TRANS_DP_CTL_B 0xe1300
3354#define TRANS_DP_CTL_C 0xe2300
3355#define TRANS_DP_CTL(pipe) (TRANS_DP_CTL_A + (pipe) * 0x01000)
3356#define TRANS_DP_OUTPUT_ENABLE (1<<31)
3357#define TRANS_DP_PORT_SEL_B (0<<29)
3358#define TRANS_DP_PORT_SEL_C (1<<29)
3359#define TRANS_DP_PORT_SEL_D (2<<29)
3360#define TRANS_DP_PORT_SEL_NONE (3<<29)
3361#define TRANS_DP_PORT_SEL_MASK (3<<29)
3362#define TRANS_DP_AUDIO_ONLY (1<<26)
3363#define TRANS_DP_ENH_FRAMING (1<<18)
3364#define TRANS_DP_8BPC (0<<9)
3365#define TRANS_DP_10BPC (1<<9)
3366#define TRANS_DP_6BPC (2<<9)
3367#define TRANS_DP_12BPC (3<<9)
3368#define TRANS_DP_BPC_MASK (3<<9)
3369#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
3370#define TRANS_DP_VSYNC_ACTIVE_LOW 0
3371#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
3372#define TRANS_DP_HSYNC_ACTIVE_LOW 0
3373#define TRANS_DP_SYNC_MASK (3<<3)
3374
3375/* SNB eDP training params */
3376/* SNB A-stepping */
3377#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
3378#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
3379#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
3380#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
3381/* SNB B-stepping */
3382#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
3383#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
3384#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
3385#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
3386#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
3387#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
3388
3389#define FORCEWAKE 0xA18C
3390#define FORCEWAKE_ACK 0x130090
3391
3392#define GT_FIFO_FREE_ENTRIES 0x120008
3393#define GT_FIFO_NUM_RESERVED_ENTRIES 20
3394
3395#define GEN6_RPNSWREQ 0xA008
3396#define GEN6_TURBO_DISABLE (1<<31)
3397#define GEN6_FREQUENCY(x) ((x)<<25)
3398#define GEN6_OFFSET(x) ((x)<<19)
3399#define GEN6_AGGRESSIVE_TURBO (0<<15)
3400#define GEN6_RC_VIDEO_FREQ 0xA00C
3401#define GEN6_RC_CONTROL 0xA090
3402#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
3403#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
3404#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
3405#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
3406#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
3407#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
3408#define GEN6_RC_CTL_HW_ENABLE (1<<31)
3409#define GEN6_RP_DOWN_TIMEOUT 0xA010
3410#define GEN6_RP_INTERRUPT_LIMITS 0xA014
3411#define GEN6_RPSTAT1 0xA01C
3412#define GEN6_CAGF_SHIFT 8
3413#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
3414#define GEN6_RP_CONTROL 0xA024
3415#define GEN6_RP_MEDIA_TURBO (1<<11)
3416#define GEN6_RP_USE_NORMAL_FREQ (1<<9)
3417#define GEN6_RP_MEDIA_IS_GFX (1<<8)
3418#define GEN6_RP_ENABLE (1<<7)
3419#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
3420#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
3421#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
3422#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
3423#define GEN6_RP_UP_THRESHOLD 0xA02C
3424#define GEN6_RP_DOWN_THRESHOLD 0xA030
3425#define GEN6_RP_CUR_UP_EI 0xA050
3426#define GEN6_CURICONT_MASK 0xffffff
3427#define GEN6_RP_CUR_UP 0xA054
3428#define GEN6_CURBSYTAVG_MASK 0xffffff
3429#define GEN6_RP_PREV_UP 0xA058
3430#define GEN6_RP_CUR_DOWN_EI 0xA05C
3431#define GEN6_CURIAVG_MASK 0xffffff
3432#define GEN6_RP_CUR_DOWN 0xA060
3433#define GEN6_RP_PREV_DOWN 0xA064
3434#define GEN6_RP_UP_EI 0xA068
3435#define GEN6_RP_DOWN_EI 0xA06C
3436#define GEN6_RP_IDLE_HYSTERSIS 0xA070
3437#define GEN6_RC_STATE 0xA094
3438#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
3439#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
3440#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
3441#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
3442#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
3443#define GEN6_RC_SLEEP 0xA0B0
3444#define GEN6_RC1e_THRESHOLD 0xA0B4
3445#define GEN6_RC6_THRESHOLD 0xA0B8
3446#define GEN6_RC6p_THRESHOLD 0xA0BC
3447#define GEN6_RC6pp_THRESHOLD 0xA0C0
3448#define GEN6_PMINTRMSK 0xA168
3449
3450#define GEN6_PMISR 0x44020
3451#define GEN6_PMIMR 0x44024 /* rps_lock */
3452#define GEN6_PMIIR 0x44028
3453#define GEN6_PMIER 0x4402C
3454#define GEN6_PM_MBOX_EVENT (1<<25)
3455#define GEN6_PM_THERMAL_EVENT (1<<24)
3456#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
3457#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
3458#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
3459#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
3460#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
3461#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
3462 GEN6_PM_RP_DOWN_THRESHOLD | \
3463 GEN6_PM_RP_DOWN_TIMEOUT)
3464
3465#define GEN6_PCODE_MAILBOX 0x138124
3466#define GEN6_PCODE_READY (1<<31)
3467#define GEN6_READ_OC_PARAMS 0xc
3468#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
3469#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
3470#define GEN6_PCODE_DATA 0x138128
3471#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
3472
3473#endif /* _I915_REG_H_ */
1/* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
2 * All Rights Reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the
6 * "Software"), to deal in the Software without restriction, including
7 * without limitation the rights to use, copy, modify, merge, publish,
8 * distribute, sub license, and/or sell copies of the Software, and to
9 * permit persons to whom the Software is furnished to do so, subject to
10 * the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the
13 * next paragraph) shall be included in all copies or substantial portions
14 * of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
20 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef _I915_REG_H_
26#define _I915_REG_H_
27
28#define _PIPE(pipe, a, b) ((a) + (pipe)*((b)-(a)))
29#define _TRANSCODER(tran, a, b) ((a) + (tran)*((b)-(a)))
30
31#define _PORT(port, a, b) ((a) + (port)*((b)-(a)))
32
33#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
34#define _MASKED_BIT_DISABLE(a) ((a) << 16)
35
36/* PCI config space */
37
38#define HPLLCC 0xc0 /* 855 only */
39#define GC_CLOCK_CONTROL_MASK (0xf << 0)
40#define GC_CLOCK_133_200 (0 << 0)
41#define GC_CLOCK_100_200 (1 << 0)
42#define GC_CLOCK_100_133 (2 << 0)
43#define GC_CLOCK_166_250 (3 << 0)
44#define GCFGC2 0xda
45#define GCFGC 0xf0 /* 915+ only */
46#define GC_LOW_FREQUENCY_ENABLE (1 << 7)
47#define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
48#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4)
49#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
50#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
51#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
52#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
53#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
54#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
55#define GC_DISPLAY_CLOCK_MASK (7 << 4)
56#define GM45_GC_RENDER_CLOCK_MASK (0xf << 0)
57#define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
58#define GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
59#define GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
60#define GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
61#define I965_GC_RENDER_CLOCK_MASK (0xf << 0)
62#define I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
63#define I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
64#define I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
65#define I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
66#define I945_GC_RENDER_CLOCK_MASK (7 << 0)
67#define I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
68#define I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
69#define I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
70#define I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
71#define I915_GC_RENDER_CLOCK_MASK (7 << 0)
72#define I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
73#define I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
74#define I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
75#define PCI_LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
76
77
78/* Graphics reset regs */
79#define I965_GDRST 0xc0 /* PCI config register */
80#define ILK_GDSR 0x2ca4 /* MCHBAR offset */
81#define GRDOM_FULL (0<<2)
82#define GRDOM_RENDER (1<<2)
83#define GRDOM_MEDIA (3<<2)
84#define GRDOM_MASK (3<<2)
85#define GRDOM_RESET_ENABLE (1<<0)
86
87#define GEN6_MBCUNIT_SNPCR 0x900c /* for LLC config */
88#define GEN6_MBC_SNPCR_SHIFT 21
89#define GEN6_MBC_SNPCR_MASK (3<<21)
90#define GEN6_MBC_SNPCR_MAX (0<<21)
91#define GEN6_MBC_SNPCR_MED (1<<21)
92#define GEN6_MBC_SNPCR_LOW (2<<21)
93#define GEN6_MBC_SNPCR_MIN (3<<21) /* only 1/16th of the cache is shared */
94
95#define GEN6_MBCTL 0x0907c
96#define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4)
97#define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3)
98#define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2)
99#define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1)
100#define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0)
101
102#define GEN6_GDRST 0x941c
103#define GEN6_GRDOM_FULL (1 << 0)
104#define GEN6_GRDOM_RENDER (1 << 1)
105#define GEN6_GRDOM_MEDIA (1 << 2)
106#define GEN6_GRDOM_BLT (1 << 3)
107
108#define RING_PP_DIR_BASE(ring) ((ring)->mmio_base+0x228)
109#define RING_PP_DIR_BASE_READ(ring) ((ring)->mmio_base+0x518)
110#define RING_PP_DIR_DCLV(ring) ((ring)->mmio_base+0x220)
111#define PP_DIR_DCLV_2G 0xffffffff
112
113#define GEN8_RING_PDP_UDW(ring, n) ((ring)->mmio_base+0x270 + ((n) * 8 + 4))
114#define GEN8_RING_PDP_LDW(ring, n) ((ring)->mmio_base+0x270 + (n) * 8)
115
116#define GAM_ECOCHK 0x4090
117#define ECOCHK_SNB_BIT (1<<10)
118#define HSW_ECOCHK_ARB_PRIO_SOL (1<<6)
119#define ECOCHK_PPGTT_CACHE64B (0x3<<3)
120#define ECOCHK_PPGTT_CACHE4B (0x0<<3)
121#define ECOCHK_PPGTT_GFDT_IVB (0x1<<4)
122#define ECOCHK_PPGTT_LLC_IVB (0x1<<3)
123#define ECOCHK_PPGTT_UC_HSW (0x1<<3)
124#define ECOCHK_PPGTT_WT_HSW (0x2<<3)
125#define ECOCHK_PPGTT_WB_HSW (0x3<<3)
126
127#define GAC_ECO_BITS 0x14090
128#define ECOBITS_SNB_BIT (1<<13)
129#define ECOBITS_PPGTT_CACHE64B (3<<8)
130#define ECOBITS_PPGTT_CACHE4B (0<<8)
131
132#define GAB_CTL 0x24000
133#define GAB_CTL_CONT_AFTER_PAGEFAULT (1<<8)
134
135/* VGA stuff */
136
137#define VGA_ST01_MDA 0x3ba
138#define VGA_ST01_CGA 0x3da
139
140#define VGA_MSR_WRITE 0x3c2
141#define VGA_MSR_READ 0x3cc
142#define VGA_MSR_MEM_EN (1<<1)
143#define VGA_MSR_CGA_MODE (1<<0)
144
145#define VGA_SR_INDEX 0x3c4
146#define SR01 1
147#define VGA_SR_DATA 0x3c5
148
149#define VGA_AR_INDEX 0x3c0
150#define VGA_AR_VID_EN (1<<5)
151#define VGA_AR_DATA_WRITE 0x3c0
152#define VGA_AR_DATA_READ 0x3c1
153
154#define VGA_GR_INDEX 0x3ce
155#define VGA_GR_DATA 0x3cf
156/* GR05 */
157#define VGA_GR_MEM_READ_MODE_SHIFT 3
158#define VGA_GR_MEM_READ_MODE_PLANE 1
159/* GR06 */
160#define VGA_GR_MEM_MODE_MASK 0xc
161#define VGA_GR_MEM_MODE_SHIFT 2
162#define VGA_GR_MEM_A0000_AFFFF 0
163#define VGA_GR_MEM_A0000_BFFFF 1
164#define VGA_GR_MEM_B0000_B7FFF 2
165#define VGA_GR_MEM_B0000_BFFFF 3
166
167#define VGA_DACMASK 0x3c6
168#define VGA_DACRX 0x3c7
169#define VGA_DACWX 0x3c8
170#define VGA_DACDATA 0x3c9
171
172#define VGA_CR_INDEX_MDA 0x3b4
173#define VGA_CR_DATA_MDA 0x3b5
174#define VGA_CR_INDEX_CGA 0x3d4
175#define VGA_CR_DATA_CGA 0x3d5
176
177/*
178 * Instruction field definitions used by the command parser
179 */
180#define INSTR_CLIENT_SHIFT 29
181#define INSTR_CLIENT_MASK 0xE0000000
182#define INSTR_MI_CLIENT 0x0
183#define INSTR_BC_CLIENT 0x2
184#define INSTR_RC_CLIENT 0x3
185#define INSTR_SUBCLIENT_SHIFT 27
186#define INSTR_SUBCLIENT_MASK 0x18000000
187#define INSTR_MEDIA_SUBCLIENT 0x2
188
189/*
190 * Memory interface instructions used by the kernel
191 */
192#define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags))
193
194#define MI_NOOP MI_INSTR(0, 0)
195#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
196#define MI_WAIT_FOR_EVENT MI_INSTR(0x03, 0)
197#define MI_WAIT_FOR_OVERLAY_FLIP (1<<16)
198#define MI_WAIT_FOR_PLANE_B_FLIP (1<<6)
199#define MI_WAIT_FOR_PLANE_A_FLIP (1<<2)
200#define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1)
201#define MI_FLUSH MI_INSTR(0x04, 0)
202#define MI_READ_FLUSH (1 << 0)
203#define MI_EXE_FLUSH (1 << 1)
204#define MI_NO_WRITE_FLUSH (1 << 2)
205#define MI_SCENE_COUNT (1 << 3) /* just increment scene count */
206#define MI_END_SCENE (1 << 4) /* flush binner and incr scene count */
207#define MI_INVALIDATE_ISP (1 << 5) /* invalidate indirect state pointers */
208#define MI_REPORT_HEAD MI_INSTR(0x07, 0)
209#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
210#define MI_ARB_ENABLE (1<<0)
211#define MI_ARB_DISABLE (0<<0)
212#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
213#define MI_SUSPEND_FLUSH MI_INSTR(0x0b, 0)
214#define MI_SUSPEND_FLUSH_EN (1<<0)
215#define MI_OVERLAY_FLIP MI_INSTR(0x11, 0)
216#define MI_OVERLAY_CONTINUE (0x0<<21)
217#define MI_OVERLAY_ON (0x1<<21)
218#define MI_OVERLAY_OFF (0x2<<21)
219#define MI_LOAD_SCAN_LINES_INCL MI_INSTR(0x12, 0)
220#define MI_DISPLAY_FLIP MI_INSTR(0x14, 2)
221#define MI_DISPLAY_FLIP_I915 MI_INSTR(0x14, 1)
222#define MI_DISPLAY_FLIP_PLANE(n) ((n) << 20)
223/* IVB has funny definitions for which plane to flip. */
224#define MI_DISPLAY_FLIP_IVB_PLANE_A (0 << 19)
225#define MI_DISPLAY_FLIP_IVB_PLANE_B (1 << 19)
226#define MI_DISPLAY_FLIP_IVB_SPRITE_A (2 << 19)
227#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
228#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
229#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
230#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6+ */
231#define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
232#define MI_SEMAPHORE_UPDATE (1<<21)
233#define MI_SEMAPHORE_COMPARE (1<<20)
234#define MI_SEMAPHORE_REGISTER (1<<18)
235#define MI_SEMAPHORE_SYNC_VR (0<<16) /* RCS wait for VCS (RVSYNC) */
236#define MI_SEMAPHORE_SYNC_VER (1<<16) /* RCS wait for VECS (RVESYNC) */
237#define MI_SEMAPHORE_SYNC_BR (2<<16) /* RCS wait for BCS (RBSYNC) */
238#define MI_SEMAPHORE_SYNC_BV (0<<16) /* VCS wait for BCS (VBSYNC) */
239#define MI_SEMAPHORE_SYNC_VEV (1<<16) /* VCS wait for VECS (VVESYNC) */
240#define MI_SEMAPHORE_SYNC_RV (2<<16) /* VCS wait for RCS (VRSYNC) */
241#define MI_SEMAPHORE_SYNC_RB (0<<16) /* BCS wait for RCS (BRSYNC) */
242#define MI_SEMAPHORE_SYNC_VEB (1<<16) /* BCS wait for VECS (BVESYNC) */
243#define MI_SEMAPHORE_SYNC_VB (2<<16) /* BCS wait for VCS (BVSYNC) */
244#define MI_SEMAPHORE_SYNC_BVE (0<<16) /* VECS wait for BCS (VEBSYNC) */
245#define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
246#define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
247#define MI_SEMAPHORE_SYNC_INVALID (3<<16)
248#define MI_SET_CONTEXT MI_INSTR(0x18, 0)
249#define MI_MM_SPACE_GTT (1<<8)
250#define MI_MM_SPACE_PHYSICAL (0<<8)
251#define MI_SAVE_EXT_STATE_EN (1<<3)
252#define MI_RESTORE_EXT_STATE_EN (1<<2)
253#define MI_FORCE_RESTORE (1<<1)
254#define MI_RESTORE_INHIBIT (1<<0)
255#define MI_STORE_DWORD_IMM MI_INSTR(0x20, 1)
256#define MI_MEM_VIRTUAL (1 << 22) /* 965+ only */
257#define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1)
258#define MI_STORE_DWORD_INDEX_SHIFT 2
259/* Official intel docs are somewhat sloppy concerning MI_LOAD_REGISTER_IMM:
260 * - Always issue a MI_NOOP _before_ the MI_LOAD_REGISTER_IMM - otherwise hw
261 * simply ignores the register load under certain conditions.
262 * - One can actually load arbitrary many arbitrary registers: Simply issue x
263 * address/value pairs. Don't overdue it, though, x <= 2^4 must hold!
264 */
265#define MI_LOAD_REGISTER_IMM(x) MI_INSTR(0x22, 2*x-1)
266#define MI_STORE_REGISTER_MEM(x) MI_INSTR(0x24, 2*x-1)
267#define MI_SRM_LRM_GLOBAL_GTT (1<<22)
268#define MI_FLUSH_DW MI_INSTR(0x26, 1) /* for GEN6 */
269#define MI_FLUSH_DW_STORE_INDEX (1<<21)
270#define MI_INVALIDATE_TLB (1<<18)
271#define MI_FLUSH_DW_OP_STOREDW (1<<14)
272#define MI_INVALIDATE_BSD (1<<7)
273#define MI_FLUSH_DW_USE_GTT (1<<2)
274#define MI_FLUSH_DW_USE_PPGTT (0<<2)
275#define MI_BATCH_BUFFER MI_INSTR(0x30, 1)
276#define MI_BATCH_NON_SECURE (1)
277/* for snb/ivb/vlv this also means "batch in ppgtt" when ppgtt is enabled. */
278#define MI_BATCH_NON_SECURE_I965 (1<<8)
279#define MI_BATCH_PPGTT_HSW (1<<8)
280#define MI_BATCH_NON_SECURE_HSW (1<<13)
281#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 0)
282#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
283#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
284
285
286#define MI_PREDICATE_RESULT_2 (0x2214)
287#define LOWER_SLICE_ENABLED (1<<0)
288#define LOWER_SLICE_DISABLED (0<<0)
289
290/*
291 * 3D instructions used by the kernel
292 */
293#define GFX_INSTR(opcode, flags) ((0x3 << 29) | ((opcode) << 24) | (flags))
294
295#define GFX_OP_RASTER_RULES ((0x3<<29)|(0x7<<24))
296#define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
297#define SC_UPDATE_SCISSOR (0x1<<1)
298#define SC_ENABLE_MASK (0x1<<0)
299#define SC_ENABLE (0x1<<0)
300#define GFX_OP_LOAD_INDIRECT ((0x3<<29)|(0x1d<<24)|(0x7<<16))
301#define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
302#define SCI_YMIN_MASK (0xffff<<16)
303#define SCI_XMIN_MASK (0xffff<<0)
304#define SCI_YMAX_MASK (0xffff<<16)
305#define SCI_XMAX_MASK (0xffff<<0)
306#define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19))
307#define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1)
308#define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
309#define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
310#define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4)
311#define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
312#define GFX_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1)
313#define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
314#define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2)
315#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4)
316#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
317#define XY_MONO_SRC_COPY_IMM_BLT ((2<<29)|(0x71<<22)|5)
318#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
319#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
320#define BLT_DEPTH_8 (0<<24)
321#define BLT_DEPTH_16_565 (1<<24)
322#define BLT_DEPTH_16_1555 (2<<24)
323#define BLT_DEPTH_32 (3<<24)
324#define BLT_ROP_GXCOPY (0xcc<<16)
325#define XY_SRC_COPY_BLT_SRC_TILED (1<<15) /* 965+ only */
326#define XY_SRC_COPY_BLT_DST_TILED (1<<11) /* 965+ only */
327#define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2)
328#define ASYNC_FLIP (1<<22)
329#define DISPLAY_PLANE_A (0<<20)
330#define DISPLAY_PLANE_B (1<<20)
331#define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|(len-2))
332#define PIPE_CONTROL_GLOBAL_GTT_IVB (1<<24) /* gen7+ */
333#define PIPE_CONTROL_CS_STALL (1<<20)
334#define PIPE_CONTROL_TLB_INVALIDATE (1<<18)
335#define PIPE_CONTROL_QW_WRITE (1<<14)
336#define PIPE_CONTROL_DEPTH_STALL (1<<13)
337#define PIPE_CONTROL_WRITE_FLUSH (1<<12)
338#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
339#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on Ironlake */
340#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
341#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
342#define PIPE_CONTROL_NOTIFY (1<<8)
343#define PIPE_CONTROL_VF_CACHE_INVALIDATE (1<<4)
344#define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3)
345#define PIPE_CONTROL_STATE_CACHE_INVALIDATE (1<<2)
346#define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
347#define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
348#define PIPE_CONTROL_GLOBAL_GTT (1<<2) /* in addr dword */
349
350
351/*
352 * Reset registers
353 */
354#define DEBUG_RESET_I830 0x6070
355#define DEBUG_RESET_FULL (1<<7)
356#define DEBUG_RESET_RENDER (1<<8)
357#define DEBUG_RESET_DISPLAY (1<<9)
358
359/*
360 * IOSF sideband
361 */
362#define VLV_IOSF_DOORBELL_REQ (VLV_DISPLAY_BASE + 0x2100)
363#define IOSF_DEVFN_SHIFT 24
364#define IOSF_OPCODE_SHIFT 16
365#define IOSF_PORT_SHIFT 8
366#define IOSF_BYTE_ENABLES_SHIFT 4
367#define IOSF_BAR_SHIFT 1
368#define IOSF_SB_BUSY (1<<0)
369#define IOSF_PORT_BUNIT 0x3
370#define IOSF_PORT_PUNIT 0x4
371#define IOSF_PORT_NC 0x11
372#define IOSF_PORT_DPIO 0x12
373#define IOSF_PORT_GPIO_NC 0x13
374#define IOSF_PORT_CCK 0x14
375#define IOSF_PORT_CCU 0xA9
376#define IOSF_PORT_GPS_CORE 0x48
377#define IOSF_PORT_FLISDSI 0x1B
378#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
379#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
380
381/* See configdb bunit SB addr map */
382#define BUNIT_REG_BISOC 0x11
383
384#define PUNIT_OPCODE_REG_READ 6
385#define PUNIT_OPCODE_REG_WRITE 7
386
387#define PUNIT_REG_DSPFREQ 0x36
388#define DSPFREQSTAT_SHIFT 30
389#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
390#define DSPFREQGUAR_SHIFT 14
391#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
392
393/* See the PUNIT HAS v0.8 for the below bits */
394enum punit_power_well {
395 PUNIT_POWER_WELL_RENDER = 0,
396 PUNIT_POWER_WELL_MEDIA = 1,
397 PUNIT_POWER_WELL_DISP2D = 3,
398 PUNIT_POWER_WELL_DPIO_CMN_BC = 5,
399 PUNIT_POWER_WELL_DPIO_TX_B_LANES_01 = 6,
400 PUNIT_POWER_WELL_DPIO_TX_B_LANES_23 = 7,
401 PUNIT_POWER_WELL_DPIO_TX_C_LANES_01 = 8,
402 PUNIT_POWER_WELL_DPIO_TX_C_LANES_23 = 9,
403 PUNIT_POWER_WELL_DPIO_RX0 = 10,
404 PUNIT_POWER_WELL_DPIO_RX1 = 11,
405
406 PUNIT_POWER_WELL_NUM,
407};
408
409#define PUNIT_REG_PWRGT_CTRL 0x60
410#define PUNIT_REG_PWRGT_STATUS 0x61
411#define PUNIT_PWRGT_MASK(power_well) (3 << ((power_well) * 2))
412#define PUNIT_PWRGT_PWR_ON(power_well) (0 << ((power_well) * 2))
413#define PUNIT_PWRGT_CLK_GATE(power_well) (1 << ((power_well) * 2))
414#define PUNIT_PWRGT_RESET(power_well) (2 << ((power_well) * 2))
415#define PUNIT_PWRGT_PWR_GATE(power_well) (3 << ((power_well) * 2))
416
417#define PUNIT_REG_GPU_LFM 0xd3
418#define PUNIT_REG_GPU_FREQ_REQ 0xd4
419#define PUNIT_REG_GPU_FREQ_STS 0xd8
420#define GENFREQSTATUS (1<<0)
421#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
422
423#define PUNIT_FUSE_BUS2 0xf6 /* bits 47:40 */
424#define PUNIT_FUSE_BUS1 0xf5 /* bits 55:48 */
425
426#define IOSF_NC_FB_GFX_FREQ_FUSE 0x1c
427#define FB_GFX_MAX_FREQ_FUSE_SHIFT 3
428#define FB_GFX_MAX_FREQ_FUSE_MASK 0x000007f8
429#define FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT 11
430#define FB_GFX_FGUARANTEED_FREQ_FUSE_MASK 0x0007f800
431#define IOSF_NC_FB_GFX_FMAX_FUSE_HI 0x34
432#define FB_FMAX_VMIN_FREQ_HI_MASK 0x00000007
433#define IOSF_NC_FB_GFX_FMAX_FUSE_LO 0x30
434#define FB_FMAX_VMIN_FREQ_LO_SHIFT 27
435#define FB_FMAX_VMIN_FREQ_LO_MASK 0xf8000000
436
437/* vlv2 north clock has */
438#define CCK_FUSE_REG 0x8
439#define CCK_FUSE_HPLL_FREQ_MASK 0x3
440#define CCK_REG_DSI_PLL_FUSE 0x44
441#define CCK_REG_DSI_PLL_CONTROL 0x48
442#define DSI_PLL_VCO_EN (1 << 31)
443#define DSI_PLL_LDO_GATE (1 << 30)
444#define DSI_PLL_P1_POST_DIV_SHIFT 17
445#define DSI_PLL_P1_POST_DIV_MASK (0x1ff << 17)
446#define DSI_PLL_P2_MUX_DSI0_DIV2 (1 << 13)
447#define DSI_PLL_P3_MUX_DSI1_DIV2 (1 << 12)
448#define DSI_PLL_MUX_MASK (3 << 9)
449#define DSI_PLL_MUX_DSI0_DSIPLL (0 << 10)
450#define DSI_PLL_MUX_DSI0_CCK (1 << 10)
451#define DSI_PLL_MUX_DSI1_DSIPLL (0 << 9)
452#define DSI_PLL_MUX_DSI1_CCK (1 << 9)
453#define DSI_PLL_CLK_GATE_MASK (0xf << 5)
454#define DSI_PLL_CLK_GATE_DSI0_DSIPLL (1 << 8)
455#define DSI_PLL_CLK_GATE_DSI1_DSIPLL (1 << 7)
456#define DSI_PLL_CLK_GATE_DSI0_CCK (1 << 6)
457#define DSI_PLL_CLK_GATE_DSI1_CCK (1 << 5)
458#define DSI_PLL_LOCK (1 << 0)
459#define CCK_REG_DSI_PLL_DIVIDER 0x4c
460#define DSI_PLL_LFSR (1 << 31)
461#define DSI_PLL_FRACTION_EN (1 << 30)
462#define DSI_PLL_FRAC_COUNTER_SHIFT 27
463#define DSI_PLL_FRAC_COUNTER_MASK (7 << 27)
464#define DSI_PLL_USYNC_CNT_SHIFT 18
465#define DSI_PLL_USYNC_CNT_MASK (0x1ff << 18)
466#define DSI_PLL_N1_DIV_SHIFT 16
467#define DSI_PLL_N1_DIV_MASK (3 << 16)
468#define DSI_PLL_M1_DIV_SHIFT 0
469#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
470#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
471
472/*
473 * DPIO - a special bus for various display related registers to hide behind
474 *
475 * DPIO is VLV only.
476 *
477 * Note: digital port B is DDI0, digital pot C is DDI1
478 */
479#define DPIO_DEVFN 0
480#define DPIO_OPCODE_REG_WRITE 1
481#define DPIO_OPCODE_REG_READ 0
482
483#define DPIO_CTL (VLV_DISPLAY_BASE + 0x2110)
484#define DPIO_MODSEL1 (1<<3) /* if ref clk b == 27 */
485#define DPIO_MODSEL0 (1<<2) /* if ref clk a == 27 */
486#define DPIO_SFR_BYPASS (1<<1)
487#define DPIO_CMNRST (1<<0)
488
489#define DPIO_PHY(pipe) ((pipe) >> 1)
490#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
491
492/*
493 * Per pipe/PLL DPIO regs
494 */
495#define _VLV_PLL_DW3_CH0 0x800c
496#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
497#define DPIO_POST_DIV_DAC 0
498#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
499#define DPIO_POST_DIV_LVDS1 2
500#define DPIO_POST_DIV_LVDS2 3
501#define DPIO_K_SHIFT (24) /* 4 bits */
502#define DPIO_P1_SHIFT (21) /* 3 bits */
503#define DPIO_P2_SHIFT (16) /* 5 bits */
504#define DPIO_N_SHIFT (12) /* 4 bits */
505#define DPIO_ENABLE_CALIBRATION (1<<11)
506#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
507#define DPIO_M2DIV_MASK 0xff
508#define _VLV_PLL_DW3_CH1 0x802c
509#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
510
511#define _VLV_PLL_DW5_CH0 0x8014
512#define DPIO_REFSEL_OVERRIDE 27
513#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
514#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
515#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */
516#define DPIO_PLL_REFCLK_SEL_MASK 3
517#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
518#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
519#define _VLV_PLL_DW5_CH1 0x8034
520#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
521
522#define _VLV_PLL_DW7_CH0 0x801c
523#define _VLV_PLL_DW7_CH1 0x803c
524#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
525
526#define _VLV_PLL_DW8_CH0 0x8040
527#define _VLV_PLL_DW8_CH1 0x8060
528#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
529
530#define VLV_PLL_DW9_BCAST 0xc044
531#define _VLV_PLL_DW9_CH0 0x8044
532#define _VLV_PLL_DW9_CH1 0x8064
533#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
534
535#define _VLV_PLL_DW10_CH0 0x8048
536#define _VLV_PLL_DW10_CH1 0x8068
537#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
538
539#define _VLV_PLL_DW11_CH0 0x804c
540#define _VLV_PLL_DW11_CH1 0x806c
541#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
542
543/* Spec for ref block start counts at DW10 */
544#define VLV_REF_DW13 0x80ac
545
546#define VLV_CMN_DW0 0x8100
547
548/*
549 * Per DDI channel DPIO regs
550 */
551
552#define _VLV_PCS_DW0_CH0 0x8200
553#define _VLV_PCS_DW0_CH1 0x8400
554#define DPIO_PCS_TX_LANE2_RESET (1<<16)
555#define DPIO_PCS_TX_LANE1_RESET (1<<7)
556#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
557
558#define _VLV_PCS_DW1_CH0 0x8204
559#define _VLV_PCS_DW1_CH1 0x8404
560#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
561#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
562#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
563#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
564#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
565
566#define _VLV_PCS_DW8_CH0 0x8220
567#define _VLV_PCS_DW8_CH1 0x8420
568#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
569
570#define _VLV_PCS01_DW8_CH0 0x0220
571#define _VLV_PCS23_DW8_CH0 0x0420
572#define _VLV_PCS01_DW8_CH1 0x2620
573#define _VLV_PCS23_DW8_CH1 0x2820
574#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
575#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
576
577#define _VLV_PCS_DW9_CH0 0x8224
578#define _VLV_PCS_DW9_CH1 0x8424
579#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
580
581#define _VLV_PCS_DW11_CH0 0x822c
582#define _VLV_PCS_DW11_CH1 0x842c
583#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
584
585#define _VLV_PCS_DW12_CH0 0x8230
586#define _VLV_PCS_DW12_CH1 0x8430
587#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
588
589#define _VLV_PCS_DW14_CH0 0x8238
590#define _VLV_PCS_DW14_CH1 0x8438
591#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
592
593#define _VLV_PCS_DW23_CH0 0x825c
594#define _VLV_PCS_DW23_CH1 0x845c
595#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
596
597#define _VLV_TX_DW2_CH0 0x8288
598#define _VLV_TX_DW2_CH1 0x8488
599#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
600
601#define _VLV_TX_DW3_CH0 0x828c
602#define _VLV_TX_DW3_CH1 0x848c
603#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
604
605#define _VLV_TX_DW4_CH0 0x8290
606#define _VLV_TX_DW4_CH1 0x8490
607#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
608
609#define _VLV_TX3_DW4_CH0 0x690
610#define _VLV_TX3_DW4_CH1 0x2a90
611#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
612
613#define _VLV_TX_DW5_CH0 0x8294
614#define _VLV_TX_DW5_CH1 0x8494
615#define DPIO_TX_OCALINIT_EN (1<<31)
616#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
617
618#define _VLV_TX_DW11_CH0 0x82ac
619#define _VLV_TX_DW11_CH1 0x84ac
620#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
621
622#define _VLV_TX_DW14_CH0 0x82b8
623#define _VLV_TX_DW14_CH1 0x84b8
624#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
625
626/*
627 * Fence registers
628 */
629#define FENCE_REG_830_0 0x2000
630#define FENCE_REG_945_8 0x3000
631#define I830_FENCE_START_MASK 0x07f80000
632#define I830_FENCE_TILING_Y_SHIFT 12
633#define I830_FENCE_SIZE_BITS(size) ((ffs((size) >> 19) - 1) << 8)
634#define I830_FENCE_PITCH_SHIFT 4
635#define I830_FENCE_REG_VALID (1<<0)
636#define I915_FENCE_MAX_PITCH_VAL 4
637#define I830_FENCE_MAX_PITCH_VAL 6
638#define I830_FENCE_MAX_SIZE_VAL (1<<8)
639
640#define I915_FENCE_START_MASK 0x0ff00000
641#define I915_FENCE_SIZE_BITS(size) ((ffs((size) >> 20) - 1) << 8)
642
643#define FENCE_REG_965_0 0x03000
644#define I965_FENCE_PITCH_SHIFT 2
645#define I965_FENCE_TILING_Y_SHIFT 1
646#define I965_FENCE_REG_VALID (1<<0)
647#define I965_FENCE_MAX_PITCH_VAL 0x0400
648
649#define FENCE_REG_SANDYBRIDGE_0 0x100000
650#define SANDYBRIDGE_FENCE_PITCH_SHIFT 32
651#define GEN7_FENCE_MAX_PITCH_VAL 0x0800
652
653/* control register for cpu gtt access */
654#define TILECTL 0x101000
655#define TILECTL_SWZCTL (1 << 0)
656#define TILECTL_TLB_PREFETCH_DIS (1 << 2)
657#define TILECTL_BACKSNOOP_DIS (1 << 3)
658
659/*
660 * Instruction and interrupt control regs
661 */
662#define PGTBL_ER 0x02024
663#define RENDER_RING_BASE 0x02000
664#define BSD_RING_BASE 0x04000
665#define GEN6_BSD_RING_BASE 0x12000
666#define VEBOX_RING_BASE 0x1a000
667#define BLT_RING_BASE 0x22000
668#define RING_TAIL(base) ((base)+0x30)
669#define RING_HEAD(base) ((base)+0x34)
670#define RING_START(base) ((base)+0x38)
671#define RING_CTL(base) ((base)+0x3c)
672#define RING_SYNC_0(base) ((base)+0x40)
673#define RING_SYNC_1(base) ((base)+0x44)
674#define RING_SYNC_2(base) ((base)+0x48)
675#define GEN6_RVSYNC (RING_SYNC_0(RENDER_RING_BASE))
676#define GEN6_RBSYNC (RING_SYNC_1(RENDER_RING_BASE))
677#define GEN6_RVESYNC (RING_SYNC_2(RENDER_RING_BASE))
678#define GEN6_VBSYNC (RING_SYNC_0(GEN6_BSD_RING_BASE))
679#define GEN6_VRSYNC (RING_SYNC_1(GEN6_BSD_RING_BASE))
680#define GEN6_VVESYNC (RING_SYNC_2(GEN6_BSD_RING_BASE))
681#define GEN6_BRSYNC (RING_SYNC_0(BLT_RING_BASE))
682#define GEN6_BVSYNC (RING_SYNC_1(BLT_RING_BASE))
683#define GEN6_BVESYNC (RING_SYNC_2(BLT_RING_BASE))
684#define GEN6_VEBSYNC (RING_SYNC_0(VEBOX_RING_BASE))
685#define GEN6_VERSYNC (RING_SYNC_1(VEBOX_RING_BASE))
686#define GEN6_VEVSYNC (RING_SYNC_2(VEBOX_RING_BASE))
687#define GEN6_NOSYNC 0
688#define RING_MAX_IDLE(base) ((base)+0x54)
689#define RING_HWS_PGA(base) ((base)+0x80)
690#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
691#define ARB_MODE 0x04030
692#define ARB_MODE_SWIZZLE_SNB (1<<4)
693#define ARB_MODE_SWIZZLE_IVB (1<<5)
694#define GAMTARBMODE 0x04a08
695#define ARB_MODE_BWGTLB_DISABLE (1<<9)
696#define ARB_MODE_SWIZZLE_BDW (1<<1)
697#define RENDER_HWS_PGA_GEN7 (0x04080)
698#define RING_FAULT_REG(ring) (0x4094 + 0x100*(ring)->id)
699#define RING_FAULT_GTTSEL_MASK (1<<11)
700#define RING_FAULT_SRCID(x) ((x >> 3) & 0xff)
701#define RING_FAULT_FAULT_TYPE(x) ((x >> 1) & 0x3)
702#define RING_FAULT_VALID (1<<0)
703#define DONE_REG 0x40b0
704#define GEN8_PRIVATE_PAT 0x40e0
705#define BSD_HWS_PGA_GEN7 (0x04180)
706#define BLT_HWS_PGA_GEN7 (0x04280)
707#define VEBOX_HWS_PGA_GEN7 (0x04380)
708#define RING_ACTHD(base) ((base)+0x74)
709#define RING_ACTHD_UDW(base) ((base)+0x5c)
710#define RING_NOPID(base) ((base)+0x94)
711#define RING_IMR(base) ((base)+0xa8)
712#define RING_TIMESTAMP(base) ((base)+0x358)
713#define TAIL_ADDR 0x001FFFF8
714#define HEAD_WRAP_COUNT 0xFFE00000
715#define HEAD_WRAP_ONE 0x00200000
716#define HEAD_ADDR 0x001FFFFC
717#define RING_NR_PAGES 0x001FF000
718#define RING_REPORT_MASK 0x00000006
719#define RING_REPORT_64K 0x00000002
720#define RING_REPORT_128K 0x00000004
721#define RING_NO_REPORT 0x00000000
722#define RING_VALID_MASK 0x00000001
723#define RING_VALID 0x00000001
724#define RING_INVALID 0x00000000
725#define RING_WAIT_I8XX (1<<0) /* gen2, PRBx_HEAD */
726#define RING_WAIT (1<<11) /* gen3+, PRBx_CTL */
727#define RING_WAIT_SEMAPHORE (1<<10) /* gen6+ */
728#if 0
729#define PRB0_TAIL 0x02030
730#define PRB0_HEAD 0x02034
731#define PRB0_START 0x02038
732#define PRB0_CTL 0x0203c
733#define PRB1_TAIL 0x02040 /* 915+ only */
734#define PRB1_HEAD 0x02044 /* 915+ only */
735#define PRB1_START 0x02048 /* 915+ only */
736#define PRB1_CTL 0x0204c /* 915+ only */
737#endif
738#define IPEIR_I965 0x02064
739#define IPEHR_I965 0x02068
740#define INSTDONE_I965 0x0206c
741#define GEN7_INSTDONE_1 0x0206c
742#define GEN7_SC_INSTDONE 0x07100
743#define GEN7_SAMPLER_INSTDONE 0x0e160
744#define GEN7_ROW_INSTDONE 0x0e164
745#define I915_NUM_INSTDONE_REG 4
746#define RING_IPEIR(base) ((base)+0x64)
747#define RING_IPEHR(base) ((base)+0x68)
748#define RING_INSTDONE(base) ((base)+0x6c)
749#define RING_INSTPS(base) ((base)+0x70)
750#define RING_DMA_FADD(base) ((base)+0x78)
751#define RING_INSTPM(base) ((base)+0xc0)
752#define RING_MI_MODE(base) ((base)+0x9c)
753#define INSTPS 0x02070 /* 965+ only */
754#define INSTDONE1 0x0207c /* 965+ only */
755#define ACTHD_I965 0x02074
756#define HWS_PGA 0x02080
757#define HWS_ADDRESS_MASK 0xfffff000
758#define HWS_START_ADDRESS_SHIFT 4
759#define PWRCTXA 0x2088 /* 965GM+ only */
760#define PWRCTX_EN (1<<0)
761#define IPEIR 0x02088
762#define IPEHR 0x0208c
763#define INSTDONE 0x02090
764#define NOPID 0x02094
765#define HWSTAM 0x02098
766#define DMA_FADD_I8XX 0x020d0
767#define RING_BBSTATE(base) ((base)+0x110)
768#define RING_BBADDR(base) ((base)+0x140)
769#define RING_BBADDR_UDW(base) ((base)+0x168) /* gen8+ */
770
771#define ERROR_GEN6 0x040a0
772#define GEN7_ERR_INT 0x44040
773#define ERR_INT_POISON (1<<31)
774#define ERR_INT_MMIO_UNCLAIMED (1<<13)
775#define ERR_INT_PIPE_CRC_DONE_C (1<<8)
776#define ERR_INT_FIFO_UNDERRUN_C (1<<6)
777#define ERR_INT_PIPE_CRC_DONE_B (1<<5)
778#define ERR_INT_FIFO_UNDERRUN_B (1<<3)
779#define ERR_INT_PIPE_CRC_DONE_A (1<<2)
780#define ERR_INT_PIPE_CRC_DONE(pipe) (1<<(2 + pipe*3))
781#define ERR_INT_FIFO_UNDERRUN_A (1<<0)
782#define ERR_INT_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
783
784#define FPGA_DBG 0x42300
785#define FPGA_DBG_RM_NOCLAIM (1<<31)
786
787#define DERRMR 0x44050
788/* Note that HBLANK events are reserved on bdw+ */
789#define DERRMR_PIPEA_SCANLINE (1<<0)
790#define DERRMR_PIPEA_PRI_FLIP_DONE (1<<1)
791#define DERRMR_PIPEA_SPR_FLIP_DONE (1<<2)
792#define DERRMR_PIPEA_VBLANK (1<<3)
793#define DERRMR_PIPEA_HBLANK (1<<5)
794#define DERRMR_PIPEB_SCANLINE (1<<8)
795#define DERRMR_PIPEB_PRI_FLIP_DONE (1<<9)
796#define DERRMR_PIPEB_SPR_FLIP_DONE (1<<10)
797#define DERRMR_PIPEB_VBLANK (1<<11)
798#define DERRMR_PIPEB_HBLANK (1<<13)
799/* Note that PIPEC is not a simple translation of PIPEA/PIPEB */
800#define DERRMR_PIPEC_SCANLINE (1<<14)
801#define DERRMR_PIPEC_PRI_FLIP_DONE (1<<15)
802#define DERRMR_PIPEC_SPR_FLIP_DONE (1<<20)
803#define DERRMR_PIPEC_VBLANK (1<<21)
804#define DERRMR_PIPEC_HBLANK (1<<22)
805
806
807/* GM45+ chicken bits -- debug workaround bits that may be required
808 * for various sorts of correct behavior. The top 16 bits of each are
809 * the enables for writing to the corresponding low bit.
810 */
811#define _3D_CHICKEN 0x02084
812#define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10)
813#define _3D_CHICKEN2 0x0208c
814/* Disables pipelining of read flushes past the SF-WIZ interface.
815 * Required on all Ironlake steppings according to the B-Spec, but the
816 * particular danger of not doing so is not specified.
817 */
818# define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14)
819#define _3D_CHICKEN3 0x02090
820#define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10)
821#define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5)
822#define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x)<<1) /* gen8+ */
823#define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */
824
825#define MI_MODE 0x0209c
826# define VS_TIMER_DISPATCH (1 << 6)
827# define MI_FLUSH_ENABLE (1 << 12)
828# define ASYNC_FLIP_PERF_DISABLE (1 << 14)
829# define MODE_IDLE (1 << 9)
830# define STOP_RING (1 << 8)
831
832#define GEN6_GT_MODE 0x20d0
833#define GEN7_GT_MODE 0x7008
834#define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7))
835#define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0)
836#define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1)
837#define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0)
838#define GEN6_WIZ_HASHING_MASK (GEN6_WIZ_HASHING(1, 1) << 16)
839#define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5)
840
841#define GFX_MODE 0x02520
842#define GFX_MODE_GEN7 0x0229c
843#define RING_MODE_GEN7(ring) ((ring)->mmio_base+0x29c)
844#define GFX_RUN_LIST_ENABLE (1<<15)
845#define GFX_TLB_INVALIDATE_ALWAYS (1<<13)
846#define GFX_SURFACE_FAULT_ENABLE (1<<12)
847#define GFX_REPLAY_MODE (1<<11)
848#define GFX_PSMI_GRANULARITY (1<<10)
849#define GFX_PPGTT_ENABLE (1<<9)
850
851#define VLV_DISPLAY_BASE 0x180000
852
853#define SCPD0 0x0209c /* 915+ only */
854#define IER 0x020a0
855#define IIR 0x020a4
856#define IMR 0x020a8
857#define ISR 0x020ac
858#define VLV_GUNIT_CLOCK_GATE (VLV_DISPLAY_BASE + 0x2060)
859#define GCFG_DIS (1<<8)
860#define VLV_IIR_RW (VLV_DISPLAY_BASE + 0x2084)
861#define VLV_IER (VLV_DISPLAY_BASE + 0x20a0)
862#define VLV_IIR (VLV_DISPLAY_BASE + 0x20a4)
863#define VLV_IMR (VLV_DISPLAY_BASE + 0x20a8)
864#define VLV_ISR (VLV_DISPLAY_BASE + 0x20ac)
865#define VLV_PCBR (VLV_DISPLAY_BASE + 0x2120)
866#define DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
867#define EIR 0x020b0
868#define EMR 0x020b4
869#define ESR 0x020b8
870#define GM45_ERROR_PAGE_TABLE (1<<5)
871#define GM45_ERROR_MEM_PRIV (1<<4)
872#define I915_ERROR_PAGE_TABLE (1<<4)
873#define GM45_ERROR_CP_PRIV (1<<3)
874#define I915_ERROR_MEMORY_REFRESH (1<<1)
875#define I915_ERROR_INSTRUCTION (1<<0)
876#define INSTPM 0x020c0
877#define INSTPM_SELF_EN (1<<12) /* 915GM only */
878#define INSTPM_AGPBUSY_DIS (1<<11) /* gen3: when disabled, pending interrupts
879 will not assert AGPBUSY# and will only
880 be delivered when out of C3. */
881#define INSTPM_FORCE_ORDERING (1<<7) /* GEN6+ */
882#define INSTPM_TLB_INVALIDATE (1<<9)
883#define INSTPM_SYNC_FLUSH (1<<5)
884#define ACTHD 0x020c8
885#define FW_BLC 0x020d8
886#define FW_BLC2 0x020dc
887#define FW_BLC_SELF 0x020e0 /* 915+ only */
888#define FW_BLC_SELF_EN_MASK (1<<31)
889#define FW_BLC_SELF_FIFO_MASK (1<<16) /* 945 only */
890#define FW_BLC_SELF_EN (1<<15) /* 945 only */
891#define MM_BURST_LENGTH 0x00700000
892#define MM_FIFO_WATERMARK 0x0001F000
893#define LM_BURST_LENGTH 0x00000700
894#define LM_FIFO_WATERMARK 0x0000001F
895#define MI_ARB_STATE 0x020e4 /* 915+ only */
896
897/* Make render/texture TLB fetches lower priorty than associated data
898 * fetches. This is not turned on by default
899 */
900#define MI_ARB_RENDER_TLB_LOW_PRIORITY (1 << 15)
901
902/* Isoch request wait on GTT enable (Display A/B/C streams).
903 * Make isoch requests stall on the TLB update. May cause
904 * display underruns (test mode only)
905 */
906#define MI_ARB_ISOCH_WAIT_GTT (1 << 14)
907
908/* Block grant count for isoch requests when block count is
909 * set to a finite value.
910 */
911#define MI_ARB_BLOCK_GRANT_MASK (3 << 12)
912#define MI_ARB_BLOCK_GRANT_8 (0 << 12) /* for 3 display planes */
913#define MI_ARB_BLOCK_GRANT_4 (1 << 12) /* for 2 display planes */
914#define MI_ARB_BLOCK_GRANT_2 (2 << 12) /* for 1 display plane */
915#define MI_ARB_BLOCK_GRANT_0 (3 << 12) /* don't use */
916
917/* Enable render writes to complete in C2/C3/C4 power states.
918 * If this isn't enabled, render writes are prevented in low
919 * power states. That seems bad to me.
920 */
921#define MI_ARB_C3_LP_WRITE_ENABLE (1 << 11)
922
923/* This acknowledges an async flip immediately instead
924 * of waiting for 2TLB fetches.
925 */
926#define MI_ARB_ASYNC_FLIP_ACK_IMMEDIATE (1 << 10)
927
928/* Enables non-sequential data reads through arbiter
929 */
930#define MI_ARB_DUAL_DATA_PHASE_DISABLE (1 << 9)
931
932/* Disable FSB snooping of cacheable write cycles from binner/render
933 * command stream
934 */
935#define MI_ARB_CACHE_SNOOP_DISABLE (1 << 8)
936
937/* Arbiter time slice for non-isoch streams */
938#define MI_ARB_TIME_SLICE_MASK (7 << 5)
939#define MI_ARB_TIME_SLICE_1 (0 << 5)
940#define MI_ARB_TIME_SLICE_2 (1 << 5)
941#define MI_ARB_TIME_SLICE_4 (2 << 5)
942#define MI_ARB_TIME_SLICE_6 (3 << 5)
943#define MI_ARB_TIME_SLICE_8 (4 << 5)
944#define MI_ARB_TIME_SLICE_10 (5 << 5)
945#define MI_ARB_TIME_SLICE_14 (6 << 5)
946#define MI_ARB_TIME_SLICE_16 (7 << 5)
947
948/* Low priority grace period page size */
949#define MI_ARB_LOW_PRIORITY_GRACE_4KB (0 << 4) /* default */
950#define MI_ARB_LOW_PRIORITY_GRACE_8KB (1 << 4)
951
952/* Disable display A/B trickle feed */
953#define MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE (1 << 2)
954
955/* Set display plane priority */
956#define MI_ARB_DISPLAY_PRIORITY_A_B (0 << 0) /* display A > display B */
957#define MI_ARB_DISPLAY_PRIORITY_B_A (1 << 0) /* display B > display A */
958
959#define CACHE_MODE_0 0x02120 /* 915+ only */
960#define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1<<8)
961#define CM0_IZ_OPT_DISABLE (1<<6)
962#define CM0_ZR_OPT_DISABLE (1<<5)
963#define CM0_STC_EVICT_DISABLE_LRA_SNB (1<<5)
964#define CM0_DEPTH_EVICT_DISABLE (1<<4)
965#define CM0_COLOR_EVICT_DISABLE (1<<3)
966#define CM0_DEPTH_WRITE_DISABLE (1<<1)
967#define CM0_RC_OP_FLUSH_DISABLE (1<<0)
968#define GFX_FLSH_CNTL 0x02170 /* 915+ only */
969#define GFX_FLSH_CNTL_GEN6 0x101008
970#define GFX_FLSH_CNTL_EN (1<<0)
971#define ECOSKPD 0x021d0
972#define ECO_GATING_CX_ONLY (1<<3)
973#define ECO_FLIP_DONE (1<<0)
974
975#define CACHE_MODE_0_GEN7 0x7000 /* IVB+ */
976#define HIZ_RAW_STALL_OPT_DISABLE (1<<2)
977#define CACHE_MODE_1 0x7004 /* IVB+ */
978#define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE (1<<6)
979#define GEN8_4x4_STC_OPTIMIZATION_DISABLE (1<<6)
980
981#define GEN6_BLITTER_ECOSKPD 0x221d0
982#define GEN6_BLITTER_LOCK_SHIFT 16
983#define GEN6_BLITTER_FBC_NOTIFY (1<<3)
984
985#define GEN6_RC_SLEEP_PSMI_CONTROL 0x2050
986#define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12)
987
988#define GEN6_BSD_SLEEP_PSMI_CONTROL 0x12050
989#define GEN6_BSD_SLEEP_MSG_DISABLE (1 << 0)
990#define GEN6_BSD_SLEEP_FLUSH_DISABLE (1 << 2)
991#define GEN6_BSD_SLEEP_INDICATOR (1 << 3)
992#define GEN6_BSD_GO_INDICATOR (1 << 4)
993
994/* On modern GEN architectures interrupt control consists of two sets
995 * of registers. The first set pertains to the ring generating the
996 * interrupt. The second control is for the functional block generating the
997 * interrupt. These are PM, GT, DE, etc.
998 *
999 * Luckily *knocks on wood* all the ring interrupt bits match up with the
1000 * GT interrupt bits, so we don't need to duplicate the defines.
1001 *
1002 * These defines should cover us well from SNB->HSW with minor exceptions
1003 * it can also work on ILK.
1004 */
1005#define GT_BLT_FLUSHDW_NOTIFY_INTERRUPT (1 << 26)
1006#define GT_BLT_CS_ERROR_INTERRUPT (1 << 25)
1007#define GT_BLT_USER_INTERRUPT (1 << 22)
1008#define GT_BSD_CS_ERROR_INTERRUPT (1 << 15)
1009#define GT_BSD_USER_INTERRUPT (1 << 12)
1010#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 (1 << 11) /* hsw+; rsvd on snb, ivb, vlv */
1011#define GT_RENDER_L3_PARITY_ERROR_INTERRUPT (1 << 5) /* !snb */
1012#define GT_RENDER_PIPECTL_NOTIFY_INTERRUPT (1 << 4)
1013#define GT_RENDER_CS_MASTER_ERROR_INTERRUPT (1 << 3)
1014#define GT_RENDER_SYNC_STATUS_INTERRUPT (1 << 2)
1015#define GT_RENDER_DEBUG_INTERRUPT (1 << 1)
1016#define GT_RENDER_USER_INTERRUPT (1 << 0)
1017
1018#define PM_VEBOX_CS_ERROR_INTERRUPT (1 << 12) /* hsw+ */
1019#define PM_VEBOX_USER_INTERRUPT (1 << 10) /* hsw+ */
1020
1021#define GT_PARITY_ERROR(dev) \
1022 (GT_RENDER_L3_PARITY_ERROR_INTERRUPT | \
1023 (IS_HASWELL(dev) ? GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1 : 0))
1024
1025/* These are all the "old" interrupts */
1026#define ILK_BSD_USER_INTERRUPT (1<<5)
1027#define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18)
1028#define I915_DISPLAY_PORT_INTERRUPT (1<<17)
1029#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15)
1030#define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */
1031#define I915_HWB_OOM_INTERRUPT (1<<13)
1032#define I915_SYNC_STATUS_INTERRUPT (1<<12)
1033#define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11)
1034#define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10)
1035#define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9)
1036#define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8)
1037#define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7)
1038#define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6)
1039#define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5)
1040#define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4)
1041#define I915_DEBUG_INTERRUPT (1<<2)
1042#define I915_USER_INTERRUPT (1<<1)
1043#define I915_ASLE_INTERRUPT (1<<0)
1044#define I915_BSD_USER_INTERRUPT (1 << 25)
1045
1046#define GEN6_BSD_RNCID 0x12198
1047
1048#define GEN7_FF_THREAD_MODE 0x20a0
1049#define GEN7_FF_SCHED_MASK 0x0077070
1050#define GEN8_FF_DS_REF_CNT_FFME (1 << 19)
1051#define GEN7_FF_TS_SCHED_HS1 (0x5<<16)
1052#define GEN7_FF_TS_SCHED_HS0 (0x3<<16)
1053#define GEN7_FF_TS_SCHED_LOAD_BALANCE (0x1<<16)
1054#define GEN7_FF_TS_SCHED_HW (0x0<<16) /* Default */
1055#define GEN7_FF_VS_REF_CNT_FFME (1 << 15)
1056#define GEN7_FF_VS_SCHED_HS1 (0x5<<12)
1057#define GEN7_FF_VS_SCHED_HS0 (0x3<<12)
1058#define GEN7_FF_VS_SCHED_LOAD_BALANCE (0x1<<12) /* Default */
1059#define GEN7_FF_VS_SCHED_HW (0x0<<12)
1060#define GEN7_FF_DS_SCHED_HS1 (0x5<<4)
1061#define GEN7_FF_DS_SCHED_HS0 (0x3<<4)
1062#define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1<<4) /* Default */
1063#define GEN7_FF_DS_SCHED_HW (0x0<<4)
1064
1065/*
1066 * Framebuffer compression (915+ only)
1067 */
1068
1069#define FBC_CFB_BASE 0x03200 /* 4k page aligned */
1070#define FBC_LL_BASE 0x03204 /* 4k page aligned */
1071#define FBC_CONTROL 0x03208
1072#define FBC_CTL_EN (1<<31)
1073#define FBC_CTL_PERIODIC (1<<30)
1074#define FBC_CTL_INTERVAL_SHIFT (16)
1075#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
1076#define FBC_CTL_C3_IDLE (1<<13)
1077#define FBC_CTL_STRIDE_SHIFT (5)
1078#define FBC_CTL_FENCENO_SHIFT (0)
1079#define FBC_COMMAND 0x0320c
1080#define FBC_CMD_COMPRESS (1<<0)
1081#define FBC_STATUS 0x03210
1082#define FBC_STAT_COMPRESSING (1<<31)
1083#define FBC_STAT_COMPRESSED (1<<30)
1084#define FBC_STAT_MODIFIED (1<<29)
1085#define FBC_STAT_CURRENT_LINE_SHIFT (0)
1086#define FBC_CONTROL2 0x03214
1087#define FBC_CTL_FENCE_DBL (0<<4)
1088#define FBC_CTL_IDLE_IMM (0<<2)
1089#define FBC_CTL_IDLE_FULL (1<<2)
1090#define FBC_CTL_IDLE_LINE (2<<2)
1091#define FBC_CTL_IDLE_DEBUG (3<<2)
1092#define FBC_CTL_CPU_FENCE (1<<1)
1093#define FBC_CTL_PLANE(plane) ((plane)<<0)
1094#define FBC_FENCE_OFF 0x03218 /* BSpec typo has 321Bh */
1095#define FBC_TAG 0x03300
1096
1097#define FBC_LL_SIZE (1536)
1098
1099/* Framebuffer compression for GM45+ */
1100#define DPFC_CB_BASE 0x3200
1101#define DPFC_CONTROL 0x3208
1102#define DPFC_CTL_EN (1<<31)
1103#define DPFC_CTL_PLANE(plane) ((plane)<<30)
1104#define IVB_DPFC_CTL_PLANE(plane) ((plane)<<29)
1105#define DPFC_CTL_FENCE_EN (1<<29)
1106#define IVB_DPFC_CTL_FENCE_EN (1<<28)
1107#define DPFC_CTL_PERSISTENT_MODE (1<<25)
1108#define DPFC_SR_EN (1<<10)
1109#define DPFC_CTL_LIMIT_1X (0<<6)
1110#define DPFC_CTL_LIMIT_2X (1<<6)
1111#define DPFC_CTL_LIMIT_4X (2<<6)
1112#define DPFC_RECOMP_CTL 0x320c
1113#define DPFC_RECOMP_STALL_EN (1<<27)
1114#define DPFC_RECOMP_STALL_WM_SHIFT (16)
1115#define DPFC_RECOMP_STALL_WM_MASK (0x07ff0000)
1116#define DPFC_RECOMP_TIMER_COUNT_SHIFT (0)
1117#define DPFC_RECOMP_TIMER_COUNT_MASK (0x0000003f)
1118#define DPFC_STATUS 0x3210
1119#define DPFC_INVAL_SEG_SHIFT (16)
1120#define DPFC_INVAL_SEG_MASK (0x07ff0000)
1121#define DPFC_COMP_SEG_SHIFT (0)
1122#define DPFC_COMP_SEG_MASK (0x000003ff)
1123#define DPFC_STATUS2 0x3214
1124#define DPFC_FENCE_YOFF 0x3218
1125#define DPFC_CHICKEN 0x3224
1126#define DPFC_HT_MODIFY (1<<31)
1127
1128/* Framebuffer compression for Ironlake */
1129#define ILK_DPFC_CB_BASE 0x43200
1130#define ILK_DPFC_CONTROL 0x43208
1131/* The bit 28-8 is reserved */
1132#define DPFC_RESERVED (0x1FFFFF00)
1133#define ILK_DPFC_RECOMP_CTL 0x4320c
1134#define ILK_DPFC_STATUS 0x43210
1135#define ILK_DPFC_FENCE_YOFF 0x43218
1136#define ILK_DPFC_CHICKEN 0x43224
1137#define ILK_FBC_RT_BASE 0x2128
1138#define ILK_FBC_RT_VALID (1<<0)
1139#define SNB_FBC_FRONT_BUFFER (1<<1)
1140
1141#define ILK_DISPLAY_CHICKEN1 0x42000
1142#define ILK_FBCQ_DIS (1<<22)
1143#define ILK_PABSTRETCH_DIS (1<<21)
1144
1145
1146/*
1147 * Framebuffer compression for Sandybridge
1148 *
1149 * The following two registers are of type GTTMMADR
1150 */
1151#define SNB_DPFC_CTL_SA 0x100100
1152#define SNB_CPU_FENCE_ENABLE (1<<29)
1153#define DPFC_CPU_FENCE_OFFSET 0x100104
1154
1155/* Framebuffer compression for Ivybridge */
1156#define IVB_FBC_RT_BASE 0x7020
1157
1158#define IPS_CTL 0x43408
1159#define IPS_ENABLE (1 << 31)
1160
1161#define MSG_FBC_REND_STATE 0x50380
1162#define FBC_REND_NUKE (1<<2)
1163#define FBC_REND_CACHE_CLEAN (1<<1)
1164
1165/*
1166 * GPIO regs
1167 */
1168#define GPIOA 0x5010
1169#define GPIOB 0x5014
1170#define GPIOC 0x5018
1171#define GPIOD 0x501c
1172#define GPIOE 0x5020
1173#define GPIOF 0x5024
1174#define GPIOG 0x5028
1175#define GPIOH 0x502c
1176# define GPIO_CLOCK_DIR_MASK (1 << 0)
1177# define GPIO_CLOCK_DIR_IN (0 << 1)
1178# define GPIO_CLOCK_DIR_OUT (1 << 1)
1179# define GPIO_CLOCK_VAL_MASK (1 << 2)
1180# define GPIO_CLOCK_VAL_OUT (1 << 3)
1181# define GPIO_CLOCK_VAL_IN (1 << 4)
1182# define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
1183# define GPIO_DATA_DIR_MASK (1 << 8)
1184# define GPIO_DATA_DIR_IN (0 << 9)
1185# define GPIO_DATA_DIR_OUT (1 << 9)
1186# define GPIO_DATA_VAL_MASK (1 << 10)
1187# define GPIO_DATA_VAL_OUT (1 << 11)
1188# define GPIO_DATA_VAL_IN (1 << 12)
1189# define GPIO_DATA_PULLUP_DISABLE (1 << 13)
1190
1191#define GMBUS0 0x5100 /* clock/port select */
1192#define GMBUS_RATE_100KHZ (0<<8)
1193#define GMBUS_RATE_50KHZ (1<<8)
1194#define GMBUS_RATE_400KHZ (2<<8) /* reserved on Pineview */
1195#define GMBUS_RATE_1MHZ (3<<8) /* reserved on Pineview */
1196#define GMBUS_HOLD_EXT (1<<7) /* 300ns hold time, rsvd on Pineview */
1197#define GMBUS_PORT_DISABLED 0
1198#define GMBUS_PORT_SSC 1
1199#define GMBUS_PORT_VGADDC 2
1200#define GMBUS_PORT_PANEL 3
1201#define GMBUS_PORT_DPC 4 /* HDMIC */
1202#define GMBUS_PORT_DPB 5 /* SDVO, HDMIB */
1203#define GMBUS_PORT_DPD 6 /* HDMID */
1204#define GMBUS_PORT_RESERVED 7 /* 7 reserved */
1205#define GMBUS_NUM_PORTS (GMBUS_PORT_DPD - GMBUS_PORT_SSC + 1)
1206#define GMBUS1 0x5104 /* command/status */
1207#define GMBUS_SW_CLR_INT (1<<31)
1208#define GMBUS_SW_RDY (1<<30)
1209#define GMBUS_ENT (1<<29) /* enable timeout */
1210#define GMBUS_CYCLE_NONE (0<<25)
1211#define GMBUS_CYCLE_WAIT (1<<25)
1212#define GMBUS_CYCLE_INDEX (2<<25)
1213#define GMBUS_CYCLE_STOP (4<<25)
1214#define GMBUS_BYTE_COUNT_SHIFT 16
1215#define GMBUS_SLAVE_INDEX_SHIFT 8
1216#define GMBUS_SLAVE_ADDR_SHIFT 1
1217#define GMBUS_SLAVE_READ (1<<0)
1218#define GMBUS_SLAVE_WRITE (0<<0)
1219#define GMBUS2 0x5108 /* status */
1220#define GMBUS_INUSE (1<<15)
1221#define GMBUS_HW_WAIT_PHASE (1<<14)
1222#define GMBUS_STALL_TIMEOUT (1<<13)
1223#define GMBUS_INT (1<<12)
1224#define GMBUS_HW_RDY (1<<11)
1225#define GMBUS_SATOER (1<<10)
1226#define GMBUS_ACTIVE (1<<9)
1227#define GMBUS3 0x510c /* data buffer bytes 3-0 */
1228#define GMBUS4 0x5110 /* interrupt mask (Pineview+) */
1229#define GMBUS_SLAVE_TIMEOUT_EN (1<<4)
1230#define GMBUS_NAK_EN (1<<3)
1231#define GMBUS_IDLE_EN (1<<2)
1232#define GMBUS_HW_WAIT_EN (1<<1)
1233#define GMBUS_HW_RDY_EN (1<<0)
1234#define GMBUS5 0x5120 /* byte index */
1235#define GMBUS_2BYTE_INDEX_EN (1<<31)
1236
1237/*
1238 * Clock control & power management
1239 */
1240#define DPLL_A_OFFSET 0x6014
1241#define DPLL_B_OFFSET 0x6018
1242#define DPLL(pipe) (dev_priv->info.dpll_offsets[pipe] + \
1243 dev_priv->info.display_mmio_offset)
1244
1245#define VGA0 0x6000
1246#define VGA1 0x6004
1247#define VGA_PD 0x6010
1248#define VGA0_PD_P2_DIV_4 (1 << 7)
1249#define VGA0_PD_P1_DIV_2 (1 << 5)
1250#define VGA0_PD_P1_SHIFT 0
1251#define VGA0_PD_P1_MASK (0x1f << 0)
1252#define VGA1_PD_P2_DIV_4 (1 << 15)
1253#define VGA1_PD_P1_DIV_2 (1 << 13)
1254#define VGA1_PD_P1_SHIFT 8
1255#define VGA1_PD_P1_MASK (0x1f << 8)
1256#define DPLL_VCO_ENABLE (1 << 31)
1257#define DPLL_SDVO_HIGH_SPEED (1 << 30)
1258#define DPLL_DVO_2X_MODE (1 << 30)
1259#define DPLL_EXT_BUFFER_ENABLE_VLV (1 << 30)
1260#define DPLL_SYNCLOCK_ENABLE (1 << 29)
1261#define DPLL_REFA_CLK_ENABLE_VLV (1 << 29)
1262#define DPLL_VGA_MODE_DIS (1 << 28)
1263#define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */
1264#define DPLLB_MODE_LVDS (2 << 26) /* i915 */
1265#define DPLL_MODE_MASK (3 << 26)
1266#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */
1267#define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */
1268#define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */
1269#define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
1270#define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
1271#define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
1272#define DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW 0x00ff8000 /* Pineview */
1273#define DPLL_LOCK_VLV (1<<15)
1274#define DPLL_INTEGRATED_CRI_CLK_VLV (1<<14)
1275#define DPLL_INTEGRATED_CLOCK_VLV (1<<13)
1276#define DPLL_PORTC_READY_MASK (0xf << 4)
1277#define DPLL_PORTB_READY_MASK (0xf)
1278
1279#define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
1280/*
1281 * The i830 generation, in LVDS mode, defines P1 as the bit number set within
1282 * this field (only one bit may be set).
1283 */
1284#define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
1285#define DPLL_FPA01_P1_POST_DIV_SHIFT 16
1286#define DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW 15
1287/* i830, required in DVO non-gang */
1288#define PLL_P2_DIVIDE_BY_4 (1 << 23)
1289#define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
1290#define PLL_REF_INPUT_DREFCLK (0 << 13)
1291#define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
1292#define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */
1293#define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13)
1294#define PLL_REF_INPUT_MASK (3 << 13)
1295#define PLL_LOAD_PULSE_PHASE_SHIFT 9
1296/* Ironlake */
1297# define PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT 9
1298# define PLL_REF_SDVO_HDMI_MULTIPLIER_MASK (7 << 9)
1299# define PLL_REF_SDVO_HDMI_MULTIPLIER(x) (((x)-1) << 9)
1300# define DPLL_FPA1_P1_POST_DIV_SHIFT 0
1301# define DPLL_FPA1_P1_POST_DIV_MASK 0xff
1302
1303/*
1304 * Parallel to Serial Load Pulse phase selection.
1305 * Selects the phase for the 10X DPLL clock for the PCIe
1306 * digital display port. The range is 4 to 13; 10 or more
1307 * is just a flip delay. The default is 6
1308 */
1309#define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT)
1310#define DISPLAY_RATE_SELECT_FPA1 (1 << 8)
1311/*
1312 * SDVO multiplier for 945G/GM. Not used on 965.
1313 */
1314#define SDVO_MULTIPLIER_MASK 0x000000ff
1315#define SDVO_MULTIPLIER_SHIFT_HIRES 4
1316#define SDVO_MULTIPLIER_SHIFT_VGA 0
1317
1318#define DPLL_A_MD_OFFSET 0x601c /* 965+ only */
1319#define DPLL_B_MD_OFFSET 0x6020 /* 965+ only */
1320#define DPLL_MD(pipe) (dev_priv->info.dpll_md_offsets[pipe] + \
1321 dev_priv->info.display_mmio_offset)
1322
1323/*
1324 * UDI pixel divider, controlling how many pixels are stuffed into a packet.
1325 *
1326 * Value is pixels minus 1. Must be set to 1 pixel for SDVO.
1327 */
1328#define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000
1329#define DPLL_MD_UDI_DIVIDER_SHIFT 24
1330/* UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */
1331#define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000
1332#define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16
1333/*
1334 * SDVO/UDI pixel multiplier.
1335 *
1336 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus
1337 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate
1338 * modes, the bus rate would be below the limits, so SDVO allows for stuffing
1339 * dummy bytes in the datastream at an increased clock rate, with both sides of
1340 * the link knowing how many bytes are fill.
1341 *
1342 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock
1343 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be
1344 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and
1345 * through an SDVO command.
1346 *
1347 * This register field has values of multiplication factor minus 1, with
1348 * a maximum multiplier of 5 for SDVO.
1349 */
1350#define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00
1351#define DPLL_MD_UDI_MULTIPLIER_SHIFT 8
1352/*
1353 * SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK.
1354 * This best be set to the default value (3) or the CRT won't work. No,
1355 * I don't entirely understand what this does...
1356 */
1357#define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f
1358#define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0
1359
1360#define _FPA0 0x06040
1361#define _FPA1 0x06044
1362#define _FPB0 0x06048
1363#define _FPB1 0x0604c
1364#define FP0(pipe) _PIPE(pipe, _FPA0, _FPB0)
1365#define FP1(pipe) _PIPE(pipe, _FPA1, _FPB1)
1366#define FP_N_DIV_MASK 0x003f0000
1367#define FP_N_PINEVIEW_DIV_MASK 0x00ff0000
1368#define FP_N_DIV_SHIFT 16
1369#define FP_M1_DIV_MASK 0x00003f00
1370#define FP_M1_DIV_SHIFT 8
1371#define FP_M2_DIV_MASK 0x0000003f
1372#define FP_M2_PINEVIEW_DIV_MASK 0x000000ff
1373#define FP_M2_DIV_SHIFT 0
1374#define DPLL_TEST 0x606c
1375#define DPLLB_TEST_SDVO_DIV_1 (0 << 22)
1376#define DPLLB_TEST_SDVO_DIV_2 (1 << 22)
1377#define DPLLB_TEST_SDVO_DIV_4 (2 << 22)
1378#define DPLLB_TEST_SDVO_DIV_MASK (3 << 22)
1379#define DPLLB_TEST_N_BYPASS (1 << 19)
1380#define DPLLB_TEST_M_BYPASS (1 << 18)
1381#define DPLLB_INPUT_BUFFER_ENABLE (1 << 16)
1382#define DPLLA_TEST_N_BYPASS (1 << 3)
1383#define DPLLA_TEST_M_BYPASS (1 << 2)
1384#define DPLLA_INPUT_BUFFER_ENABLE (1 << 0)
1385#define D_STATE 0x6104
1386#define DSTATE_GFX_RESET_I830 (1<<6)
1387#define DSTATE_PLL_D3_OFF (1<<3)
1388#define DSTATE_GFX_CLOCK_GATING (1<<1)
1389#define DSTATE_DOT_CLOCK_GATING (1<<0)
1390#define DSPCLK_GATE_D (dev_priv->info.display_mmio_offset + 0x6200)
1391# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
1392# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
1393# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
1394# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
1395# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
1396# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
1397# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
1398# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
1399# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
1400# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
1401# define TVEUNIT_CLOCK_GATE_DISABLE (1 << 20) /* 915-945 */
1402# define DVSUNIT_CLOCK_GATE_DISABLE (1 << 19) /* 915-945 */
1403# define DSSUNIT_CLOCK_GATE_DISABLE (1 << 18) /* 915-945 */
1404# define DDBUNIT_CLOCK_GATE_DISABLE (1 << 17) /* 915-945 */
1405# define DPRUNIT_CLOCK_GATE_DISABLE (1 << 16) /* 915-945 */
1406# define DPFUNIT_CLOCK_GATE_DISABLE (1 << 15) /* 915-945 */
1407# define DPBMUNIT_CLOCK_GATE_DISABLE (1 << 14) /* 915-945 */
1408# define DPLSUNIT_CLOCK_GATE_DISABLE (1 << 13) /* 915-945 */
1409# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
1410# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
1411# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
1412# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
1413# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
1414# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
1415# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
1416# define DPIOUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 915-945 */
1417# define OVFUNIT_CLOCK_GATE_DISABLE (1 << 5)
1418# define OVBUNIT_CLOCK_GATE_DISABLE (1 << 4)
1419/**
1420 * This bit must be set on the 830 to prevent hangs when turning off the
1421 * overlay scaler.
1422 */
1423# define OVRUNIT_CLOCK_GATE_DISABLE (1 << 3)
1424# define OVCUNIT_CLOCK_GATE_DISABLE (1 << 2)
1425# define OVUUNIT_CLOCK_GATE_DISABLE (1 << 1)
1426# define ZVUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 830 */
1427# define OVLUNIT_CLOCK_GATE_DISABLE (1 << 0) /* 845,865 */
1428
1429#define RENCLK_GATE_D1 0x6204
1430# define BLITTER_CLOCK_GATE_DISABLE (1 << 13) /* 945GM only */
1431# define MPEG_CLOCK_GATE_DISABLE (1 << 12) /* 945GM only */
1432# define PC_FE_CLOCK_GATE_DISABLE (1 << 11)
1433# define PC_BE_CLOCK_GATE_DISABLE (1 << 10)
1434# define WINDOWER_CLOCK_GATE_DISABLE (1 << 9)
1435# define INTERPOLATOR_CLOCK_GATE_DISABLE (1 << 8)
1436# define COLOR_CALCULATOR_CLOCK_GATE_DISABLE (1 << 7)
1437# define MOTION_COMP_CLOCK_GATE_DISABLE (1 << 6)
1438# define MAG_CLOCK_GATE_DISABLE (1 << 5)
1439/** This bit must be unset on 855,865 */
1440# define MECI_CLOCK_GATE_DISABLE (1 << 4)
1441# define DCMP_CLOCK_GATE_DISABLE (1 << 3)
1442# define MEC_CLOCK_GATE_DISABLE (1 << 2)
1443# define MECO_CLOCK_GATE_DISABLE (1 << 1)
1444/** This bit must be set on 855,865. */
1445# define SV_CLOCK_GATE_DISABLE (1 << 0)
1446# define I915_MPEG_CLOCK_GATE_DISABLE (1 << 16)
1447# define I915_VLD_IP_PR_CLOCK_GATE_DISABLE (1 << 15)
1448# define I915_MOTION_COMP_CLOCK_GATE_DISABLE (1 << 14)
1449# define I915_BD_BF_CLOCK_GATE_DISABLE (1 << 13)
1450# define I915_SF_SE_CLOCK_GATE_DISABLE (1 << 12)
1451# define I915_WM_CLOCK_GATE_DISABLE (1 << 11)
1452# define I915_IZ_CLOCK_GATE_DISABLE (1 << 10)
1453# define I915_PI_CLOCK_GATE_DISABLE (1 << 9)
1454# define I915_DI_CLOCK_GATE_DISABLE (1 << 8)
1455# define I915_SH_SV_CLOCK_GATE_DISABLE (1 << 7)
1456# define I915_PL_DG_QC_FT_CLOCK_GATE_DISABLE (1 << 6)
1457# define I915_SC_CLOCK_GATE_DISABLE (1 << 5)
1458# define I915_FL_CLOCK_GATE_DISABLE (1 << 4)
1459# define I915_DM_CLOCK_GATE_DISABLE (1 << 3)
1460# define I915_PS_CLOCK_GATE_DISABLE (1 << 2)
1461# define I915_CC_CLOCK_GATE_DISABLE (1 << 1)
1462# define I915_BY_CLOCK_GATE_DISABLE (1 << 0)
1463
1464# define I965_RCZ_CLOCK_GATE_DISABLE (1 << 30)
1465/** This bit must always be set on 965G/965GM */
1466# define I965_RCC_CLOCK_GATE_DISABLE (1 << 29)
1467# define I965_RCPB_CLOCK_GATE_DISABLE (1 << 28)
1468# define I965_DAP_CLOCK_GATE_DISABLE (1 << 27)
1469# define I965_ROC_CLOCK_GATE_DISABLE (1 << 26)
1470# define I965_GW_CLOCK_GATE_DISABLE (1 << 25)
1471# define I965_TD_CLOCK_GATE_DISABLE (1 << 24)
1472/** This bit must always be set on 965G */
1473# define I965_ISC_CLOCK_GATE_DISABLE (1 << 23)
1474# define I965_IC_CLOCK_GATE_DISABLE (1 << 22)
1475# define I965_EU_CLOCK_GATE_DISABLE (1 << 21)
1476# define I965_IF_CLOCK_GATE_DISABLE (1 << 20)
1477# define I965_TC_CLOCK_GATE_DISABLE (1 << 19)
1478# define I965_SO_CLOCK_GATE_DISABLE (1 << 17)
1479# define I965_FBC_CLOCK_GATE_DISABLE (1 << 16)
1480# define I965_MARI_CLOCK_GATE_DISABLE (1 << 15)
1481# define I965_MASF_CLOCK_GATE_DISABLE (1 << 14)
1482# define I965_MAWB_CLOCK_GATE_DISABLE (1 << 13)
1483# define I965_EM_CLOCK_GATE_DISABLE (1 << 12)
1484# define I965_UC_CLOCK_GATE_DISABLE (1 << 11)
1485# define I965_SI_CLOCK_GATE_DISABLE (1 << 6)
1486# define I965_MT_CLOCK_GATE_DISABLE (1 << 5)
1487# define I965_PL_CLOCK_GATE_DISABLE (1 << 4)
1488# define I965_DG_CLOCK_GATE_DISABLE (1 << 3)
1489# define I965_QC_CLOCK_GATE_DISABLE (1 << 2)
1490# define I965_FT_CLOCK_GATE_DISABLE (1 << 1)
1491# define I965_DM_CLOCK_GATE_DISABLE (1 << 0)
1492
1493#define RENCLK_GATE_D2 0x6208
1494#define VF_UNIT_CLOCK_GATE_DISABLE (1 << 9)
1495#define GS_UNIT_CLOCK_GATE_DISABLE (1 << 7)
1496#define CL_UNIT_CLOCK_GATE_DISABLE (1 << 6)
1497#define RAMCLK_GATE_D 0x6210 /* CRL only */
1498#define DEUC 0x6214 /* CRL only */
1499
1500#define FW_BLC_SELF_VLV (VLV_DISPLAY_BASE + 0x6500)
1501#define FW_CSPWRDWNEN (1<<15)
1502
1503#define MI_ARB_VLV (VLV_DISPLAY_BASE + 0x6504)
1504
1505#define CZCLK_CDCLK_FREQ_RATIO (VLV_DISPLAY_BASE + 0x6508)
1506#define CDCLK_FREQ_SHIFT 4
1507#define CDCLK_FREQ_MASK (0x1f << CDCLK_FREQ_SHIFT)
1508#define CZCLK_FREQ_MASK 0xf
1509#define GMBUSFREQ_VLV (VLV_DISPLAY_BASE + 0x6510)
1510
1511/*
1512 * Palette regs
1513 */
1514#define PALETTE_A_OFFSET 0xa000
1515#define PALETTE_B_OFFSET 0xa800
1516#define PALETTE(pipe) (dev_priv->info.palette_offsets[pipe] + \
1517 dev_priv->info.display_mmio_offset)
1518
1519/* MCH MMIO space */
1520
1521/*
1522 * MCHBAR mirror.
1523 *
1524 * This mirrors the MCHBAR MMIO space whose location is determined by
1525 * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
1526 * every way. It is not accessible from the CP register read instructions.
1527 *
1528 * Starting from Haswell, you can't write registers using the MCHBAR mirror,
1529 * just read.
1530 */
1531#define MCHBAR_MIRROR_BASE 0x10000
1532
1533#define MCHBAR_MIRROR_BASE_SNB 0x140000
1534
1535/* Memory controller frequency in MCHBAR for Haswell (possible SNB+) */
1536#define DCLK (MCHBAR_MIRROR_BASE_SNB + 0x5e04)
1537
1538/** 915-945 and GM965 MCH register controlling DRAM channel access */
1539#define DCC 0x10200
1540#define DCC_ADDRESSING_MODE_SINGLE_CHANNEL (0 << 0)
1541#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC (1 << 0)
1542#define DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED (2 << 0)
1543#define DCC_ADDRESSING_MODE_MASK (3 << 0)
1544#define DCC_CHANNEL_XOR_DISABLE (1 << 10)
1545#define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
1546
1547/** Pineview MCH register contains DDR3 setting */
1548#define CSHRDDR3CTL 0x101a8
1549#define CSHRDDR3CTL_DDR3 (1 << 2)
1550
1551/** 965 MCH register controlling DRAM channel configuration */
1552#define C0DRB3 0x10206
1553#define C1DRB3 0x10606
1554
1555/** snb MCH registers for reading the DRAM channel configuration */
1556#define MAD_DIMM_C0 (MCHBAR_MIRROR_BASE_SNB + 0x5004)
1557#define MAD_DIMM_C1 (MCHBAR_MIRROR_BASE_SNB + 0x5008)
1558#define MAD_DIMM_C2 (MCHBAR_MIRROR_BASE_SNB + 0x500C)
1559#define MAD_DIMM_ECC_MASK (0x3 << 24)
1560#define MAD_DIMM_ECC_OFF (0x0 << 24)
1561#define MAD_DIMM_ECC_IO_ON_LOGIC_OFF (0x1 << 24)
1562#define MAD_DIMM_ECC_IO_OFF_LOGIC_ON (0x2 << 24)
1563#define MAD_DIMM_ECC_ON (0x3 << 24)
1564#define MAD_DIMM_ENH_INTERLEAVE (0x1 << 22)
1565#define MAD_DIMM_RANK_INTERLEAVE (0x1 << 21)
1566#define MAD_DIMM_B_WIDTH_X16 (0x1 << 20) /* X8 chips if unset */
1567#define MAD_DIMM_A_WIDTH_X16 (0x1 << 19) /* X8 chips if unset */
1568#define MAD_DIMM_B_DUAL_RANK (0x1 << 18)
1569#define MAD_DIMM_A_DUAL_RANK (0x1 << 17)
1570#define MAD_DIMM_A_SELECT (0x1 << 16)
1571/* DIMM sizes are in multiples of 256mb. */
1572#define MAD_DIMM_B_SIZE_SHIFT 8
1573#define MAD_DIMM_B_SIZE_MASK (0xff << MAD_DIMM_B_SIZE_SHIFT)
1574#define MAD_DIMM_A_SIZE_SHIFT 0
1575#define MAD_DIMM_A_SIZE_MASK (0xff << MAD_DIMM_A_SIZE_SHIFT)
1576
1577/** snb MCH registers for priority tuning */
1578#define MCH_SSKPD (MCHBAR_MIRROR_BASE_SNB + 0x5d10)
1579#define MCH_SSKPD_WM0_MASK 0x3f
1580#define MCH_SSKPD_WM0_VAL 0xc
1581
1582#define MCH_SECP_NRG_STTS (MCHBAR_MIRROR_BASE_SNB + 0x592c)
1583
1584/* Clocking configuration register */
1585#define CLKCFG 0x10c00
1586#define CLKCFG_FSB_400 (5 << 0) /* hrawclk 100 */
1587#define CLKCFG_FSB_533 (1 << 0) /* hrawclk 133 */
1588#define CLKCFG_FSB_667 (3 << 0) /* hrawclk 166 */
1589#define CLKCFG_FSB_800 (2 << 0) /* hrawclk 200 */
1590#define CLKCFG_FSB_1067 (6 << 0) /* hrawclk 266 */
1591#define CLKCFG_FSB_1333 (7 << 0) /* hrawclk 333 */
1592/* Note, below two are guess */
1593#define CLKCFG_FSB_1600 (4 << 0) /* hrawclk 400 */
1594#define CLKCFG_FSB_1600_ALT (0 << 0) /* hrawclk 400 */
1595#define CLKCFG_FSB_MASK (7 << 0)
1596#define CLKCFG_MEM_533 (1 << 4)
1597#define CLKCFG_MEM_667 (2 << 4)
1598#define CLKCFG_MEM_800 (3 << 4)
1599#define CLKCFG_MEM_MASK (7 << 4)
1600
1601#define TSC1 0x11001
1602#define TSE (1<<0)
1603#define TR1 0x11006
1604#define TSFS 0x11020
1605#define TSFS_SLOPE_MASK 0x0000ff00
1606#define TSFS_SLOPE_SHIFT 8
1607#define TSFS_INTR_MASK 0x000000ff
1608
1609#define CRSTANDVID 0x11100
1610#define PXVFREQ_BASE 0x11110 /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */
1611#define PXVFREQ_PX_MASK 0x7f000000
1612#define PXVFREQ_PX_SHIFT 24
1613#define VIDFREQ_BASE 0x11110
1614#define VIDFREQ1 0x11110 /* VIDFREQ1-4 (0x1111c) (Cantiga) */
1615#define VIDFREQ2 0x11114
1616#define VIDFREQ3 0x11118
1617#define VIDFREQ4 0x1111c
1618#define VIDFREQ_P0_MASK 0x1f000000
1619#define VIDFREQ_P0_SHIFT 24
1620#define VIDFREQ_P0_CSCLK_MASK 0x00f00000
1621#define VIDFREQ_P0_CSCLK_SHIFT 20
1622#define VIDFREQ_P0_CRCLK_MASK 0x000f0000
1623#define VIDFREQ_P0_CRCLK_SHIFT 16
1624#define VIDFREQ_P1_MASK 0x00001f00
1625#define VIDFREQ_P1_SHIFT 8
1626#define VIDFREQ_P1_CSCLK_MASK 0x000000f0
1627#define VIDFREQ_P1_CSCLK_SHIFT 4
1628#define VIDFREQ_P1_CRCLK_MASK 0x0000000f
1629#define INTTOEXT_BASE_ILK 0x11300
1630#define INTTOEXT_BASE 0x11120 /* INTTOEXT1-8 (0x1113c) */
1631#define INTTOEXT_MAP3_SHIFT 24
1632#define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT)
1633#define INTTOEXT_MAP2_SHIFT 16
1634#define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT)
1635#define INTTOEXT_MAP1_SHIFT 8
1636#define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT)
1637#define INTTOEXT_MAP0_SHIFT 0
1638#define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT)
1639#define MEMSWCTL 0x11170 /* Ironlake only */
1640#define MEMCTL_CMD_MASK 0xe000
1641#define MEMCTL_CMD_SHIFT 13
1642#define MEMCTL_CMD_RCLK_OFF 0
1643#define MEMCTL_CMD_RCLK_ON 1
1644#define MEMCTL_CMD_CHFREQ 2
1645#define MEMCTL_CMD_CHVID 3
1646#define MEMCTL_CMD_VMMOFF 4
1647#define MEMCTL_CMD_VMMON 5
1648#define MEMCTL_CMD_STS (1<<12) /* write 1 triggers command, clears
1649 when command complete */
1650#define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */
1651#define MEMCTL_FREQ_SHIFT 8
1652#define MEMCTL_SFCAVM (1<<7)
1653#define MEMCTL_TGT_VID_MASK 0x007f
1654#define MEMIHYST 0x1117c
1655#define MEMINTREN 0x11180 /* 16 bits */
1656#define MEMINT_RSEXIT_EN (1<<8)
1657#define MEMINT_CX_SUPR_EN (1<<7)
1658#define MEMINT_CONT_BUSY_EN (1<<6)
1659#define MEMINT_AVG_BUSY_EN (1<<5)
1660#define MEMINT_EVAL_CHG_EN (1<<4)
1661#define MEMINT_MON_IDLE_EN (1<<3)
1662#define MEMINT_UP_EVAL_EN (1<<2)
1663#define MEMINT_DOWN_EVAL_EN (1<<1)
1664#define MEMINT_SW_CMD_EN (1<<0)
1665#define MEMINTRSTR 0x11182 /* 16 bits */
1666#define MEM_RSEXIT_MASK 0xc000
1667#define MEM_RSEXIT_SHIFT 14
1668#define MEM_CONT_BUSY_MASK 0x3000
1669#define MEM_CONT_BUSY_SHIFT 12
1670#define MEM_AVG_BUSY_MASK 0x0c00
1671#define MEM_AVG_BUSY_SHIFT 10
1672#define MEM_EVAL_CHG_MASK 0x0300
1673#define MEM_EVAL_BUSY_SHIFT 8
1674#define MEM_MON_IDLE_MASK 0x00c0
1675#define MEM_MON_IDLE_SHIFT 6
1676#define MEM_UP_EVAL_MASK 0x0030
1677#define MEM_UP_EVAL_SHIFT 4
1678#define MEM_DOWN_EVAL_MASK 0x000c
1679#define MEM_DOWN_EVAL_SHIFT 2
1680#define MEM_SW_CMD_MASK 0x0003
1681#define MEM_INT_STEER_GFX 0
1682#define MEM_INT_STEER_CMR 1
1683#define MEM_INT_STEER_SMI 2
1684#define MEM_INT_STEER_SCI 3
1685#define MEMINTRSTS 0x11184
1686#define MEMINT_RSEXIT (1<<7)
1687#define MEMINT_CONT_BUSY (1<<6)
1688#define MEMINT_AVG_BUSY (1<<5)
1689#define MEMINT_EVAL_CHG (1<<4)
1690#define MEMINT_MON_IDLE (1<<3)
1691#define MEMINT_UP_EVAL (1<<2)
1692#define MEMINT_DOWN_EVAL (1<<1)
1693#define MEMINT_SW_CMD (1<<0)
1694#define MEMMODECTL 0x11190
1695#define MEMMODE_BOOST_EN (1<<31)
1696#define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */
1697#define MEMMODE_BOOST_FREQ_SHIFT 24
1698#define MEMMODE_IDLE_MODE_MASK 0x00030000
1699#define MEMMODE_IDLE_MODE_SHIFT 16
1700#define MEMMODE_IDLE_MODE_EVAL 0
1701#define MEMMODE_IDLE_MODE_CONT 1
1702#define MEMMODE_HWIDLE_EN (1<<15)
1703#define MEMMODE_SWMODE_EN (1<<14)
1704#define MEMMODE_RCLK_GATE (1<<13)
1705#define MEMMODE_HW_UPDATE (1<<12)
1706#define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */
1707#define MEMMODE_FSTART_SHIFT 8
1708#define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */
1709#define MEMMODE_FMAX_SHIFT 4
1710#define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */
1711#define RCBMAXAVG 0x1119c
1712#define MEMSWCTL2 0x1119e /* Cantiga only */
1713#define SWMEMCMD_RENDER_OFF (0 << 13)
1714#define SWMEMCMD_RENDER_ON (1 << 13)
1715#define SWMEMCMD_SWFREQ (2 << 13)
1716#define SWMEMCMD_TARVID (3 << 13)
1717#define SWMEMCMD_VRM_OFF (4 << 13)
1718#define SWMEMCMD_VRM_ON (5 << 13)
1719#define CMDSTS (1<<12)
1720#define SFCAVM (1<<11)
1721#define SWFREQ_MASK 0x0380 /* P0-7 */
1722#define SWFREQ_SHIFT 7
1723#define TARVID_MASK 0x001f
1724#define MEMSTAT_CTG 0x111a0
1725#define RCBMINAVG 0x111a0
1726#define RCUPEI 0x111b0
1727#define RCDNEI 0x111b4
1728#define RSTDBYCTL 0x111b8
1729#define RS1EN (1<<31)
1730#define RS2EN (1<<30)
1731#define RS3EN (1<<29)
1732#define D3RS3EN (1<<28) /* Display D3 imlies RS3 */
1733#define SWPROMORSX (1<<27) /* RSx promotion timers ignored */
1734#define RCWAKERW (1<<26) /* Resetwarn from PCH causes wakeup */
1735#define DPRSLPVREN (1<<25) /* Fast voltage ramp enable */
1736#define GFXTGHYST (1<<24) /* Hysteresis to allow trunk gating */
1737#define RCX_SW_EXIT (1<<23) /* Leave RSx and prevent re-entry */
1738#define RSX_STATUS_MASK (7<<20)
1739#define RSX_STATUS_ON (0<<20)
1740#define RSX_STATUS_RC1 (1<<20)
1741#define RSX_STATUS_RC1E (2<<20)
1742#define RSX_STATUS_RS1 (3<<20)
1743#define RSX_STATUS_RS2 (4<<20) /* aka rc6 */
1744#define RSX_STATUS_RSVD (5<<20) /* deep rc6 unsupported on ilk */
1745#define RSX_STATUS_RS3 (6<<20) /* rs3 unsupported on ilk */
1746#define RSX_STATUS_RSVD2 (7<<20)
1747#define UWRCRSXE (1<<19) /* wake counter limit prevents rsx */
1748#define RSCRP (1<<18) /* rs requests control on rs1/2 reqs */
1749#define JRSC (1<<17) /* rsx coupled to cpu c-state */
1750#define RS2INC0 (1<<16) /* allow rs2 in cpu c0 */
1751#define RS1CONTSAV_MASK (3<<14)
1752#define RS1CONTSAV_NO_RS1 (0<<14) /* rs1 doesn't save/restore context */
1753#define RS1CONTSAV_RSVD (1<<14)
1754#define RS1CONTSAV_SAVE_RS1 (2<<14) /* rs1 saves context */
1755#define RS1CONTSAV_FULL_RS1 (3<<14) /* rs1 saves and restores context */
1756#define NORMSLEXLAT_MASK (3<<12)
1757#define SLOW_RS123 (0<<12)
1758#define SLOW_RS23 (1<<12)
1759#define SLOW_RS3 (2<<12)
1760#define NORMAL_RS123 (3<<12)
1761#define RCMODE_TIMEOUT (1<<11) /* 0 is eval interval method */
1762#define IMPROMOEN (1<<10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */
1763#define RCENTSYNC (1<<9) /* rs coupled to cpu c-state (3/6/7) */
1764#define STATELOCK (1<<7) /* locked to rs_cstate if 0 */
1765#define RS_CSTATE_MASK (3<<4)
1766#define RS_CSTATE_C367_RS1 (0<<4)
1767#define RS_CSTATE_C36_RS1_C7_RS2 (1<<4)
1768#define RS_CSTATE_RSVD (2<<4)
1769#define RS_CSTATE_C367_RS2 (3<<4)
1770#define REDSAVES (1<<3) /* no context save if was idle during rs0 */
1771#define REDRESTORES (1<<2) /* no restore if was idle during rs0 */
1772#define VIDCTL 0x111c0
1773#define VIDSTS 0x111c8
1774#define VIDSTART 0x111cc /* 8 bits */
1775#define MEMSTAT_ILK 0x111f8
1776#define MEMSTAT_VID_MASK 0x7f00
1777#define MEMSTAT_VID_SHIFT 8
1778#define MEMSTAT_PSTATE_MASK 0x00f8
1779#define MEMSTAT_PSTATE_SHIFT 3
1780#define MEMSTAT_MON_ACTV (1<<2)
1781#define MEMSTAT_SRC_CTL_MASK 0x0003
1782#define MEMSTAT_SRC_CTL_CORE 0
1783#define MEMSTAT_SRC_CTL_TRB 1
1784#define MEMSTAT_SRC_CTL_THM 2
1785#define MEMSTAT_SRC_CTL_STDBY 3
1786#define RCPREVBSYTUPAVG 0x113b8
1787#define RCPREVBSYTDNAVG 0x113bc
1788#define PMMISC 0x11214
1789#define MCPPCE_EN (1<<0) /* enable PM_MSG from PCH->MPC */
1790#define SDEW 0x1124c
1791#define CSIEW0 0x11250
1792#define CSIEW1 0x11254
1793#define CSIEW2 0x11258
1794#define PEW 0x1125c
1795#define DEW 0x11270
1796#define MCHAFE 0x112c0
1797#define CSIEC 0x112e0
1798#define DMIEC 0x112e4
1799#define DDREC 0x112e8
1800#define PEG0EC 0x112ec
1801#define PEG1EC 0x112f0
1802#define GFXEC 0x112f4
1803#define RPPREVBSYTUPAVG 0x113b8
1804#define RPPREVBSYTDNAVG 0x113bc
1805#define ECR 0x11600
1806#define ECR_GPFE (1<<31)
1807#define ECR_IMONE (1<<30)
1808#define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */
1809#define OGW0 0x11608
1810#define OGW1 0x1160c
1811#define EG0 0x11610
1812#define EG1 0x11614
1813#define EG2 0x11618
1814#define EG3 0x1161c
1815#define EG4 0x11620
1816#define EG5 0x11624
1817#define EG6 0x11628
1818#define EG7 0x1162c
1819#define PXW 0x11664
1820#define PXWL 0x11680
1821#define LCFUSE02 0x116c0
1822#define LCFUSE_HIV_MASK 0x000000ff
1823#define CSIPLL0 0x12c10
1824#define DDRMPLL1 0X12c20
1825#define PEG_BAND_GAP_DATA 0x14d68
1826
1827#define GEN6_GT_THREAD_STATUS_REG 0x13805c
1828#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
1829#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
1830
1831#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
1832#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
1833#define GEN6_RP_STATE_CAP (MCHBAR_MIRROR_BASE_SNB + 0x5998)
1834
1835/*
1836 * Logical Context regs
1837 */
1838#define CCID 0x2180
1839#define CCID_EN (1<<0)
1840/*
1841 * Notes on SNB/IVB/VLV context size:
1842 * - Power context is saved elsewhere (LLC or stolen)
1843 * - Ring/execlist context is saved on SNB, not on IVB
1844 * - Extended context size already includes render context size
1845 * - We always need to follow the extended context size.
1846 * SNB BSpec has comments indicating that we should use the
1847 * render context size instead if execlists are disabled, but
1848 * based on empirical testing that's just nonsense.
1849 * - Pipelined/VF state is saved on SNB/IVB respectively
1850 * - GT1 size just indicates how much of render context
1851 * doesn't need saving on GT1
1852 */
1853#define CXT_SIZE 0x21a0
1854#define GEN6_CXT_POWER_SIZE(cxt_reg) ((cxt_reg >> 24) & 0x3f)
1855#define GEN6_CXT_RING_SIZE(cxt_reg) ((cxt_reg >> 18) & 0x3f)
1856#define GEN6_CXT_RENDER_SIZE(cxt_reg) ((cxt_reg >> 12) & 0x3f)
1857#define GEN6_CXT_EXTENDED_SIZE(cxt_reg) ((cxt_reg >> 6) & 0x3f)
1858#define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f)
1859#define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \
1860 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \
1861 GEN6_CXT_PIPELINE_SIZE(cxt_reg))
1862#define GEN7_CXT_SIZE 0x21a8
1863#define GEN7_CXT_POWER_SIZE(ctx_reg) ((ctx_reg >> 25) & 0x7f)
1864#define GEN7_CXT_RING_SIZE(ctx_reg) ((ctx_reg >> 22) & 0x7)
1865#define GEN7_CXT_RENDER_SIZE(ctx_reg) ((ctx_reg >> 16) & 0x3f)
1866#define GEN7_CXT_EXTENDED_SIZE(ctx_reg) ((ctx_reg >> 9) & 0x7f)
1867#define GEN7_CXT_GT1_SIZE(ctx_reg) ((ctx_reg >> 6) & 0x7)
1868#define GEN7_CXT_VFSTATE_SIZE(ctx_reg) ((ctx_reg >> 0) & 0x3f)
1869#define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \
1870 GEN7_CXT_VFSTATE_SIZE(ctx_reg))
1871/* Haswell does have the CXT_SIZE register however it does not appear to be
1872 * valid. Now, docs explain in dwords what is in the context object. The full
1873 * size is 70720 bytes, however, the power context and execlist context will
1874 * never be saved (power context is stored elsewhere, and execlists don't work
1875 * on HSW) - so the final size is 66944 bytes, which rounds to 17 pages.
1876 */
1877#define HSW_CXT_TOTAL_SIZE (17 * PAGE_SIZE)
1878/* Same as Haswell, but 72064 bytes now. */
1879#define GEN8_CXT_TOTAL_SIZE (18 * PAGE_SIZE)
1880
1881
1882#define VLV_CLK_CTL2 0x101104
1883#define CLK_CTL2_CZCOUNT_30NS_SHIFT 28
1884
1885/*
1886 * Overlay regs
1887 */
1888
1889#define OVADD 0x30000
1890#define DOVSTA 0x30008
1891#define OC_BUF (0x3<<20)
1892#define OGAMC5 0x30010
1893#define OGAMC4 0x30014
1894#define OGAMC3 0x30018
1895#define OGAMC2 0x3001c
1896#define OGAMC1 0x30020
1897#define OGAMC0 0x30024
1898
1899/*
1900 * Display engine regs
1901 */
1902
1903/* Pipe A CRC regs */
1904#define _PIPE_CRC_CTL_A 0x60050
1905#define PIPE_CRC_ENABLE (1 << 31)
1906/* ivb+ source selection */
1907#define PIPE_CRC_SOURCE_PRIMARY_IVB (0 << 29)
1908#define PIPE_CRC_SOURCE_SPRITE_IVB (1 << 29)
1909#define PIPE_CRC_SOURCE_PF_IVB (2 << 29)
1910/* ilk+ source selection */
1911#define PIPE_CRC_SOURCE_PRIMARY_ILK (0 << 28)
1912#define PIPE_CRC_SOURCE_SPRITE_ILK (1 << 28)
1913#define PIPE_CRC_SOURCE_PIPE_ILK (2 << 28)
1914/* embedded DP port on the north display block, reserved on ivb */
1915#define PIPE_CRC_SOURCE_PORT_A_ILK (4 << 28)
1916#define PIPE_CRC_SOURCE_FDI_ILK (5 << 28) /* reserved on ivb */
1917/* vlv source selection */
1918#define PIPE_CRC_SOURCE_PIPE_VLV (0 << 27)
1919#define PIPE_CRC_SOURCE_HDMIB_VLV (1 << 27)
1920#define PIPE_CRC_SOURCE_HDMIC_VLV (2 << 27)
1921/* with DP port the pipe source is invalid */
1922#define PIPE_CRC_SOURCE_DP_D_VLV (3 << 27)
1923#define PIPE_CRC_SOURCE_DP_B_VLV (6 << 27)
1924#define PIPE_CRC_SOURCE_DP_C_VLV (7 << 27)
1925/* gen3+ source selection */
1926#define PIPE_CRC_SOURCE_PIPE_I9XX (0 << 28)
1927#define PIPE_CRC_SOURCE_SDVOB_I9XX (1 << 28)
1928#define PIPE_CRC_SOURCE_SDVOC_I9XX (2 << 28)
1929/* with DP/TV port the pipe source is invalid */
1930#define PIPE_CRC_SOURCE_DP_D_G4X (3 << 28)
1931#define PIPE_CRC_SOURCE_TV_PRE (4 << 28)
1932#define PIPE_CRC_SOURCE_TV_POST (5 << 28)
1933#define PIPE_CRC_SOURCE_DP_B_G4X (6 << 28)
1934#define PIPE_CRC_SOURCE_DP_C_G4X (7 << 28)
1935/* gen2 doesn't have source selection bits */
1936#define PIPE_CRC_INCLUDE_BORDER_I8XX (1 << 30)
1937
1938#define _PIPE_CRC_RES_1_A_IVB 0x60064
1939#define _PIPE_CRC_RES_2_A_IVB 0x60068
1940#define _PIPE_CRC_RES_3_A_IVB 0x6006c
1941#define _PIPE_CRC_RES_4_A_IVB 0x60070
1942#define _PIPE_CRC_RES_5_A_IVB 0x60074
1943
1944#define _PIPE_CRC_RES_RED_A 0x60060
1945#define _PIPE_CRC_RES_GREEN_A 0x60064
1946#define _PIPE_CRC_RES_BLUE_A 0x60068
1947#define _PIPE_CRC_RES_RES1_A_I915 0x6006c
1948#define _PIPE_CRC_RES_RES2_A_G4X 0x60080
1949
1950/* Pipe B CRC regs */
1951#define _PIPE_CRC_RES_1_B_IVB 0x61064
1952#define _PIPE_CRC_RES_2_B_IVB 0x61068
1953#define _PIPE_CRC_RES_3_B_IVB 0x6106c
1954#define _PIPE_CRC_RES_4_B_IVB 0x61070
1955#define _PIPE_CRC_RES_5_B_IVB 0x61074
1956
1957#define PIPE_CRC_CTL(pipe) _TRANSCODER2(pipe, _PIPE_CRC_CTL_A)
1958#define PIPE_CRC_RES_1_IVB(pipe) \
1959 _TRANSCODER2(pipe, _PIPE_CRC_RES_1_A_IVB)
1960#define PIPE_CRC_RES_2_IVB(pipe) \
1961 _TRANSCODER2(pipe, _PIPE_CRC_RES_2_A_IVB)
1962#define PIPE_CRC_RES_3_IVB(pipe) \
1963 _TRANSCODER2(pipe, _PIPE_CRC_RES_3_A_IVB)
1964#define PIPE_CRC_RES_4_IVB(pipe) \
1965 _TRANSCODER2(pipe, _PIPE_CRC_RES_4_A_IVB)
1966#define PIPE_CRC_RES_5_IVB(pipe) \
1967 _TRANSCODER2(pipe, _PIPE_CRC_RES_5_A_IVB)
1968
1969#define PIPE_CRC_RES_RED(pipe) \
1970 _TRANSCODER2(pipe, _PIPE_CRC_RES_RED_A)
1971#define PIPE_CRC_RES_GREEN(pipe) \
1972 _TRANSCODER2(pipe, _PIPE_CRC_RES_GREEN_A)
1973#define PIPE_CRC_RES_BLUE(pipe) \
1974 _TRANSCODER2(pipe, _PIPE_CRC_RES_BLUE_A)
1975#define PIPE_CRC_RES_RES1_I915(pipe) \
1976 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES1_A_I915)
1977#define PIPE_CRC_RES_RES2_G4X(pipe) \
1978 _TRANSCODER2(pipe, _PIPE_CRC_RES_RES2_A_G4X)
1979
1980/* Pipe A timing regs */
1981#define _HTOTAL_A 0x60000
1982#define _HBLANK_A 0x60004
1983#define _HSYNC_A 0x60008
1984#define _VTOTAL_A 0x6000c
1985#define _VBLANK_A 0x60010
1986#define _VSYNC_A 0x60014
1987#define _PIPEASRC 0x6001c
1988#define _BCLRPAT_A 0x60020
1989#define _VSYNCSHIFT_A 0x60028
1990
1991/* Pipe B timing regs */
1992#define _HTOTAL_B 0x61000
1993#define _HBLANK_B 0x61004
1994#define _HSYNC_B 0x61008
1995#define _VTOTAL_B 0x6100c
1996#define _VBLANK_B 0x61010
1997#define _VSYNC_B 0x61014
1998#define _PIPEBSRC 0x6101c
1999#define _BCLRPAT_B 0x61020
2000#define _VSYNCSHIFT_B 0x61028
2001
2002#define TRANSCODER_A_OFFSET 0x60000
2003#define TRANSCODER_B_OFFSET 0x61000
2004#define TRANSCODER_C_OFFSET 0x62000
2005#define TRANSCODER_EDP_OFFSET 0x6f000
2006
2007#define _TRANSCODER2(pipe, reg) (dev_priv->info.trans_offsets[(pipe)] - \
2008 dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
2009 dev_priv->info.display_mmio_offset)
2010
2011#define HTOTAL(trans) _TRANSCODER2(trans, _HTOTAL_A)
2012#define HBLANK(trans) _TRANSCODER2(trans, _HBLANK_A)
2013#define HSYNC(trans) _TRANSCODER2(trans, _HSYNC_A)
2014#define VTOTAL(trans) _TRANSCODER2(trans, _VTOTAL_A)
2015#define VBLANK(trans) _TRANSCODER2(trans, _VBLANK_A)
2016#define VSYNC(trans) _TRANSCODER2(trans, _VSYNC_A)
2017#define BCLRPAT(trans) _TRANSCODER2(trans, _BCLRPAT_A)
2018#define VSYNCSHIFT(trans) _TRANSCODER2(trans, _VSYNCSHIFT_A)
2019#define PIPESRC(trans) _TRANSCODER2(trans, _PIPEASRC)
2020
2021/* HSW+ eDP PSR registers */
2022#define EDP_PSR_BASE(dev) (IS_HASWELL(dev) ? 0x64800 : 0x6f800)
2023#define EDP_PSR_CTL(dev) (EDP_PSR_BASE(dev) + 0)
2024#define EDP_PSR_ENABLE (1<<31)
2025#define EDP_PSR_LINK_DISABLE (0<<27)
2026#define EDP_PSR_LINK_STANDBY (1<<27)
2027#define EDP_PSR_MIN_LINK_ENTRY_TIME_MASK (3<<25)
2028#define EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES (0<<25)
2029#define EDP_PSR_MIN_LINK_ENTRY_TIME_4_LINES (1<<25)
2030#define EDP_PSR_MIN_LINK_ENTRY_TIME_2_LINES (2<<25)
2031#define EDP_PSR_MIN_LINK_ENTRY_TIME_0_LINES (3<<25)
2032#define EDP_PSR_MAX_SLEEP_TIME_SHIFT 20
2033#define EDP_PSR_SKIP_AUX_EXIT (1<<12)
2034#define EDP_PSR_TP1_TP2_SEL (0<<11)
2035#define EDP_PSR_TP1_TP3_SEL (1<<11)
2036#define EDP_PSR_TP2_TP3_TIME_500us (0<<8)
2037#define EDP_PSR_TP2_TP3_TIME_100us (1<<8)
2038#define EDP_PSR_TP2_TP3_TIME_2500us (2<<8)
2039#define EDP_PSR_TP2_TP3_TIME_0us (3<<8)
2040#define EDP_PSR_TP1_TIME_500us (0<<4)
2041#define EDP_PSR_TP1_TIME_100us (1<<4)
2042#define EDP_PSR_TP1_TIME_2500us (2<<4)
2043#define EDP_PSR_TP1_TIME_0us (3<<4)
2044#define EDP_PSR_IDLE_FRAME_SHIFT 0
2045
2046#define EDP_PSR_AUX_CTL(dev) (EDP_PSR_BASE(dev) + 0x10)
2047#define EDP_PSR_AUX_DATA1(dev) (EDP_PSR_BASE(dev) + 0x14)
2048#define EDP_PSR_DPCD_COMMAND 0x80060000
2049#define EDP_PSR_AUX_DATA2(dev) (EDP_PSR_BASE(dev) + 0x18)
2050#define EDP_PSR_DPCD_NORMAL_OPERATION (1<<24)
2051#define EDP_PSR_AUX_DATA3(dev) (EDP_PSR_BASE(dev) + 0x1c)
2052#define EDP_PSR_AUX_DATA4(dev) (EDP_PSR_BASE(dev) + 0x20)
2053#define EDP_PSR_AUX_DATA5(dev) (EDP_PSR_BASE(dev) + 0x24)
2054
2055#define EDP_PSR_STATUS_CTL(dev) (EDP_PSR_BASE(dev) + 0x40)
2056#define EDP_PSR_STATUS_STATE_MASK (7<<29)
2057#define EDP_PSR_STATUS_STATE_IDLE (0<<29)
2058#define EDP_PSR_STATUS_STATE_SRDONACK (1<<29)
2059#define EDP_PSR_STATUS_STATE_SRDENT (2<<29)
2060#define EDP_PSR_STATUS_STATE_BUFOFF (3<<29)
2061#define EDP_PSR_STATUS_STATE_BUFON (4<<29)
2062#define EDP_PSR_STATUS_STATE_AUXACK (5<<29)
2063#define EDP_PSR_STATUS_STATE_SRDOFFACK (6<<29)
2064#define EDP_PSR_STATUS_LINK_MASK (3<<26)
2065#define EDP_PSR_STATUS_LINK_FULL_OFF (0<<26)
2066#define EDP_PSR_STATUS_LINK_FULL_ON (1<<26)
2067#define EDP_PSR_STATUS_LINK_STANDBY (2<<26)
2068#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_SHIFT 20
2069#define EDP_PSR_STATUS_MAX_SLEEP_TIMER_MASK 0x1f
2070#define EDP_PSR_STATUS_COUNT_SHIFT 16
2071#define EDP_PSR_STATUS_COUNT_MASK 0xf
2072#define EDP_PSR_STATUS_AUX_ERROR (1<<15)
2073#define EDP_PSR_STATUS_AUX_SENDING (1<<12)
2074#define EDP_PSR_STATUS_SENDING_IDLE (1<<9)
2075#define EDP_PSR_STATUS_SENDING_TP2_TP3 (1<<8)
2076#define EDP_PSR_STATUS_SENDING_TP1 (1<<4)
2077#define EDP_PSR_STATUS_IDLE_MASK 0xf
2078
2079#define EDP_PSR_PERF_CNT(dev) (EDP_PSR_BASE(dev) + 0x44)
2080#define EDP_PSR_PERF_CNT_MASK 0xffffff
2081
2082#define EDP_PSR_DEBUG_CTL(dev) (EDP_PSR_BASE(dev) + 0x60)
2083#define EDP_PSR_DEBUG_MASK_LPSP (1<<27)
2084#define EDP_PSR_DEBUG_MASK_MEMUP (1<<26)
2085#define EDP_PSR_DEBUG_MASK_HPD (1<<25)
2086
2087/* VGA port control */
2088#define ADPA 0x61100
2089#define PCH_ADPA 0xe1100
2090#define VLV_ADPA (VLV_DISPLAY_BASE + ADPA)
2091
2092#define ADPA_DAC_ENABLE (1<<31)
2093#define ADPA_DAC_DISABLE 0
2094#define ADPA_PIPE_SELECT_MASK (1<<30)
2095#define ADPA_PIPE_A_SELECT 0
2096#define ADPA_PIPE_B_SELECT (1<<30)
2097#define ADPA_PIPE_SELECT(pipe) ((pipe) << 30)
2098/* CPT uses bits 29:30 for pch transcoder select */
2099#define ADPA_CRT_HOTPLUG_MASK 0x03ff0000 /* bit 25-16 */
2100#define ADPA_CRT_HOTPLUG_MONITOR_NONE (0<<24)
2101#define ADPA_CRT_HOTPLUG_MONITOR_MASK (3<<24)
2102#define ADPA_CRT_HOTPLUG_MONITOR_COLOR (3<<24)
2103#define ADPA_CRT_HOTPLUG_MONITOR_MONO (2<<24)
2104#define ADPA_CRT_HOTPLUG_ENABLE (1<<23)
2105#define ADPA_CRT_HOTPLUG_PERIOD_64 (0<<22)
2106#define ADPA_CRT_HOTPLUG_PERIOD_128 (1<<22)
2107#define ADPA_CRT_HOTPLUG_WARMUP_5MS (0<<21)
2108#define ADPA_CRT_HOTPLUG_WARMUP_10MS (1<<21)
2109#define ADPA_CRT_HOTPLUG_SAMPLE_2S (0<<20)
2110#define ADPA_CRT_HOTPLUG_SAMPLE_4S (1<<20)
2111#define ADPA_CRT_HOTPLUG_VOLTAGE_40 (0<<18)
2112#define ADPA_CRT_HOTPLUG_VOLTAGE_50 (1<<18)
2113#define ADPA_CRT_HOTPLUG_VOLTAGE_60 (2<<18)
2114#define ADPA_CRT_HOTPLUG_VOLTAGE_70 (3<<18)
2115#define ADPA_CRT_HOTPLUG_VOLREF_325MV (0<<17)
2116#define ADPA_CRT_HOTPLUG_VOLREF_475MV (1<<17)
2117#define ADPA_CRT_HOTPLUG_FORCE_TRIGGER (1<<16)
2118#define ADPA_USE_VGA_HVPOLARITY (1<<15)
2119#define ADPA_SETS_HVPOLARITY 0
2120#define ADPA_VSYNC_CNTL_DISABLE (1<<10)
2121#define ADPA_VSYNC_CNTL_ENABLE 0
2122#define ADPA_HSYNC_CNTL_DISABLE (1<<11)
2123#define ADPA_HSYNC_CNTL_ENABLE 0
2124#define ADPA_VSYNC_ACTIVE_HIGH (1<<4)
2125#define ADPA_VSYNC_ACTIVE_LOW 0
2126#define ADPA_HSYNC_ACTIVE_HIGH (1<<3)
2127#define ADPA_HSYNC_ACTIVE_LOW 0
2128#define ADPA_DPMS_MASK (~(3<<10))
2129#define ADPA_DPMS_ON (0<<10)
2130#define ADPA_DPMS_SUSPEND (1<<10)
2131#define ADPA_DPMS_STANDBY (2<<10)
2132#define ADPA_DPMS_OFF (3<<10)
2133
2134
2135/* Hotplug control (945+ only) */
2136#define PORT_HOTPLUG_EN (dev_priv->info.display_mmio_offset + 0x61110)
2137#define PORTB_HOTPLUG_INT_EN (1 << 29)
2138#define PORTC_HOTPLUG_INT_EN (1 << 28)
2139#define PORTD_HOTPLUG_INT_EN (1 << 27)
2140#define SDVOB_HOTPLUG_INT_EN (1 << 26)
2141#define SDVOC_HOTPLUG_INT_EN (1 << 25)
2142#define TV_HOTPLUG_INT_EN (1 << 18)
2143#define CRT_HOTPLUG_INT_EN (1 << 9)
2144#define HOTPLUG_INT_EN_MASK (PORTB_HOTPLUG_INT_EN | \
2145 PORTC_HOTPLUG_INT_EN | \
2146 PORTD_HOTPLUG_INT_EN | \
2147 SDVOC_HOTPLUG_INT_EN | \
2148 SDVOB_HOTPLUG_INT_EN | \
2149 CRT_HOTPLUG_INT_EN)
2150#define CRT_HOTPLUG_FORCE_DETECT (1 << 3)
2151#define CRT_HOTPLUG_ACTIVATION_PERIOD_32 (0 << 8)
2152/* must use period 64 on GM45 according to docs */
2153#define CRT_HOTPLUG_ACTIVATION_PERIOD_64 (1 << 8)
2154#define CRT_HOTPLUG_DAC_ON_TIME_2M (0 << 7)
2155#define CRT_HOTPLUG_DAC_ON_TIME_4M (1 << 7)
2156#define CRT_HOTPLUG_VOLTAGE_COMPARE_40 (0 << 5)
2157#define CRT_HOTPLUG_VOLTAGE_COMPARE_50 (1 << 5)
2158#define CRT_HOTPLUG_VOLTAGE_COMPARE_60 (2 << 5)
2159#define CRT_HOTPLUG_VOLTAGE_COMPARE_70 (3 << 5)
2160#define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK (3 << 5)
2161#define CRT_HOTPLUG_DETECT_DELAY_1G (0 << 4)
2162#define CRT_HOTPLUG_DETECT_DELAY_2G (1 << 4)
2163#define CRT_HOTPLUG_DETECT_VOLTAGE_325MV (0 << 2)
2164#define CRT_HOTPLUG_DETECT_VOLTAGE_475MV (1 << 2)
2165
2166#define PORT_HOTPLUG_STAT (dev_priv->info.display_mmio_offset + 0x61114)
2167/*
2168 * HDMI/DP bits are gen4+
2169 *
2170 * WARNING: Bspec for hpd status bits on gen4 seems to be completely confused.
2171 * Please check the detailed lore in the commit message for for experimental
2172 * evidence.
2173 */
2174#define PORTD_HOTPLUG_LIVE_STATUS_G4X (1 << 29)
2175#define PORTC_HOTPLUG_LIVE_STATUS_G4X (1 << 28)
2176#define PORTB_HOTPLUG_LIVE_STATUS_G4X (1 << 27)
2177/* VLV DP/HDMI bits again match Bspec */
2178#define PORTD_HOTPLUG_LIVE_STATUS_VLV (1 << 27)
2179#define PORTC_HOTPLUG_LIVE_STATUS_VLV (1 << 28)
2180#define PORTB_HOTPLUG_LIVE_STATUS_VLV (1 << 29)
2181#define PORTD_HOTPLUG_INT_STATUS (3 << 21)
2182#define PORTC_HOTPLUG_INT_STATUS (3 << 19)
2183#define PORTB_HOTPLUG_INT_STATUS (3 << 17)
2184/* CRT/TV common between gen3+ */
2185#define CRT_HOTPLUG_INT_STATUS (1 << 11)
2186#define TV_HOTPLUG_INT_STATUS (1 << 10)
2187#define CRT_HOTPLUG_MONITOR_MASK (3 << 8)
2188#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2189#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2190#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2191#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2192#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2193#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2194#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (7 << 4)
2195
2196/* SDVO is different across gen3/4 */
2197#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2198#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
2199/*
2200 * Bspec seems to be seriously misleaded about the SDVO hpd bits on i965g/gm,
2201 * since reality corrobates that they're the same as on gen3. But keep these
2202 * bits here (and the comment!) to help any other lost wanderers back onto the
2203 * right tracks.
2204 */
2205#define SDVOC_HOTPLUG_INT_STATUS_I965 (3 << 4)
2206#define SDVOB_HOTPLUG_INT_STATUS_I965 (3 << 2)
2207#define SDVOC_HOTPLUG_INT_STATUS_I915 (1 << 7)
2208#define SDVOB_HOTPLUG_INT_STATUS_I915 (1 << 6)
2209#define HOTPLUG_INT_STATUS_G4X (CRT_HOTPLUG_INT_STATUS | \
2210 SDVOB_HOTPLUG_INT_STATUS_G4X | \
2211 SDVOC_HOTPLUG_INT_STATUS_G4X | \
2212 PORTB_HOTPLUG_INT_STATUS | \
2213 PORTC_HOTPLUG_INT_STATUS | \
2214 PORTD_HOTPLUG_INT_STATUS)
2215
2216#define HOTPLUG_INT_STATUS_I915 (CRT_HOTPLUG_INT_STATUS | \
2217 SDVOB_HOTPLUG_INT_STATUS_I915 | \
2218 SDVOC_HOTPLUG_INT_STATUS_I915 | \
2219 PORTB_HOTPLUG_INT_STATUS | \
2220 PORTC_HOTPLUG_INT_STATUS | \
2221 PORTD_HOTPLUG_INT_STATUS)
2222
2223/* SDVO and HDMI port control.
2224 * The same register may be used for SDVO or HDMI */
2225#define GEN3_SDVOB 0x61140
2226#define GEN3_SDVOC 0x61160
2227#define GEN4_HDMIB GEN3_SDVOB
2228#define GEN4_HDMIC GEN3_SDVOC
2229#define PCH_SDVOB 0xe1140
2230#define PCH_HDMIB PCH_SDVOB
2231#define PCH_HDMIC 0xe1150
2232#define PCH_HDMID 0xe1160
2233
2234#define PORT_DFT_I9XX 0x61150
2235#define DC_BALANCE_RESET (1 << 25)
2236#define PORT_DFT2_G4X 0x61154
2237#define DC_BALANCE_RESET_VLV (1 << 31)
2238#define PIPE_SCRAMBLE_RESET_MASK (0x3 << 0)
2239#define PIPE_B_SCRAMBLE_RESET (1 << 1)
2240#define PIPE_A_SCRAMBLE_RESET (1 << 0)
2241
2242/* Gen 3 SDVO bits: */
2243#define SDVO_ENABLE (1 << 31)
2244#define SDVO_PIPE_SEL(pipe) ((pipe) << 30)
2245#define SDVO_PIPE_SEL_MASK (1 << 30)
2246#define SDVO_PIPE_B_SELECT (1 << 30)
2247#define SDVO_STALL_SELECT (1 << 29)
2248#define SDVO_INTERRUPT_ENABLE (1 << 26)
2249/**
2250 * 915G/GM SDVO pixel multiplier.
2251 * Programmed value is multiplier - 1, up to 5x.
2252 * \sa DPLL_MD_UDI_MULTIPLIER_MASK
2253 */
2254#define SDVO_PORT_MULTIPLY_MASK (7 << 23)
2255#define SDVO_PORT_MULTIPLY_SHIFT 23
2256#define SDVO_PHASE_SELECT_MASK (15 << 19)
2257#define SDVO_PHASE_SELECT_DEFAULT (6 << 19)
2258#define SDVO_CLOCK_OUTPUT_INVERT (1 << 18)
2259#define SDVOC_GANG_MODE (1 << 16) /* Port C only */
2260#define SDVO_BORDER_ENABLE (1 << 7) /* SDVO only */
2261#define SDVOB_PCIE_CONCURRENCY (1 << 3) /* Port B only */
2262#define SDVO_DETECTED (1 << 2)
2263/* Bits to be preserved when writing */
2264#define SDVOB_PRESERVE_MASK ((1 << 17) | (1 << 16) | (1 << 14) | \
2265 SDVO_INTERRUPT_ENABLE)
2266#define SDVOC_PRESERVE_MASK ((1 << 17) | SDVO_INTERRUPT_ENABLE)
2267
2268/* Gen 4 SDVO/HDMI bits: */
2269#define SDVO_COLOR_FORMAT_8bpc (0 << 26)
2270#define SDVO_COLOR_FORMAT_MASK (7 << 26)
2271#define SDVO_ENCODING_SDVO (0 << 10)
2272#define SDVO_ENCODING_HDMI (2 << 10)
2273#define HDMI_MODE_SELECT_HDMI (1 << 9) /* HDMI only */
2274#define HDMI_MODE_SELECT_DVI (0 << 9) /* HDMI only */
2275#define HDMI_COLOR_RANGE_16_235 (1 << 8) /* HDMI only */
2276#define SDVO_AUDIO_ENABLE (1 << 6)
2277/* VSYNC/HSYNC bits new with 965, default is to be set */
2278#define SDVO_VSYNC_ACTIVE_HIGH (1 << 4)
2279#define SDVO_HSYNC_ACTIVE_HIGH (1 << 3)
2280
2281/* Gen 5 (IBX) SDVO/HDMI bits: */
2282#define HDMI_COLOR_FORMAT_12bpc (3 << 26) /* HDMI only */
2283#define SDVOB_HOTPLUG_ENABLE (1 << 23) /* SDVO only */
2284
2285/* Gen 6 (CPT) SDVO/HDMI bits: */
2286#define SDVO_PIPE_SEL_CPT(pipe) ((pipe) << 29)
2287#define SDVO_PIPE_SEL_MASK_CPT (3 << 29)
2288
2289
2290/* DVO port control */
2291#define DVOA 0x61120
2292#define DVOB 0x61140
2293#define DVOC 0x61160
2294#define DVO_ENABLE (1 << 31)
2295#define DVO_PIPE_B_SELECT (1 << 30)
2296#define DVO_PIPE_STALL_UNUSED (0 << 28)
2297#define DVO_PIPE_STALL (1 << 28)
2298#define DVO_PIPE_STALL_TV (2 << 28)
2299#define DVO_PIPE_STALL_MASK (3 << 28)
2300#define DVO_USE_VGA_SYNC (1 << 15)
2301#define DVO_DATA_ORDER_I740 (0 << 14)
2302#define DVO_DATA_ORDER_FP (1 << 14)
2303#define DVO_VSYNC_DISABLE (1 << 11)
2304#define DVO_HSYNC_DISABLE (1 << 10)
2305#define DVO_VSYNC_TRISTATE (1 << 9)
2306#define DVO_HSYNC_TRISTATE (1 << 8)
2307#define DVO_BORDER_ENABLE (1 << 7)
2308#define DVO_DATA_ORDER_GBRG (1 << 6)
2309#define DVO_DATA_ORDER_RGGB (0 << 6)
2310#define DVO_DATA_ORDER_GBRG_ERRATA (0 << 6)
2311#define DVO_DATA_ORDER_RGGB_ERRATA (1 << 6)
2312#define DVO_VSYNC_ACTIVE_HIGH (1 << 4)
2313#define DVO_HSYNC_ACTIVE_HIGH (1 << 3)
2314#define DVO_BLANK_ACTIVE_HIGH (1 << 2)
2315#define DVO_OUTPUT_CSTATE_PIXELS (1 << 1) /* SDG only */
2316#define DVO_OUTPUT_SOURCE_SIZE_PIXELS (1 << 0) /* SDG only */
2317#define DVO_PRESERVE_MASK (0x7<<24)
2318#define DVOA_SRCDIM 0x61124
2319#define DVOB_SRCDIM 0x61144
2320#define DVOC_SRCDIM 0x61164
2321#define DVO_SRCDIM_HORIZONTAL_SHIFT 12
2322#define DVO_SRCDIM_VERTICAL_SHIFT 0
2323
2324/* LVDS port control */
2325#define LVDS 0x61180
2326/*
2327 * Enables the LVDS port. This bit must be set before DPLLs are enabled, as
2328 * the DPLL semantics change when the LVDS is assigned to that pipe.
2329 */
2330#define LVDS_PORT_EN (1 << 31)
2331/* Selects pipe B for LVDS data. Must be set on pre-965. */
2332#define LVDS_PIPEB_SELECT (1 << 30)
2333#define LVDS_PIPE_MASK (1 << 30)
2334#define LVDS_PIPE(pipe) ((pipe) << 30)
2335/* LVDS dithering flag on 965/g4x platform */
2336#define LVDS_ENABLE_DITHER (1 << 25)
2337/* LVDS sync polarity flags. Set to invert (i.e. negative) */
2338#define LVDS_VSYNC_POLARITY (1 << 21)
2339#define LVDS_HSYNC_POLARITY (1 << 20)
2340
2341/* Enable border for unscaled (or aspect-scaled) display */
2342#define LVDS_BORDER_ENABLE (1 << 15)
2343/*
2344 * Enables the A0-A2 data pairs and CLKA, containing 18 bits of color data per
2345 * pixel.
2346 */
2347#define LVDS_A0A2_CLKA_POWER_MASK (3 << 8)
2348#define LVDS_A0A2_CLKA_POWER_DOWN (0 << 8)
2349#define LVDS_A0A2_CLKA_POWER_UP (3 << 8)
2350/*
2351 * Controls the A3 data pair, which contains the additional LSBs for 24 bit
2352 * mode. Only enabled if LVDS_A0A2_CLKA_POWER_UP also indicates it should be
2353 * on.
2354 */
2355#define LVDS_A3_POWER_MASK (3 << 6)
2356#define LVDS_A3_POWER_DOWN (0 << 6)
2357#define LVDS_A3_POWER_UP (3 << 6)
2358/*
2359 * Controls the CLKB pair. This should only be set when LVDS_B0B3_POWER_UP
2360 * is set.
2361 */
2362#define LVDS_CLKB_POWER_MASK (3 << 4)
2363#define LVDS_CLKB_POWER_DOWN (0 << 4)
2364#define LVDS_CLKB_POWER_UP (3 << 4)
2365/*
2366 * Controls the B0-B3 data pairs. This must be set to match the DPLL p2
2367 * setting for whether we are in dual-channel mode. The B3 pair will
2368 * additionally only be powered up when LVDS_A3_POWER_UP is set.
2369 */
2370#define LVDS_B0B3_POWER_MASK (3 << 2)
2371#define LVDS_B0B3_POWER_DOWN (0 << 2)
2372#define LVDS_B0B3_POWER_UP (3 << 2)
2373
2374/* Video Data Island Packet control */
2375#define VIDEO_DIP_DATA 0x61178
2376/* Read the description of VIDEO_DIP_DATA (before Haswel) or VIDEO_DIP_ECC
2377 * (Haswell and newer) to see which VIDEO_DIP_DATA byte corresponds to each byte
2378 * of the infoframe structure specified by CEA-861. */
2379#define VIDEO_DIP_DATA_SIZE 32
2380#define VIDEO_DIP_VSC_DATA_SIZE 36
2381#define VIDEO_DIP_CTL 0x61170
2382/* Pre HSW: */
2383#define VIDEO_DIP_ENABLE (1 << 31)
2384#define VIDEO_DIP_PORT(port) ((port) << 29)
2385#define VIDEO_DIP_PORT_MASK (3 << 29)
2386#define VIDEO_DIP_ENABLE_GCP (1 << 25)
2387#define VIDEO_DIP_ENABLE_AVI (1 << 21)
2388#define VIDEO_DIP_ENABLE_VENDOR (2 << 21)
2389#define VIDEO_DIP_ENABLE_GAMUT (4 << 21)
2390#define VIDEO_DIP_ENABLE_SPD (8 << 21)
2391#define VIDEO_DIP_SELECT_AVI (0 << 19)
2392#define VIDEO_DIP_SELECT_VENDOR (1 << 19)
2393#define VIDEO_DIP_SELECT_SPD (3 << 19)
2394#define VIDEO_DIP_SELECT_MASK (3 << 19)
2395#define VIDEO_DIP_FREQ_ONCE (0 << 16)
2396#define VIDEO_DIP_FREQ_VSYNC (1 << 16)
2397#define VIDEO_DIP_FREQ_2VSYNC (2 << 16)
2398#define VIDEO_DIP_FREQ_MASK (3 << 16)
2399/* HSW and later: */
2400#define VIDEO_DIP_ENABLE_VSC_HSW (1 << 20)
2401#define VIDEO_DIP_ENABLE_GCP_HSW (1 << 16)
2402#define VIDEO_DIP_ENABLE_AVI_HSW (1 << 12)
2403#define VIDEO_DIP_ENABLE_VS_HSW (1 << 8)
2404#define VIDEO_DIP_ENABLE_GMP_HSW (1 << 4)
2405#define VIDEO_DIP_ENABLE_SPD_HSW (1 << 0)
2406
2407/* Panel power sequencing */
2408#define PP_STATUS 0x61200
2409#define PP_ON (1 << 31)
2410/*
2411 * Indicates that all dependencies of the panel are on:
2412 *
2413 * - PLL enabled
2414 * - pipe enabled
2415 * - LVDS/DVOB/DVOC on
2416 */
2417#define PP_READY (1 << 30)
2418#define PP_SEQUENCE_NONE (0 << 28)
2419#define PP_SEQUENCE_POWER_UP (1 << 28)
2420#define PP_SEQUENCE_POWER_DOWN (2 << 28)
2421#define PP_SEQUENCE_MASK (3 << 28)
2422#define PP_SEQUENCE_SHIFT 28
2423#define PP_CYCLE_DELAY_ACTIVE (1 << 27)
2424#define PP_SEQUENCE_STATE_MASK 0x0000000f
2425#define PP_SEQUENCE_STATE_OFF_IDLE (0x0 << 0)
2426#define PP_SEQUENCE_STATE_OFF_S0_1 (0x1 << 0)
2427#define PP_SEQUENCE_STATE_OFF_S0_2 (0x2 << 0)
2428#define PP_SEQUENCE_STATE_OFF_S0_3 (0x3 << 0)
2429#define PP_SEQUENCE_STATE_ON_IDLE (0x8 << 0)
2430#define PP_SEQUENCE_STATE_ON_S1_0 (0x9 << 0)
2431#define PP_SEQUENCE_STATE_ON_S1_2 (0xa << 0)
2432#define PP_SEQUENCE_STATE_ON_S1_3 (0xb << 0)
2433#define PP_SEQUENCE_STATE_RESET (0xf << 0)
2434#define PP_CONTROL 0x61204
2435#define POWER_TARGET_ON (1 << 0)
2436#define PP_ON_DELAYS 0x61208
2437#define PP_OFF_DELAYS 0x6120c
2438#define PP_DIVISOR 0x61210
2439
2440/* Panel fitting */
2441#define PFIT_CONTROL (dev_priv->info.display_mmio_offset + 0x61230)
2442#define PFIT_ENABLE (1 << 31)
2443#define PFIT_PIPE_MASK (3 << 29)
2444#define PFIT_PIPE_SHIFT 29
2445#define VERT_INTERP_DISABLE (0 << 10)
2446#define VERT_INTERP_BILINEAR (1 << 10)
2447#define VERT_INTERP_MASK (3 << 10)
2448#define VERT_AUTO_SCALE (1 << 9)
2449#define HORIZ_INTERP_DISABLE (0 << 6)
2450#define HORIZ_INTERP_BILINEAR (1 << 6)
2451#define HORIZ_INTERP_MASK (3 << 6)
2452#define HORIZ_AUTO_SCALE (1 << 5)
2453#define PANEL_8TO6_DITHER_ENABLE (1 << 3)
2454#define PFIT_FILTER_FUZZY (0 << 24)
2455#define PFIT_SCALING_AUTO (0 << 26)
2456#define PFIT_SCALING_PROGRAMMED (1 << 26)
2457#define PFIT_SCALING_PILLAR (2 << 26)
2458#define PFIT_SCALING_LETTER (3 << 26)
2459#define PFIT_PGM_RATIOS (dev_priv->info.display_mmio_offset + 0x61234)
2460/* Pre-965 */
2461#define PFIT_VERT_SCALE_SHIFT 20
2462#define PFIT_VERT_SCALE_MASK 0xfff00000
2463#define PFIT_HORIZ_SCALE_SHIFT 4
2464#define PFIT_HORIZ_SCALE_MASK 0x0000fff0
2465/* 965+ */
2466#define PFIT_VERT_SCALE_SHIFT_965 16
2467#define PFIT_VERT_SCALE_MASK_965 0x1fff0000
2468#define PFIT_HORIZ_SCALE_SHIFT_965 0
2469#define PFIT_HORIZ_SCALE_MASK_965 0x00001fff
2470
2471#define PFIT_AUTO_RATIOS (dev_priv->info.display_mmio_offset + 0x61238)
2472
2473#define _VLV_BLC_PWM_CTL2_A (dev_priv->info.display_mmio_offset + 0x61250)
2474#define _VLV_BLC_PWM_CTL2_B (dev_priv->info.display_mmio_offset + 0x61350)
2475#define VLV_BLC_PWM_CTL2(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL2_A, \
2476 _VLV_BLC_PWM_CTL2_B)
2477
2478#define _VLV_BLC_PWM_CTL_A (dev_priv->info.display_mmio_offset + 0x61254)
2479#define _VLV_BLC_PWM_CTL_B (dev_priv->info.display_mmio_offset + 0x61354)
2480#define VLV_BLC_PWM_CTL(pipe) _PIPE(pipe, _VLV_BLC_PWM_CTL_A, \
2481 _VLV_BLC_PWM_CTL_B)
2482
2483#define _VLV_BLC_HIST_CTL_A (dev_priv->info.display_mmio_offset + 0x61260)
2484#define _VLV_BLC_HIST_CTL_B (dev_priv->info.display_mmio_offset + 0x61360)
2485#define VLV_BLC_HIST_CTL(pipe) _PIPE(pipe, _VLV_BLC_HIST_CTL_A, \
2486 _VLV_BLC_HIST_CTL_B)
2487
2488/* Backlight control */
2489#define BLC_PWM_CTL2 (dev_priv->info.display_mmio_offset + 0x61250) /* 965+ only */
2490#define BLM_PWM_ENABLE (1 << 31)
2491#define BLM_COMBINATION_MODE (1 << 30) /* gen4 only */
2492#define BLM_PIPE_SELECT (1 << 29)
2493#define BLM_PIPE_SELECT_IVB (3 << 29)
2494#define BLM_PIPE_A (0 << 29)
2495#define BLM_PIPE_B (1 << 29)
2496#define BLM_PIPE_C (2 << 29) /* ivb + */
2497#define BLM_TRANSCODER_A BLM_PIPE_A /* hsw */
2498#define BLM_TRANSCODER_B BLM_PIPE_B
2499#define BLM_TRANSCODER_C BLM_PIPE_C
2500#define BLM_TRANSCODER_EDP (3 << 29)
2501#define BLM_PIPE(pipe) ((pipe) << 29)
2502#define BLM_POLARITY_I965 (1 << 28) /* gen4 only */
2503#define BLM_PHASE_IN_INTERUPT_STATUS (1 << 26)
2504#define BLM_PHASE_IN_ENABLE (1 << 25)
2505#define BLM_PHASE_IN_INTERUPT_ENABL (1 << 24)
2506#define BLM_PHASE_IN_TIME_BASE_SHIFT (16)
2507#define BLM_PHASE_IN_TIME_BASE_MASK (0xff << 16)
2508#define BLM_PHASE_IN_COUNT_SHIFT (8)
2509#define BLM_PHASE_IN_COUNT_MASK (0xff << 8)
2510#define BLM_PHASE_IN_INCR_SHIFT (0)
2511#define BLM_PHASE_IN_INCR_MASK (0xff << 0)
2512#define BLC_PWM_CTL (dev_priv->info.display_mmio_offset + 0x61254)
2513/*
2514 * This is the most significant 15 bits of the number of backlight cycles in a
2515 * complete cycle of the modulated backlight control.
2516 *
2517 * The actual value is this field multiplied by two.
2518 */
2519#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
2520#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
2521#define BLM_LEGACY_MODE (1 << 16) /* gen2 only */
2522/*
2523 * This is the number of cycles out of the backlight modulation cycle for which
2524 * the backlight is on.
2525 *
2526 * This field must be no greater than the number of cycles in the complete
2527 * backlight modulation cycle.
2528 */
2529#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
2530#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
2531#define BACKLIGHT_DUTY_CYCLE_MASK_PNV (0xfffe)
2532#define BLM_POLARITY_PNV (1 << 0) /* pnv only */
2533
2534#define BLC_HIST_CTL (dev_priv->info.display_mmio_offset + 0x61260)
2535
2536/* New registers for PCH-split platforms. Safe where new bits show up, the
2537 * register layout machtes with gen4 BLC_PWM_CTL[12]. */
2538#define BLC_PWM_CPU_CTL2 0x48250
2539#define BLC_PWM_CPU_CTL 0x48254
2540
2541#define HSW_BLC_PWM2_CTL 0x48350
2542
2543/* PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
2544 * like the normal CTL from gen4 and earlier. Hooray for confusing naming. */
2545#define BLC_PWM_PCH_CTL1 0xc8250
2546#define BLM_PCH_PWM_ENABLE (1 << 31)
2547#define BLM_PCH_OVERRIDE_ENABLE (1 << 30)
2548#define BLM_PCH_POLARITY (1 << 29)
2549#define BLC_PWM_PCH_CTL2 0xc8254
2550
2551#define UTIL_PIN_CTL 0x48400
2552#define UTIL_PIN_ENABLE (1 << 31)
2553
2554#define PCH_GTC_CTL 0xe7000
2555#define PCH_GTC_ENABLE (1 << 31)
2556
2557/* TV port control */
2558#define TV_CTL 0x68000
2559/** Enables the TV encoder */
2560# define TV_ENC_ENABLE (1 << 31)
2561/** Sources the TV encoder input from pipe B instead of A. */
2562# define TV_ENC_PIPEB_SELECT (1 << 30)
2563/** Outputs composite video (DAC A only) */
2564# define TV_ENC_OUTPUT_COMPOSITE (0 << 28)
2565/** Outputs SVideo video (DAC B/C) */
2566# define TV_ENC_OUTPUT_SVIDEO (1 << 28)
2567/** Outputs Component video (DAC A/B/C) */
2568# define TV_ENC_OUTPUT_COMPONENT (2 << 28)
2569/** Outputs Composite and SVideo (DAC A/B/C) */
2570# define TV_ENC_OUTPUT_SVIDEO_COMPOSITE (3 << 28)
2571# define TV_TRILEVEL_SYNC (1 << 21)
2572/** Enables slow sync generation (945GM only) */
2573# define TV_SLOW_SYNC (1 << 20)
2574/** Selects 4x oversampling for 480i and 576p */
2575# define TV_OVERSAMPLE_4X (0 << 18)
2576/** Selects 2x oversampling for 720p and 1080i */
2577# define TV_OVERSAMPLE_2X (1 << 18)
2578/** Selects no oversampling for 1080p */
2579# define TV_OVERSAMPLE_NONE (2 << 18)
2580/** Selects 8x oversampling */
2581# define TV_OVERSAMPLE_8X (3 << 18)
2582/** Selects progressive mode rather than interlaced */
2583# define TV_PROGRESSIVE (1 << 17)
2584/** Sets the colorburst to PAL mode. Required for non-M PAL modes. */
2585# define TV_PAL_BURST (1 << 16)
2586/** Field for setting delay of Y compared to C */
2587# define TV_YC_SKEW_MASK (7 << 12)
2588/** Enables a fix for 480p/576p standard definition modes on the 915GM only */
2589# define TV_ENC_SDP_FIX (1 << 11)
2590/**
2591 * Enables a fix for the 915GM only.
2592 *
2593 * Not sure what it does.
2594 */
2595# define TV_ENC_C0_FIX (1 << 10)
2596/** Bits that must be preserved by software */
2597# define TV_CTL_SAVE ((1 << 11) | (3 << 9) | (7 << 6) | 0xf)
2598# define TV_FUSE_STATE_MASK (3 << 4)
2599/** Read-only state that reports all features enabled */
2600# define TV_FUSE_STATE_ENABLED (0 << 4)
2601/** Read-only state that reports that Macrovision is disabled in hardware*/
2602# define TV_FUSE_STATE_NO_MACROVISION (1 << 4)
2603/** Read-only state that reports that TV-out is disabled in hardware. */
2604# define TV_FUSE_STATE_DISABLED (2 << 4)
2605/** Normal operation */
2606# define TV_TEST_MODE_NORMAL (0 << 0)
2607/** Encoder test pattern 1 - combo pattern */
2608# define TV_TEST_MODE_PATTERN_1 (1 << 0)
2609/** Encoder test pattern 2 - full screen vertical 75% color bars */
2610# define TV_TEST_MODE_PATTERN_2 (2 << 0)
2611/** Encoder test pattern 3 - full screen horizontal 75% color bars */
2612# define TV_TEST_MODE_PATTERN_3 (3 << 0)
2613/** Encoder test pattern 4 - random noise */
2614# define TV_TEST_MODE_PATTERN_4 (4 << 0)
2615/** Encoder test pattern 5 - linear color ramps */
2616# define TV_TEST_MODE_PATTERN_5 (5 << 0)
2617/**
2618 * This test mode forces the DACs to 50% of full output.
2619 *
2620 * This is used for load detection in combination with TVDAC_SENSE_MASK
2621 */
2622# define TV_TEST_MODE_MONITOR_DETECT (7 << 0)
2623# define TV_TEST_MODE_MASK (7 << 0)
2624
2625#define TV_DAC 0x68004
2626# define TV_DAC_SAVE 0x00ffff00
2627/**
2628 * Reports that DAC state change logic has reported change (RO).
2629 *
2630 * This gets cleared when TV_DAC_STATE_EN is cleared
2631*/
2632# define TVDAC_STATE_CHG (1 << 31)
2633# define TVDAC_SENSE_MASK (7 << 28)
2634/** Reports that DAC A voltage is above the detect threshold */
2635# define TVDAC_A_SENSE (1 << 30)
2636/** Reports that DAC B voltage is above the detect threshold */
2637# define TVDAC_B_SENSE (1 << 29)
2638/** Reports that DAC C voltage is above the detect threshold */
2639# define TVDAC_C_SENSE (1 << 28)
2640/**
2641 * Enables DAC state detection logic, for load-based TV detection.
2642 *
2643 * The PLL of the chosen pipe (in TV_CTL) must be running, and the encoder set
2644 * to off, for load detection to work.
2645 */
2646# define TVDAC_STATE_CHG_EN (1 << 27)
2647/** Sets the DAC A sense value to high */
2648# define TVDAC_A_SENSE_CTL (1 << 26)
2649/** Sets the DAC B sense value to high */
2650# define TVDAC_B_SENSE_CTL (1 << 25)
2651/** Sets the DAC C sense value to high */
2652# define TVDAC_C_SENSE_CTL (1 << 24)
2653/** Overrides the ENC_ENABLE and DAC voltage levels */
2654# define DAC_CTL_OVERRIDE (1 << 7)
2655/** Sets the slew rate. Must be preserved in software */
2656# define ENC_TVDAC_SLEW_FAST (1 << 6)
2657# define DAC_A_1_3_V (0 << 4)
2658# define DAC_A_1_1_V (1 << 4)
2659# define DAC_A_0_7_V (2 << 4)
2660# define DAC_A_MASK (3 << 4)
2661# define DAC_B_1_3_V (0 << 2)
2662# define DAC_B_1_1_V (1 << 2)
2663# define DAC_B_0_7_V (2 << 2)
2664# define DAC_B_MASK (3 << 2)
2665# define DAC_C_1_3_V (0 << 0)
2666# define DAC_C_1_1_V (1 << 0)
2667# define DAC_C_0_7_V (2 << 0)
2668# define DAC_C_MASK (3 << 0)
2669
2670/**
2671 * CSC coefficients are stored in a floating point format with 9 bits of
2672 * mantissa and 2 or 3 bits of exponent. The exponent is represented as 2**-n,
2673 * where 2-bit exponents are unsigned n, and 3-bit exponents are signed n with
2674 * -1 (0x3) being the only legal negative value.
2675 */
2676#define TV_CSC_Y 0x68010
2677# define TV_RY_MASK 0x07ff0000
2678# define TV_RY_SHIFT 16
2679# define TV_GY_MASK 0x00000fff
2680# define TV_GY_SHIFT 0
2681
2682#define TV_CSC_Y2 0x68014
2683# define TV_BY_MASK 0x07ff0000
2684# define TV_BY_SHIFT 16
2685/**
2686 * Y attenuation for component video.
2687 *
2688 * Stored in 1.9 fixed point.
2689 */
2690# define TV_AY_MASK 0x000003ff
2691# define TV_AY_SHIFT 0
2692
2693#define TV_CSC_U 0x68018
2694# define TV_RU_MASK 0x07ff0000
2695# define TV_RU_SHIFT 16
2696# define TV_GU_MASK 0x000007ff
2697# define TV_GU_SHIFT 0
2698
2699#define TV_CSC_U2 0x6801c
2700# define TV_BU_MASK 0x07ff0000
2701# define TV_BU_SHIFT 16
2702/**
2703 * U attenuation for component video.
2704 *
2705 * Stored in 1.9 fixed point.
2706 */
2707# define TV_AU_MASK 0x000003ff
2708# define TV_AU_SHIFT 0
2709
2710#define TV_CSC_V 0x68020
2711# define TV_RV_MASK 0x0fff0000
2712# define TV_RV_SHIFT 16
2713# define TV_GV_MASK 0x000007ff
2714# define TV_GV_SHIFT 0
2715
2716#define TV_CSC_V2 0x68024
2717# define TV_BV_MASK 0x07ff0000
2718# define TV_BV_SHIFT 16
2719/**
2720 * V attenuation for component video.
2721 *
2722 * Stored in 1.9 fixed point.
2723 */
2724# define TV_AV_MASK 0x000007ff
2725# define TV_AV_SHIFT 0
2726
2727#define TV_CLR_KNOBS 0x68028
2728/** 2s-complement brightness adjustment */
2729# define TV_BRIGHTNESS_MASK 0xff000000
2730# define TV_BRIGHTNESS_SHIFT 24
2731/** Contrast adjustment, as a 2.6 unsigned floating point number */
2732# define TV_CONTRAST_MASK 0x00ff0000
2733# define TV_CONTRAST_SHIFT 16
2734/** Saturation adjustment, as a 2.6 unsigned floating point number */
2735# define TV_SATURATION_MASK 0x0000ff00
2736# define TV_SATURATION_SHIFT 8
2737/** Hue adjustment, as an integer phase angle in degrees */
2738# define TV_HUE_MASK 0x000000ff
2739# define TV_HUE_SHIFT 0
2740
2741#define TV_CLR_LEVEL 0x6802c
2742/** Controls the DAC level for black */
2743# define TV_BLACK_LEVEL_MASK 0x01ff0000
2744# define TV_BLACK_LEVEL_SHIFT 16
2745/** Controls the DAC level for blanking */
2746# define TV_BLANK_LEVEL_MASK 0x000001ff
2747# define TV_BLANK_LEVEL_SHIFT 0
2748
2749#define TV_H_CTL_1 0x68030
2750/** Number of pixels in the hsync. */
2751# define TV_HSYNC_END_MASK 0x1fff0000
2752# define TV_HSYNC_END_SHIFT 16
2753/** Total number of pixels minus one in the line (display and blanking). */
2754# define TV_HTOTAL_MASK 0x00001fff
2755# define TV_HTOTAL_SHIFT 0
2756
2757#define TV_H_CTL_2 0x68034
2758/** Enables the colorburst (needed for non-component color) */
2759# define TV_BURST_ENA (1 << 31)
2760/** Offset of the colorburst from the start of hsync, in pixels minus one. */
2761# define TV_HBURST_START_SHIFT 16
2762# define TV_HBURST_START_MASK 0x1fff0000
2763/** Length of the colorburst */
2764# define TV_HBURST_LEN_SHIFT 0
2765# define TV_HBURST_LEN_MASK 0x0001fff
2766
2767#define TV_H_CTL_3 0x68038
2768/** End of hblank, measured in pixels minus one from start of hsync */
2769# define TV_HBLANK_END_SHIFT 16
2770# define TV_HBLANK_END_MASK 0x1fff0000
2771/** Start of hblank, measured in pixels minus one from start of hsync */
2772# define TV_HBLANK_START_SHIFT 0
2773# define TV_HBLANK_START_MASK 0x0001fff
2774
2775#define TV_V_CTL_1 0x6803c
2776/** XXX */
2777# define TV_NBR_END_SHIFT 16
2778# define TV_NBR_END_MASK 0x07ff0000
2779/** XXX */
2780# define TV_VI_END_F1_SHIFT 8
2781# define TV_VI_END_F1_MASK 0x00003f00
2782/** XXX */
2783# define TV_VI_END_F2_SHIFT 0
2784# define TV_VI_END_F2_MASK 0x0000003f
2785
2786#define TV_V_CTL_2 0x68040
2787/** Length of vsync, in half lines */
2788# define TV_VSYNC_LEN_MASK 0x07ff0000
2789# define TV_VSYNC_LEN_SHIFT 16
2790/** Offset of the start of vsync in field 1, measured in one less than the
2791 * number of half lines.
2792 */
2793# define TV_VSYNC_START_F1_MASK 0x00007f00
2794# define TV_VSYNC_START_F1_SHIFT 8
2795/**
2796 * Offset of the start of vsync in field 2, measured in one less than the
2797 * number of half lines.
2798 */
2799# define TV_VSYNC_START_F2_MASK 0x0000007f
2800# define TV_VSYNC_START_F2_SHIFT 0
2801
2802#define TV_V_CTL_3 0x68044
2803/** Enables generation of the equalization signal */
2804# define TV_EQUAL_ENA (1 << 31)
2805/** Length of vsync, in half lines */
2806# define TV_VEQ_LEN_MASK 0x007f0000
2807# define TV_VEQ_LEN_SHIFT 16
2808/** Offset of the start of equalization in field 1, measured in one less than
2809 * the number of half lines.
2810 */
2811# define TV_VEQ_START_F1_MASK 0x0007f00
2812# define TV_VEQ_START_F1_SHIFT 8
2813/**
2814 * Offset of the start of equalization in field 2, measured in one less than
2815 * the number of half lines.
2816 */
2817# define TV_VEQ_START_F2_MASK 0x000007f
2818# define TV_VEQ_START_F2_SHIFT 0
2819
2820#define TV_V_CTL_4 0x68048
2821/**
2822 * Offset to start of vertical colorburst, measured in one less than the
2823 * number of lines from vertical start.
2824 */
2825# define TV_VBURST_START_F1_MASK 0x003f0000
2826# define TV_VBURST_START_F1_SHIFT 16
2827/**
2828 * Offset to the end of vertical colorburst, measured in one less than the
2829 * number of lines from the start of NBR.
2830 */
2831# define TV_VBURST_END_F1_MASK 0x000000ff
2832# define TV_VBURST_END_F1_SHIFT 0
2833
2834#define TV_V_CTL_5 0x6804c
2835/**
2836 * Offset to start of vertical colorburst, measured in one less than the
2837 * number of lines from vertical start.
2838 */
2839# define TV_VBURST_START_F2_MASK 0x003f0000
2840# define TV_VBURST_START_F2_SHIFT 16
2841/**
2842 * Offset to the end of vertical colorburst, measured in one less than the
2843 * number of lines from the start of NBR.
2844 */
2845# define TV_VBURST_END_F2_MASK 0x000000ff
2846# define TV_VBURST_END_F2_SHIFT 0
2847
2848#define TV_V_CTL_6 0x68050
2849/**
2850 * Offset to start of vertical colorburst, measured in one less than the
2851 * number of lines from vertical start.
2852 */
2853# define TV_VBURST_START_F3_MASK 0x003f0000
2854# define TV_VBURST_START_F3_SHIFT 16
2855/**
2856 * Offset to the end of vertical colorburst, measured in one less than the
2857 * number of lines from the start of NBR.
2858 */
2859# define TV_VBURST_END_F3_MASK 0x000000ff
2860# define TV_VBURST_END_F3_SHIFT 0
2861
2862#define TV_V_CTL_7 0x68054
2863/**
2864 * Offset to start of vertical colorburst, measured in one less than the
2865 * number of lines from vertical start.
2866 */
2867# define TV_VBURST_START_F4_MASK 0x003f0000
2868# define TV_VBURST_START_F4_SHIFT 16
2869/**
2870 * Offset to the end of vertical colorburst, measured in one less than the
2871 * number of lines from the start of NBR.
2872 */
2873# define TV_VBURST_END_F4_MASK 0x000000ff
2874# define TV_VBURST_END_F4_SHIFT 0
2875
2876#define TV_SC_CTL_1 0x68060
2877/** Turns on the first subcarrier phase generation DDA */
2878# define TV_SC_DDA1_EN (1 << 31)
2879/** Turns on the first subcarrier phase generation DDA */
2880# define TV_SC_DDA2_EN (1 << 30)
2881/** Turns on the first subcarrier phase generation DDA */
2882# define TV_SC_DDA3_EN (1 << 29)
2883/** Sets the subcarrier DDA to reset frequency every other field */
2884# define TV_SC_RESET_EVERY_2 (0 << 24)
2885/** Sets the subcarrier DDA to reset frequency every fourth field */
2886# define TV_SC_RESET_EVERY_4 (1 << 24)
2887/** Sets the subcarrier DDA to reset frequency every eighth field */
2888# define TV_SC_RESET_EVERY_8 (2 << 24)
2889/** Sets the subcarrier DDA to never reset the frequency */
2890# define TV_SC_RESET_NEVER (3 << 24)
2891/** Sets the peak amplitude of the colorburst.*/
2892# define TV_BURST_LEVEL_MASK 0x00ff0000
2893# define TV_BURST_LEVEL_SHIFT 16
2894/** Sets the increment of the first subcarrier phase generation DDA */
2895# define TV_SCDDA1_INC_MASK 0x00000fff
2896# define TV_SCDDA1_INC_SHIFT 0
2897
2898#define TV_SC_CTL_2 0x68064
2899/** Sets the rollover for the second subcarrier phase generation DDA */
2900# define TV_SCDDA2_SIZE_MASK 0x7fff0000
2901# define TV_SCDDA2_SIZE_SHIFT 16
2902/** Sets the increent of the second subcarrier phase generation DDA */
2903# define TV_SCDDA2_INC_MASK 0x00007fff
2904# define TV_SCDDA2_INC_SHIFT 0
2905
2906#define TV_SC_CTL_3 0x68068
2907/** Sets the rollover for the third subcarrier phase generation DDA */
2908# define TV_SCDDA3_SIZE_MASK 0x7fff0000
2909# define TV_SCDDA3_SIZE_SHIFT 16
2910/** Sets the increent of the third subcarrier phase generation DDA */
2911# define TV_SCDDA3_INC_MASK 0x00007fff
2912# define TV_SCDDA3_INC_SHIFT 0
2913
2914#define TV_WIN_POS 0x68070
2915/** X coordinate of the display from the start of horizontal active */
2916# define TV_XPOS_MASK 0x1fff0000
2917# define TV_XPOS_SHIFT 16
2918/** Y coordinate of the display from the start of vertical active (NBR) */
2919# define TV_YPOS_MASK 0x00000fff
2920# define TV_YPOS_SHIFT 0
2921
2922#define TV_WIN_SIZE 0x68074
2923/** Horizontal size of the display window, measured in pixels*/
2924# define TV_XSIZE_MASK 0x1fff0000
2925# define TV_XSIZE_SHIFT 16
2926/**
2927 * Vertical size of the display window, measured in pixels.
2928 *
2929 * Must be even for interlaced modes.
2930 */
2931# define TV_YSIZE_MASK 0x00000fff
2932# define TV_YSIZE_SHIFT 0
2933
2934#define TV_FILTER_CTL_1 0x68080
2935/**
2936 * Enables automatic scaling calculation.
2937 *
2938 * If set, the rest of the registers are ignored, and the calculated values can
2939 * be read back from the register.
2940 */
2941# define TV_AUTO_SCALE (1 << 31)
2942/**
2943 * Disables the vertical filter.
2944 *
2945 * This is required on modes more than 1024 pixels wide */
2946# define TV_V_FILTER_BYPASS (1 << 29)
2947/** Enables adaptive vertical filtering */
2948# define TV_VADAPT (1 << 28)
2949# define TV_VADAPT_MODE_MASK (3 << 26)
2950/** Selects the least adaptive vertical filtering mode */
2951# define TV_VADAPT_MODE_LEAST (0 << 26)
2952/** Selects the moderately adaptive vertical filtering mode */
2953# define TV_VADAPT_MODE_MODERATE (1 << 26)
2954/** Selects the most adaptive vertical filtering mode */
2955# define TV_VADAPT_MODE_MOST (3 << 26)
2956/**
2957 * Sets the horizontal scaling factor.
2958 *
2959 * This should be the fractional part of the horizontal scaling factor divided
2960 * by the oversampling rate. TV_HSCALE should be less than 1, and set to:
2961 *
2962 * (src width - 1) / ((oversample * dest width) - 1)
2963 */
2964# define TV_HSCALE_FRAC_MASK 0x00003fff
2965# define TV_HSCALE_FRAC_SHIFT 0
2966
2967#define TV_FILTER_CTL_2 0x68084
2968/**
2969 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2970 *
2971 * TV_VSCALE should be (src height - 1) / ((interlace * dest height) - 1)
2972 */
2973# define TV_VSCALE_INT_MASK 0x00038000
2974# define TV_VSCALE_INT_SHIFT 15
2975/**
2976 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2977 *
2978 * \sa TV_VSCALE_INT_MASK
2979 */
2980# define TV_VSCALE_FRAC_MASK 0x00007fff
2981# define TV_VSCALE_FRAC_SHIFT 0
2982
2983#define TV_FILTER_CTL_3 0x68088
2984/**
2985 * Sets the integer part of the 3.15 fixed-point vertical scaling factor.
2986 *
2987 * TV_VSCALE should be (src height - 1) / (1/4 * (dest height - 1))
2988 *
2989 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2990 */
2991# define TV_VSCALE_IP_INT_MASK 0x00038000
2992# define TV_VSCALE_IP_INT_SHIFT 15
2993/**
2994 * Sets the fractional part of the 3.15 fixed-point vertical scaling factor.
2995 *
2996 * For progressive modes, TV_VSCALE_IP_INT should be set to zeroes.
2997 *
2998 * \sa TV_VSCALE_IP_INT_MASK
2999 */
3000# define TV_VSCALE_IP_FRAC_MASK 0x00007fff
3001# define TV_VSCALE_IP_FRAC_SHIFT 0
3002
3003#define TV_CC_CONTROL 0x68090
3004# define TV_CC_ENABLE (1 << 31)
3005/**
3006 * Specifies which field to send the CC data in.
3007 *
3008 * CC data is usually sent in field 0.
3009 */
3010# define TV_CC_FID_MASK (1 << 27)
3011# define TV_CC_FID_SHIFT 27
3012/** Sets the horizontal position of the CC data. Usually 135. */
3013# define TV_CC_HOFF_MASK 0x03ff0000
3014# define TV_CC_HOFF_SHIFT 16
3015/** Sets the vertical position of the CC data. Usually 21 */
3016# define TV_CC_LINE_MASK 0x0000003f
3017# define TV_CC_LINE_SHIFT 0
3018
3019#define TV_CC_DATA 0x68094
3020# define TV_CC_RDY (1 << 31)
3021/** Second word of CC data to be transmitted. */
3022# define TV_CC_DATA_2_MASK 0x007f0000
3023# define TV_CC_DATA_2_SHIFT 16
3024/** First word of CC data to be transmitted. */
3025# define TV_CC_DATA_1_MASK 0x0000007f
3026# define TV_CC_DATA_1_SHIFT 0
3027
3028#define TV_H_LUMA_0 0x68100
3029#define TV_H_LUMA_59 0x681ec
3030#define TV_H_CHROMA_0 0x68200
3031#define TV_H_CHROMA_59 0x682ec
3032#define TV_V_LUMA_0 0x68300
3033#define TV_V_LUMA_42 0x683a8
3034#define TV_V_CHROMA_0 0x68400
3035#define TV_V_CHROMA_42 0x684a8
3036
3037/* Display Port */
3038#define DP_A 0x64000 /* eDP */
3039#define DP_B 0x64100
3040#define DP_C 0x64200
3041#define DP_D 0x64300
3042
3043#define DP_PORT_EN (1 << 31)
3044#define DP_PIPEB_SELECT (1 << 30)
3045#define DP_PIPE_MASK (1 << 30)
3046
3047/* Link training mode - select a suitable mode for each stage */
3048#define DP_LINK_TRAIN_PAT_1 (0 << 28)
3049#define DP_LINK_TRAIN_PAT_2 (1 << 28)
3050#define DP_LINK_TRAIN_PAT_IDLE (2 << 28)
3051#define DP_LINK_TRAIN_OFF (3 << 28)
3052#define DP_LINK_TRAIN_MASK (3 << 28)
3053#define DP_LINK_TRAIN_SHIFT 28
3054
3055/* CPT Link training mode */
3056#define DP_LINK_TRAIN_PAT_1_CPT (0 << 8)
3057#define DP_LINK_TRAIN_PAT_2_CPT (1 << 8)
3058#define DP_LINK_TRAIN_PAT_IDLE_CPT (2 << 8)
3059#define DP_LINK_TRAIN_OFF_CPT (3 << 8)
3060#define DP_LINK_TRAIN_MASK_CPT (7 << 8)
3061#define DP_LINK_TRAIN_SHIFT_CPT 8
3062
3063/* Signal voltages. These are mostly controlled by the other end */
3064#define DP_VOLTAGE_0_4 (0 << 25)
3065#define DP_VOLTAGE_0_6 (1 << 25)
3066#define DP_VOLTAGE_0_8 (2 << 25)
3067#define DP_VOLTAGE_1_2 (3 << 25)
3068#define DP_VOLTAGE_MASK (7 << 25)
3069#define DP_VOLTAGE_SHIFT 25
3070
3071/* Signal pre-emphasis levels, like voltages, the other end tells us what
3072 * they want
3073 */
3074#define DP_PRE_EMPHASIS_0 (0 << 22)
3075#define DP_PRE_EMPHASIS_3_5 (1 << 22)
3076#define DP_PRE_EMPHASIS_6 (2 << 22)
3077#define DP_PRE_EMPHASIS_9_5 (3 << 22)
3078#define DP_PRE_EMPHASIS_MASK (7 << 22)
3079#define DP_PRE_EMPHASIS_SHIFT 22
3080
3081/* How many wires to use. I guess 3 was too hard */
3082#define DP_PORT_WIDTH(width) (((width) - 1) << 19)
3083#define DP_PORT_WIDTH_MASK (7 << 19)
3084
3085/* Mystic DPCD version 1.1 special mode */
3086#define DP_ENHANCED_FRAMING (1 << 18)
3087
3088/* eDP */
3089#define DP_PLL_FREQ_270MHZ (0 << 16)
3090#define DP_PLL_FREQ_160MHZ (1 << 16)
3091#define DP_PLL_FREQ_MASK (3 << 16)
3092
3093/** locked once port is enabled */
3094#define DP_PORT_REVERSAL (1 << 15)
3095
3096/* eDP */
3097#define DP_PLL_ENABLE (1 << 14)
3098
3099/** sends the clock on lane 15 of the PEG for debug */
3100#define DP_CLOCK_OUTPUT_ENABLE (1 << 13)
3101
3102#define DP_SCRAMBLING_DISABLE (1 << 12)
3103#define DP_SCRAMBLING_DISABLE_IRONLAKE (1 << 7)
3104
3105/** limit RGB values to avoid confusing TVs */
3106#define DP_COLOR_RANGE_16_235 (1 << 8)
3107
3108/** Turn on the audio link */
3109#define DP_AUDIO_OUTPUT_ENABLE (1 << 6)
3110
3111/** vs and hs sync polarity */
3112#define DP_SYNC_VS_HIGH (1 << 4)
3113#define DP_SYNC_HS_HIGH (1 << 3)
3114
3115/** A fantasy */
3116#define DP_DETECTED (1 << 2)
3117
3118/** The aux channel provides a way to talk to the
3119 * signal sink for DDC etc. Max packet size supported
3120 * is 20 bytes in each direction, hence the 5 fixed
3121 * data registers
3122 */
3123#define DPA_AUX_CH_CTL 0x64010
3124#define DPA_AUX_CH_DATA1 0x64014
3125#define DPA_AUX_CH_DATA2 0x64018
3126#define DPA_AUX_CH_DATA3 0x6401c
3127#define DPA_AUX_CH_DATA4 0x64020
3128#define DPA_AUX_CH_DATA5 0x64024
3129
3130#define DPB_AUX_CH_CTL 0x64110
3131#define DPB_AUX_CH_DATA1 0x64114
3132#define DPB_AUX_CH_DATA2 0x64118
3133#define DPB_AUX_CH_DATA3 0x6411c
3134#define DPB_AUX_CH_DATA4 0x64120
3135#define DPB_AUX_CH_DATA5 0x64124
3136
3137#define DPC_AUX_CH_CTL 0x64210
3138#define DPC_AUX_CH_DATA1 0x64214
3139#define DPC_AUX_CH_DATA2 0x64218
3140#define DPC_AUX_CH_DATA3 0x6421c
3141#define DPC_AUX_CH_DATA4 0x64220
3142#define DPC_AUX_CH_DATA5 0x64224
3143
3144#define DPD_AUX_CH_CTL 0x64310
3145#define DPD_AUX_CH_DATA1 0x64314
3146#define DPD_AUX_CH_DATA2 0x64318
3147#define DPD_AUX_CH_DATA3 0x6431c
3148#define DPD_AUX_CH_DATA4 0x64320
3149#define DPD_AUX_CH_DATA5 0x64324
3150
3151#define DP_AUX_CH_CTL_SEND_BUSY (1 << 31)
3152#define DP_AUX_CH_CTL_DONE (1 << 30)
3153#define DP_AUX_CH_CTL_INTERRUPT (1 << 29)
3154#define DP_AUX_CH_CTL_TIME_OUT_ERROR (1 << 28)
3155#define DP_AUX_CH_CTL_TIME_OUT_400us (0 << 26)
3156#define DP_AUX_CH_CTL_TIME_OUT_600us (1 << 26)
3157#define DP_AUX_CH_CTL_TIME_OUT_800us (2 << 26)
3158#define DP_AUX_CH_CTL_TIME_OUT_1600us (3 << 26)
3159#define DP_AUX_CH_CTL_TIME_OUT_MASK (3 << 26)
3160#define DP_AUX_CH_CTL_RECEIVE_ERROR (1 << 25)
3161#define DP_AUX_CH_CTL_MESSAGE_SIZE_MASK (0x1f << 20)
3162#define DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT 20
3163#define DP_AUX_CH_CTL_PRECHARGE_2US_MASK (0xf << 16)
3164#define DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT 16
3165#define DP_AUX_CH_CTL_AUX_AKSV_SELECT (1 << 15)
3166#define DP_AUX_CH_CTL_MANCHESTER_TEST (1 << 14)
3167#define DP_AUX_CH_CTL_SYNC_TEST (1 << 13)
3168#define DP_AUX_CH_CTL_DEGLITCH_TEST (1 << 12)
3169#define DP_AUX_CH_CTL_PRECHARGE_TEST (1 << 11)
3170#define DP_AUX_CH_CTL_BIT_CLOCK_2X_MASK (0x7ff)
3171#define DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT 0
3172
3173/*
3174 * Computing GMCH M and N values for the Display Port link
3175 *
3176 * GMCH M/N = dot clock * bytes per pixel / ls_clk * # of lanes
3177 *
3178 * ls_clk (we assume) is the DP link clock (1.62 or 2.7 GHz)
3179 *
3180 * The GMCH value is used internally
3181 *
3182 * bytes_per_pixel is the number of bytes coming out of the plane,
3183 * which is after the LUTs, so we want the bytes for our color format.
3184 * For our current usage, this is always 3, one byte for R, G and B.
3185 */
3186#define _PIPEA_DATA_M_G4X 0x70050
3187#define _PIPEB_DATA_M_G4X 0x71050
3188
3189/* Transfer unit size for display port - 1, default is 0x3f (for TU size 64) */
3190#define TU_SIZE(x) (((x)-1) << 25) /* default size 64 */
3191#define TU_SIZE_SHIFT 25
3192#define TU_SIZE_MASK (0x3f << 25)
3193
3194#define DATA_LINK_M_N_MASK (0xffffff)
3195#define DATA_LINK_N_MAX (0x800000)
3196
3197#define _PIPEA_DATA_N_G4X 0x70054
3198#define _PIPEB_DATA_N_G4X 0x71054
3199#define PIPE_GMCH_DATA_N_MASK (0xffffff)
3200
3201/*
3202 * Computing Link M and N values for the Display Port link
3203 *
3204 * Link M / N = pixel_clock / ls_clk
3205 *
3206 * (the DP spec calls pixel_clock the 'strm_clk')
3207 *
3208 * The Link value is transmitted in the Main Stream
3209 * Attributes and VB-ID.
3210 */
3211
3212#define _PIPEA_LINK_M_G4X 0x70060
3213#define _PIPEB_LINK_M_G4X 0x71060
3214#define PIPEA_DP_LINK_M_MASK (0xffffff)
3215
3216#define _PIPEA_LINK_N_G4X 0x70064
3217#define _PIPEB_LINK_N_G4X 0x71064
3218#define PIPEA_DP_LINK_N_MASK (0xffffff)
3219
3220#define PIPE_DATA_M_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_M_G4X, _PIPEB_DATA_M_G4X)
3221#define PIPE_DATA_N_G4X(pipe) _PIPE(pipe, _PIPEA_DATA_N_G4X, _PIPEB_DATA_N_G4X)
3222#define PIPE_LINK_M_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_M_G4X, _PIPEB_LINK_M_G4X)
3223#define PIPE_LINK_N_G4X(pipe) _PIPE(pipe, _PIPEA_LINK_N_G4X, _PIPEB_LINK_N_G4X)
3224
3225/* Display & cursor control */
3226
3227/* Pipe A */
3228#define _PIPEADSL 0x70000
3229#define DSL_LINEMASK_GEN2 0x00000fff
3230#define DSL_LINEMASK_GEN3 0x00001fff
3231#define _PIPEACONF 0x70008
3232#define PIPECONF_ENABLE (1<<31)
3233#define PIPECONF_DISABLE 0
3234#define PIPECONF_DOUBLE_WIDE (1<<30)
3235#define I965_PIPECONF_ACTIVE (1<<30)
3236#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv & pipe A only */
3237#define PIPECONF_FRAME_START_DELAY_MASK (3<<27)
3238#define PIPECONF_SINGLE_WIDE 0
3239#define PIPECONF_PIPE_UNLOCKED 0
3240#define PIPECONF_PIPE_LOCKED (1<<25)
3241#define PIPECONF_PALETTE 0
3242#define PIPECONF_GAMMA (1<<24)
3243#define PIPECONF_FORCE_BORDER (1<<25)
3244#define PIPECONF_INTERLACE_MASK (7 << 21)
3245#define PIPECONF_INTERLACE_MASK_HSW (3 << 21)
3246/* Note that pre-gen3 does not support interlaced display directly. Panel
3247 * fitting must be disabled on pre-ilk for interlaced. */
3248#define PIPECONF_PROGRESSIVE (0 << 21)
3249#define PIPECONF_INTERLACE_W_SYNC_SHIFT_PANEL (4 << 21) /* gen4 only */
3250#define PIPECONF_INTERLACE_W_SYNC_SHIFT (5 << 21) /* gen4 only */
3251#define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21)
3252#define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) /* gen3 only */
3253/* Ironlake and later have a complete new set of values for interlaced. PFIT
3254 * means panel fitter required, PF means progressive fetch, DBL means power
3255 * saving pixel doubling. */
3256#define PIPECONF_PFIT_PF_INTERLACED_ILK (1 << 21)
3257#define PIPECONF_INTERLACED_ILK (3 << 21)
3258#define PIPECONF_INTERLACED_DBL_ILK (4 << 21) /* ilk/snb only */
3259#define PIPECONF_PFIT_PF_INTERLACED_DBL_ILK (5 << 21) /* ilk/snb only */
3260#define PIPECONF_INTERLACE_MODE_MASK (7 << 21)
3261#define PIPECONF_CXSR_DOWNCLOCK (1<<16)
3262#define PIPECONF_COLOR_RANGE_SELECT (1 << 13)
3263#define PIPECONF_BPC_MASK (0x7 << 5)
3264#define PIPECONF_8BPC (0<<5)
3265#define PIPECONF_10BPC (1<<5)
3266#define PIPECONF_6BPC (2<<5)
3267#define PIPECONF_12BPC (3<<5)
3268#define PIPECONF_DITHER_EN (1<<4)
3269#define PIPECONF_DITHER_TYPE_MASK (0x0000000c)
3270#define PIPECONF_DITHER_TYPE_SP (0<<2)
3271#define PIPECONF_DITHER_TYPE_ST1 (1<<2)
3272#define PIPECONF_DITHER_TYPE_ST2 (2<<2)
3273#define PIPECONF_DITHER_TYPE_TEMP (3<<2)
3274#define _PIPEASTAT 0x70024
3275#define PIPE_FIFO_UNDERRUN_STATUS (1UL<<31)
3276#define SPRITE1_FLIP_DONE_INT_EN_VLV (1UL<<30)
3277#define PIPE_CRC_ERROR_ENABLE (1UL<<29)
3278#define PIPE_CRC_DONE_ENABLE (1UL<<28)
3279#define PIPE_GMBUS_EVENT_ENABLE (1UL<<27)
3280#define PLANE_FLIP_DONE_INT_EN_VLV (1UL<<26)
3281#define PIPE_HOTPLUG_INTERRUPT_ENABLE (1UL<<26)
3282#define PIPE_VSYNC_INTERRUPT_ENABLE (1UL<<25)
3283#define PIPE_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24)
3284#define PIPE_DPST_EVENT_ENABLE (1UL<<23)
3285#define SPRITE0_FLIP_DONE_INT_EN_VLV (1UL<<22)
3286#define PIPE_LEGACY_BLC_EVENT_ENABLE (1UL<<22)
3287#define PIPE_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21)
3288#define PIPE_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20)
3289#define PIPE_B_PSR_INTERRUPT_ENABLE_VLV (1UL<<19)
3290#define PIPE_HOTPLUG_TV_INTERRUPT_ENABLE (1UL<<18) /* pre-965 */
3291#define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */
3292#define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17)
3293#define PIPEA_HBLANK_INT_EN_VLV (1UL<<16)
3294#define PIPE_OVERLAY_UPDATED_ENABLE (1UL<<16)
3295#define SPRITE1_FLIP_DONE_INT_STATUS_VLV (1UL<<15)
3296#define SPRITE0_FLIP_DONE_INT_STATUS_VLV (1UL<<14)
3297#define PIPE_CRC_ERROR_INTERRUPT_STATUS (1UL<<13)
3298#define PIPE_CRC_DONE_INTERRUPT_STATUS (1UL<<12)
3299#define PIPE_GMBUS_INTERRUPT_STATUS (1UL<<11)
3300#define PLANE_FLIP_DONE_INT_STATUS_VLV (1UL<<10)
3301#define PIPE_HOTPLUG_INTERRUPT_STATUS (1UL<<10)
3302#define PIPE_VSYNC_INTERRUPT_STATUS (1UL<<9)
3303#define PIPE_DISPLAY_LINE_COMPARE_STATUS (1UL<<8)
3304#define PIPE_DPST_EVENT_STATUS (1UL<<7)
3305#define PIPE_LEGACY_BLC_EVENT_STATUS (1UL<<6)
3306#define PIPE_A_PSR_STATUS_VLV (1UL<<6)
3307#define PIPE_ODD_FIELD_INTERRUPT_STATUS (1UL<<5)
3308#define PIPE_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4)
3309#define PIPE_B_PSR_STATUS_VLV (1UL<<3)
3310#define PIPE_HOTPLUG_TV_INTERRUPT_STATUS (1UL<<2) /* pre-965 */
3311#define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */
3312#define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1)
3313#define PIPE_OVERLAY_UPDATED_STATUS (1UL<<0)
3314
3315#define PIPESTAT_INT_ENABLE_MASK 0x7fff0000
3316#define PIPESTAT_INT_STATUS_MASK 0x0000ffff
3317
3318#define PIPE_A_OFFSET 0x70000
3319#define PIPE_B_OFFSET 0x71000
3320#define PIPE_C_OFFSET 0x72000
3321/*
3322 * There's actually no pipe EDP. Some pipe registers have
3323 * simply shifted from the pipe to the transcoder, while
3324 * keeping their original offset. Thus we need PIPE_EDP_OFFSET
3325 * to access such registers in transcoder EDP.
3326 */
3327#define PIPE_EDP_OFFSET 0x7f000
3328
3329#define _PIPE2(pipe, reg) (dev_priv->info.pipe_offsets[pipe] - \
3330 dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
3331 dev_priv->info.display_mmio_offset)
3332
3333#define PIPECONF(pipe) _PIPE2(pipe, _PIPEACONF)
3334#define PIPEDSL(pipe) _PIPE2(pipe, _PIPEADSL)
3335#define PIPEFRAME(pipe) _PIPE2(pipe, _PIPEAFRAMEHIGH)
3336#define PIPEFRAMEPIXEL(pipe) _PIPE2(pipe, _PIPEAFRAMEPIXEL)
3337#define PIPESTAT(pipe) _PIPE2(pipe, _PIPEASTAT)
3338
3339#define _PIPE_MISC_A 0x70030
3340#define _PIPE_MISC_B 0x71030
3341#define PIPEMISC_DITHER_BPC_MASK (7<<5)
3342#define PIPEMISC_DITHER_8_BPC (0<<5)
3343#define PIPEMISC_DITHER_10_BPC (1<<5)
3344#define PIPEMISC_DITHER_6_BPC (2<<5)
3345#define PIPEMISC_DITHER_12_BPC (3<<5)
3346#define PIPEMISC_DITHER_ENABLE (1<<4)
3347#define PIPEMISC_DITHER_TYPE_MASK (3<<2)
3348#define PIPEMISC_DITHER_TYPE_SP (0<<2)
3349#define PIPEMISC(pipe) _PIPE2(pipe, _PIPE_MISC_A)
3350
3351#define VLV_DPFLIPSTAT (VLV_DISPLAY_BASE + 0x70028)
3352#define PIPEB_LINE_COMPARE_INT_EN (1<<29)
3353#define PIPEB_HLINE_INT_EN (1<<28)
3354#define PIPEB_VBLANK_INT_EN (1<<27)
3355#define SPRITED_FLIP_DONE_INT_EN (1<<26)
3356#define SPRITEC_FLIP_DONE_INT_EN (1<<25)
3357#define PLANEB_FLIP_DONE_INT_EN (1<<24)
3358#define PIPEA_LINE_COMPARE_INT_EN (1<<21)
3359#define PIPEA_HLINE_INT_EN (1<<20)
3360#define PIPEA_VBLANK_INT_EN (1<<19)
3361#define SPRITEB_FLIP_DONE_INT_EN (1<<18)
3362#define SPRITEA_FLIP_DONE_INT_EN (1<<17)
3363#define PLANEA_FLIPDONE_INT_EN (1<<16)
3364
3365#define DPINVGTT (VLV_DISPLAY_BASE + 0x7002c) /* VLV only */
3366#define CURSORB_INVALID_GTT_INT_EN (1<<23)
3367#define CURSORA_INVALID_GTT_INT_EN (1<<22)
3368#define SPRITED_INVALID_GTT_INT_EN (1<<21)
3369#define SPRITEC_INVALID_GTT_INT_EN (1<<20)
3370#define PLANEB_INVALID_GTT_INT_EN (1<<19)
3371#define SPRITEB_INVALID_GTT_INT_EN (1<<18)
3372#define SPRITEA_INVALID_GTT_INT_EN (1<<17)
3373#define PLANEA_INVALID_GTT_INT_EN (1<<16)
3374#define DPINVGTT_EN_MASK 0xff0000
3375#define CURSORB_INVALID_GTT_STATUS (1<<7)
3376#define CURSORA_INVALID_GTT_STATUS (1<<6)
3377#define SPRITED_INVALID_GTT_STATUS (1<<5)
3378#define SPRITEC_INVALID_GTT_STATUS (1<<4)
3379#define PLANEB_INVALID_GTT_STATUS (1<<3)
3380#define SPRITEB_INVALID_GTT_STATUS (1<<2)
3381#define SPRITEA_INVALID_GTT_STATUS (1<<1)
3382#define PLANEA_INVALID_GTT_STATUS (1<<0)
3383#define DPINVGTT_STATUS_MASK 0xff
3384
3385#define DSPARB 0x70030
3386#define DSPARB_CSTART_MASK (0x7f << 7)
3387#define DSPARB_CSTART_SHIFT 7
3388#define DSPARB_BSTART_MASK (0x7f)
3389#define DSPARB_BSTART_SHIFT 0
3390#define DSPARB_BEND_SHIFT 9 /* on 855 */
3391#define DSPARB_AEND_SHIFT 0
3392
3393#define DSPFW1 (dev_priv->info.display_mmio_offset + 0x70034)
3394#define DSPFW_SR_SHIFT 23
3395#define DSPFW_SR_MASK (0x1ff<<23)
3396#define DSPFW_CURSORB_SHIFT 16
3397#define DSPFW_CURSORB_MASK (0x3f<<16)
3398#define DSPFW_PLANEB_SHIFT 8
3399#define DSPFW_PLANEB_MASK (0x7f<<8)
3400#define DSPFW_PLANEA_MASK (0x7f)
3401#define DSPFW2 (dev_priv->info.display_mmio_offset + 0x70038)
3402#define DSPFW_CURSORA_MASK 0x00003f00
3403#define DSPFW_CURSORA_SHIFT 8
3404#define DSPFW_PLANEC_MASK (0x7f)
3405#define DSPFW3 (dev_priv->info.display_mmio_offset + 0x7003c)
3406#define DSPFW_HPLL_SR_EN (1<<31)
3407#define DSPFW_CURSOR_SR_SHIFT 24
3408#define PINEVIEW_SELF_REFRESH_EN (1<<30)
3409#define DSPFW_CURSOR_SR_MASK (0x3f<<24)
3410#define DSPFW_HPLL_CURSOR_SHIFT 16
3411#define DSPFW_HPLL_CURSOR_MASK (0x3f<<16)
3412#define DSPFW_HPLL_SR_MASK (0x1ff)
3413#define DSPFW4 (dev_priv->info.display_mmio_offset + 0x70070)
3414#define DSPFW7 (dev_priv->info.display_mmio_offset + 0x7007c)
3415
3416/* drain latency register values*/
3417#define DRAIN_LATENCY_PRECISION_32 32
3418#define DRAIN_LATENCY_PRECISION_16 16
3419#define VLV_DDL1 (VLV_DISPLAY_BASE + 0x70050)
3420#define DDL_CURSORA_PRECISION_32 (1<<31)
3421#define DDL_CURSORA_PRECISION_16 (0<<31)
3422#define DDL_CURSORA_SHIFT 24
3423#define DDL_PLANEA_PRECISION_32 (1<<7)
3424#define DDL_PLANEA_PRECISION_16 (0<<7)
3425#define VLV_DDL2 (VLV_DISPLAY_BASE + 0x70054)
3426#define DDL_CURSORB_PRECISION_32 (1<<31)
3427#define DDL_CURSORB_PRECISION_16 (0<<31)
3428#define DDL_CURSORB_SHIFT 24
3429#define DDL_PLANEB_PRECISION_32 (1<<7)
3430#define DDL_PLANEB_PRECISION_16 (0<<7)
3431
3432/* FIFO watermark sizes etc */
3433#define G4X_FIFO_LINE_SIZE 64
3434#define I915_FIFO_LINE_SIZE 64
3435#define I830_FIFO_LINE_SIZE 32
3436
3437#define VALLEYVIEW_FIFO_SIZE 255
3438#define G4X_FIFO_SIZE 127
3439#define I965_FIFO_SIZE 512
3440#define I945_FIFO_SIZE 127
3441#define I915_FIFO_SIZE 95
3442#define I855GM_FIFO_SIZE 127 /* In cachelines */
3443#define I830_FIFO_SIZE 95
3444
3445#define VALLEYVIEW_MAX_WM 0xff
3446#define G4X_MAX_WM 0x3f
3447#define I915_MAX_WM 0x3f
3448
3449#define PINEVIEW_DISPLAY_FIFO 512 /* in 64byte unit */
3450#define PINEVIEW_FIFO_LINE_SIZE 64
3451#define PINEVIEW_MAX_WM 0x1ff
3452#define PINEVIEW_DFT_WM 0x3f
3453#define PINEVIEW_DFT_HPLLOFF_WM 0
3454#define PINEVIEW_GUARD_WM 10
3455#define PINEVIEW_CURSOR_FIFO 64
3456#define PINEVIEW_CURSOR_MAX_WM 0x3f
3457#define PINEVIEW_CURSOR_DFT_WM 0
3458#define PINEVIEW_CURSOR_GUARD_WM 5
3459
3460#define VALLEYVIEW_CURSOR_MAX_WM 64
3461#define I965_CURSOR_FIFO 64
3462#define I965_CURSOR_MAX_WM 32
3463#define I965_CURSOR_DFT_WM 8
3464
3465/* define the Watermark register on Ironlake */
3466#define WM0_PIPEA_ILK 0x45100
3467#define WM0_PIPE_PLANE_MASK (0xffff<<16)
3468#define WM0_PIPE_PLANE_SHIFT 16
3469#define WM0_PIPE_SPRITE_MASK (0xff<<8)
3470#define WM0_PIPE_SPRITE_SHIFT 8
3471#define WM0_PIPE_CURSOR_MASK (0xff)
3472
3473#define WM0_PIPEB_ILK 0x45104
3474#define WM0_PIPEC_IVB 0x45200
3475#define WM1_LP_ILK 0x45108
3476#define WM1_LP_SR_EN (1<<31)
3477#define WM1_LP_LATENCY_SHIFT 24
3478#define WM1_LP_LATENCY_MASK (0x7f<<24)
3479#define WM1_LP_FBC_MASK (0xf<<20)
3480#define WM1_LP_FBC_SHIFT 20
3481#define WM1_LP_FBC_SHIFT_BDW 19
3482#define WM1_LP_SR_MASK (0x7ff<<8)
3483#define WM1_LP_SR_SHIFT 8
3484#define WM1_LP_CURSOR_MASK (0xff)
3485#define WM2_LP_ILK 0x4510c
3486#define WM2_LP_EN (1<<31)
3487#define WM3_LP_ILK 0x45110
3488#define WM3_LP_EN (1<<31)
3489#define WM1S_LP_ILK 0x45120
3490#define WM2S_LP_IVB 0x45124
3491#define WM3S_LP_IVB 0x45128
3492#define WM1S_LP_EN (1<<31)
3493
3494#define HSW_WM_LP_VAL(lat, fbc, pri, cur) \
3495 (WM3_LP_EN | ((lat) << WM1_LP_LATENCY_SHIFT) | \
3496 ((fbc) << WM1_LP_FBC_SHIFT) | ((pri) << WM1_LP_SR_SHIFT) | (cur))
3497
3498/* Memory latency timer register */
3499#define MLTR_ILK 0x11222
3500#define MLTR_WM1_SHIFT 0
3501#define MLTR_WM2_SHIFT 8
3502/* the unit of memory self-refresh latency time is 0.5us */
3503#define ILK_SRLT_MASK 0x3f
3504
3505
3506/* the address where we get all kinds of latency value */
3507#define SSKPD 0x5d10
3508#define SSKPD_WM_MASK 0x3f
3509#define SSKPD_WM0_SHIFT 0
3510#define SSKPD_WM1_SHIFT 8
3511#define SSKPD_WM2_SHIFT 16
3512#define SSKPD_WM3_SHIFT 24
3513
3514/*
3515 * The two pipe frame counter registers are not synchronized, so
3516 * reading a stable value is somewhat tricky. The following code
3517 * should work:
3518 *
3519 * do {
3520 * high1 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3521 * PIPE_FRAME_HIGH_SHIFT;
3522 * low1 = ((INREG(PIPEAFRAMEPIXEL) & PIPE_FRAME_LOW_MASK) >>
3523 * PIPE_FRAME_LOW_SHIFT);
3524 * high2 = ((INREG(PIPEAFRAMEHIGH) & PIPE_FRAME_HIGH_MASK) >>
3525 * PIPE_FRAME_HIGH_SHIFT);
3526 * } while (high1 != high2);
3527 * frame = (high1 << 8) | low1;
3528 */
3529#define _PIPEAFRAMEHIGH 0x70040
3530#define PIPE_FRAME_HIGH_MASK 0x0000ffff
3531#define PIPE_FRAME_HIGH_SHIFT 0
3532#define _PIPEAFRAMEPIXEL 0x70044
3533#define PIPE_FRAME_LOW_MASK 0xff000000
3534#define PIPE_FRAME_LOW_SHIFT 24
3535#define PIPE_PIXEL_MASK 0x00ffffff
3536#define PIPE_PIXEL_SHIFT 0
3537/* GM45+ just has to be different */
3538#define _PIPEA_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70040)
3539#define _PIPEA_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x70044)
3540#define PIPE_FRMCOUNT_GM45(pipe) _PIPE(pipe, _PIPEA_FRMCOUNT_GM45, _PIPEB_FRMCOUNT_GM45)
3541
3542/* Cursor A & B regs */
3543#define _CURACNTR (dev_priv->info.display_mmio_offset + 0x70080)
3544/* Old style CUR*CNTR flags (desktop 8xx) */
3545#define CURSOR_ENABLE 0x80000000
3546#define CURSOR_GAMMA_ENABLE 0x40000000
3547#define CURSOR_STRIDE_MASK 0x30000000
3548#define CURSOR_PIPE_CSC_ENABLE (1<<24)
3549#define CURSOR_FORMAT_SHIFT 24
3550#define CURSOR_FORMAT_MASK (0x07 << CURSOR_FORMAT_SHIFT)
3551#define CURSOR_FORMAT_2C (0x00 << CURSOR_FORMAT_SHIFT)
3552#define CURSOR_FORMAT_3C (0x01 << CURSOR_FORMAT_SHIFT)
3553#define CURSOR_FORMAT_4C (0x02 << CURSOR_FORMAT_SHIFT)
3554#define CURSOR_FORMAT_ARGB (0x04 << CURSOR_FORMAT_SHIFT)
3555#define CURSOR_FORMAT_XRGB (0x05 << CURSOR_FORMAT_SHIFT)
3556/* New style CUR*CNTR flags */
3557#define CURSOR_MODE 0x27
3558#define CURSOR_MODE_DISABLE 0x00
3559#define CURSOR_MODE_128_32B_AX 0x02
3560#define CURSOR_MODE_256_32B_AX 0x03
3561#define CURSOR_MODE_64_32B_AX 0x07
3562#define CURSOR_MODE_128_ARGB_AX ((1 << 5) | CURSOR_MODE_128_32B_AX)
3563#define CURSOR_MODE_256_ARGB_AX ((1 << 5) | CURSOR_MODE_256_32B_AX)
3564#define CURSOR_MODE_64_ARGB_AX ((1 << 5) | CURSOR_MODE_64_32B_AX)
3565#define MCURSOR_PIPE_SELECT (1 << 28)
3566#define MCURSOR_PIPE_A 0x00
3567#define MCURSOR_PIPE_B (1 << 28)
3568#define MCURSOR_GAMMA_ENABLE (1 << 26)
3569#define CURSOR_TRICKLE_FEED_DISABLE (1 << 14)
3570#define _CURABASE (dev_priv->info.display_mmio_offset + 0x70084)
3571#define _CURAPOS (dev_priv->info.display_mmio_offset + 0x70088)
3572#define CURSOR_POS_MASK 0x007FF
3573#define CURSOR_POS_SIGN 0x8000
3574#define CURSOR_X_SHIFT 0
3575#define CURSOR_Y_SHIFT 16
3576#define CURSIZE 0x700a0
3577#define _CURBCNTR (dev_priv->info.display_mmio_offset + 0x700c0)
3578#define _CURBBASE (dev_priv->info.display_mmio_offset + 0x700c4)
3579#define _CURBPOS (dev_priv->info.display_mmio_offset + 0x700c8)
3580
3581#define _CURBCNTR_IVB 0x71080
3582#define _CURBBASE_IVB 0x71084
3583#define _CURBPOS_IVB 0x71088
3584
3585#define CURCNTR(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR)
3586#define CURBASE(pipe) _PIPE(pipe, _CURABASE, _CURBBASE)
3587#define CURPOS(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS)
3588
3589#define CURCNTR_IVB(pipe) _PIPE(pipe, _CURACNTR, _CURBCNTR_IVB)
3590#define CURBASE_IVB(pipe) _PIPE(pipe, _CURABASE, _CURBBASE_IVB)
3591#define CURPOS_IVB(pipe) _PIPE(pipe, _CURAPOS, _CURBPOS_IVB)
3592
3593/* Display A control */
3594#define _DSPACNTR 0x70180
3595#define DISPLAY_PLANE_ENABLE (1<<31)
3596#define DISPLAY_PLANE_DISABLE 0
3597#define DISPPLANE_GAMMA_ENABLE (1<<30)
3598#define DISPPLANE_GAMMA_DISABLE 0
3599#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
3600#define DISPPLANE_YUV422 (0x0<<26)
3601#define DISPPLANE_8BPP (0x2<<26)
3602#define DISPPLANE_BGRA555 (0x3<<26)
3603#define DISPPLANE_BGRX555 (0x4<<26)
3604#define DISPPLANE_BGRX565 (0x5<<26)
3605#define DISPPLANE_BGRX888 (0x6<<26)
3606#define DISPPLANE_BGRA888 (0x7<<26)
3607#define DISPPLANE_RGBX101010 (0x8<<26)
3608#define DISPPLANE_RGBA101010 (0x9<<26)
3609#define DISPPLANE_BGRX101010 (0xa<<26)
3610#define DISPPLANE_RGBX161616 (0xc<<26)
3611#define DISPPLANE_RGBX888 (0xe<<26)
3612#define DISPPLANE_RGBA888 (0xf<<26)
3613#define DISPPLANE_STEREO_ENABLE (1<<25)
3614#define DISPPLANE_STEREO_DISABLE 0
3615#define DISPPLANE_PIPE_CSC_ENABLE (1<<24)
3616#define DISPPLANE_SEL_PIPE_SHIFT 24
3617#define DISPPLANE_SEL_PIPE_MASK (3<<DISPPLANE_SEL_PIPE_SHIFT)
3618#define DISPPLANE_SEL_PIPE_A 0
3619#define DISPPLANE_SEL_PIPE_B (1<<DISPPLANE_SEL_PIPE_SHIFT)
3620#define DISPPLANE_SRC_KEY_ENABLE (1<<22)
3621#define DISPPLANE_SRC_KEY_DISABLE 0
3622#define DISPPLANE_LINE_DOUBLE (1<<20)
3623#define DISPPLANE_NO_LINE_DOUBLE 0
3624#define DISPPLANE_STEREO_POLARITY_FIRST 0
3625#define DISPPLANE_STEREO_POLARITY_SECOND (1<<18)
3626#define DISPPLANE_TRICKLE_FEED_DISABLE (1<<14) /* Ironlake */
3627#define DISPPLANE_TILED (1<<10)
3628#define _DSPAADDR 0x70184
3629#define _DSPASTRIDE 0x70188
3630#define _DSPAPOS 0x7018C /* reserved */
3631#define _DSPASIZE 0x70190
3632#define _DSPASURF 0x7019C /* 965+ only */
3633#define _DSPATILEOFF 0x701A4 /* 965+ only */
3634#define _DSPAOFFSET 0x701A4 /* HSW */
3635#define _DSPASURFLIVE 0x701AC
3636
3637#define DSPCNTR(plane) _PIPE2(plane, _DSPACNTR)
3638#define DSPADDR(plane) _PIPE2(plane, _DSPAADDR)
3639#define DSPSTRIDE(plane) _PIPE2(plane, _DSPASTRIDE)
3640#define DSPPOS(plane) _PIPE2(plane, _DSPAPOS)
3641#define DSPSIZE(plane) _PIPE2(plane, _DSPASIZE)
3642#define DSPSURF(plane) _PIPE2(plane, _DSPASURF)
3643#define DSPTILEOFF(plane) _PIPE2(plane, _DSPATILEOFF)
3644#define DSPLINOFF(plane) DSPADDR(plane)
3645#define DSPOFFSET(plane) _PIPE2(plane, _DSPAOFFSET)
3646#define DSPSURFLIVE(plane) _PIPE2(plane, _DSPASURFLIVE)
3647
3648/* Display/Sprite base address macros */
3649#define DISP_BASEADDR_MASK (0xfffff000)
3650#define I915_LO_DISPBASE(val) (val & ~DISP_BASEADDR_MASK)
3651#define I915_HI_DISPBASE(val) (val & DISP_BASEADDR_MASK)
3652
3653/* VBIOS flags */
3654#define SWF00 (dev_priv->info.display_mmio_offset + 0x71410)
3655#define SWF01 (dev_priv->info.display_mmio_offset + 0x71414)
3656#define SWF02 (dev_priv->info.display_mmio_offset + 0x71418)
3657#define SWF03 (dev_priv->info.display_mmio_offset + 0x7141c)
3658#define SWF04 (dev_priv->info.display_mmio_offset + 0x71420)
3659#define SWF05 (dev_priv->info.display_mmio_offset + 0x71424)
3660#define SWF06 (dev_priv->info.display_mmio_offset + 0x71428)
3661#define SWF10 (dev_priv->info.display_mmio_offset + 0x70410)
3662#define SWF11 (dev_priv->info.display_mmio_offset + 0x70414)
3663#define SWF14 (dev_priv->info.display_mmio_offset + 0x71420)
3664#define SWF30 (dev_priv->info.display_mmio_offset + 0x72414)
3665#define SWF31 (dev_priv->info.display_mmio_offset + 0x72418)
3666#define SWF32 (dev_priv->info.display_mmio_offset + 0x7241c)
3667
3668/* Pipe B */
3669#define _PIPEBDSL (dev_priv->info.display_mmio_offset + 0x71000)
3670#define _PIPEBCONF (dev_priv->info.display_mmio_offset + 0x71008)
3671#define _PIPEBSTAT (dev_priv->info.display_mmio_offset + 0x71024)
3672#define _PIPEBFRAMEHIGH 0x71040
3673#define _PIPEBFRAMEPIXEL 0x71044
3674#define _PIPEB_FRMCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71040)
3675#define _PIPEB_FLIPCOUNT_GM45 (dev_priv->info.display_mmio_offset + 0x71044)
3676
3677
3678/* Display B control */
3679#define _DSPBCNTR (dev_priv->info.display_mmio_offset + 0x71180)
3680#define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15)
3681#define DISPPLANE_ALPHA_TRANS_DISABLE 0
3682#define DISPPLANE_SPRITE_ABOVE_DISPLAY 0
3683#define DISPPLANE_SPRITE_ABOVE_OVERLAY (1)
3684#define _DSPBADDR (dev_priv->info.display_mmio_offset + 0x71184)
3685#define _DSPBSTRIDE (dev_priv->info.display_mmio_offset + 0x71188)
3686#define _DSPBPOS (dev_priv->info.display_mmio_offset + 0x7118C)
3687#define _DSPBSIZE (dev_priv->info.display_mmio_offset + 0x71190)
3688#define _DSPBSURF (dev_priv->info.display_mmio_offset + 0x7119C)
3689#define _DSPBTILEOFF (dev_priv->info.display_mmio_offset + 0x711A4)
3690#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
3691#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
3692
3693/* Sprite A control */
3694#define _DVSACNTR 0x72180
3695#define DVS_ENABLE (1<<31)
3696#define DVS_GAMMA_ENABLE (1<<30)
3697#define DVS_PIXFORMAT_MASK (3<<25)
3698#define DVS_FORMAT_YUV422 (0<<25)
3699#define DVS_FORMAT_RGBX101010 (1<<25)
3700#define DVS_FORMAT_RGBX888 (2<<25)
3701#define DVS_FORMAT_RGBX161616 (3<<25)
3702#define DVS_PIPE_CSC_ENABLE (1<<24)
3703#define DVS_SOURCE_KEY (1<<22)
3704#define DVS_RGB_ORDER_XBGR (1<<20)
3705#define DVS_YUV_BYTE_ORDER_MASK (3<<16)
3706#define DVS_YUV_ORDER_YUYV (0<<16)
3707#define DVS_YUV_ORDER_UYVY (1<<16)
3708#define DVS_YUV_ORDER_YVYU (2<<16)
3709#define DVS_YUV_ORDER_VYUY (3<<16)
3710#define DVS_DEST_KEY (1<<2)
3711#define DVS_TRICKLE_FEED_DISABLE (1<<14)
3712#define DVS_TILED (1<<10)
3713#define _DVSALINOFF 0x72184
3714#define _DVSASTRIDE 0x72188
3715#define _DVSAPOS 0x7218c
3716#define _DVSASIZE 0x72190
3717#define _DVSAKEYVAL 0x72194
3718#define _DVSAKEYMSK 0x72198
3719#define _DVSASURF 0x7219c
3720#define _DVSAKEYMAXVAL 0x721a0
3721#define _DVSATILEOFF 0x721a4
3722#define _DVSASURFLIVE 0x721ac
3723#define _DVSASCALE 0x72204
3724#define DVS_SCALE_ENABLE (1<<31)
3725#define DVS_FILTER_MASK (3<<29)
3726#define DVS_FILTER_MEDIUM (0<<29)
3727#define DVS_FILTER_ENHANCING (1<<29)
3728#define DVS_FILTER_SOFTENING (2<<29)
3729#define DVS_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3730#define DVS_VERTICAL_OFFSET_ENABLE (1<<27)
3731#define _DVSAGAMC 0x72300
3732
3733#define _DVSBCNTR 0x73180
3734#define _DVSBLINOFF 0x73184
3735#define _DVSBSTRIDE 0x73188
3736#define _DVSBPOS 0x7318c
3737#define _DVSBSIZE 0x73190
3738#define _DVSBKEYVAL 0x73194
3739#define _DVSBKEYMSK 0x73198
3740#define _DVSBSURF 0x7319c
3741#define _DVSBKEYMAXVAL 0x731a0
3742#define _DVSBTILEOFF 0x731a4
3743#define _DVSBSURFLIVE 0x731ac
3744#define _DVSBSCALE 0x73204
3745#define _DVSBGAMC 0x73300
3746
3747#define DVSCNTR(pipe) _PIPE(pipe, _DVSACNTR, _DVSBCNTR)
3748#define DVSLINOFF(pipe) _PIPE(pipe, _DVSALINOFF, _DVSBLINOFF)
3749#define DVSSTRIDE(pipe) _PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE)
3750#define DVSPOS(pipe) _PIPE(pipe, _DVSAPOS, _DVSBPOS)
3751#define DVSSURF(pipe) _PIPE(pipe, _DVSASURF, _DVSBSURF)
3752#define DVSKEYMAX(pipe) _PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL)
3753#define DVSSIZE(pipe) _PIPE(pipe, _DVSASIZE, _DVSBSIZE)
3754#define DVSSCALE(pipe) _PIPE(pipe, _DVSASCALE, _DVSBSCALE)
3755#define DVSTILEOFF(pipe) _PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF)
3756#define DVSKEYVAL(pipe) _PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL)
3757#define DVSKEYMSK(pipe) _PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK)
3758#define DVSSURFLIVE(pipe) _PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE)
3759
3760#define _SPRA_CTL 0x70280
3761#define SPRITE_ENABLE (1<<31)
3762#define SPRITE_GAMMA_ENABLE (1<<30)
3763#define SPRITE_PIXFORMAT_MASK (7<<25)
3764#define SPRITE_FORMAT_YUV422 (0<<25)
3765#define SPRITE_FORMAT_RGBX101010 (1<<25)
3766#define SPRITE_FORMAT_RGBX888 (2<<25)
3767#define SPRITE_FORMAT_RGBX161616 (3<<25)
3768#define SPRITE_FORMAT_YUV444 (4<<25)
3769#define SPRITE_FORMAT_XR_BGR101010 (5<<25) /* Extended range */
3770#define SPRITE_PIPE_CSC_ENABLE (1<<24)
3771#define SPRITE_SOURCE_KEY (1<<22)
3772#define SPRITE_RGB_ORDER_RGBX (1<<20) /* only for 888 and 161616 */
3773#define SPRITE_YUV_TO_RGB_CSC_DISABLE (1<<19)
3774#define SPRITE_YUV_CSC_FORMAT_BT709 (1<<18) /* 0 is BT601 */
3775#define SPRITE_YUV_BYTE_ORDER_MASK (3<<16)
3776#define SPRITE_YUV_ORDER_YUYV (0<<16)
3777#define SPRITE_YUV_ORDER_UYVY (1<<16)
3778#define SPRITE_YUV_ORDER_YVYU (2<<16)
3779#define SPRITE_YUV_ORDER_VYUY (3<<16)
3780#define SPRITE_TRICKLE_FEED_DISABLE (1<<14)
3781#define SPRITE_INT_GAMMA_ENABLE (1<<13)
3782#define SPRITE_TILED (1<<10)
3783#define SPRITE_DEST_KEY (1<<2)
3784#define _SPRA_LINOFF 0x70284
3785#define _SPRA_STRIDE 0x70288
3786#define _SPRA_POS 0x7028c
3787#define _SPRA_SIZE 0x70290
3788#define _SPRA_KEYVAL 0x70294
3789#define _SPRA_KEYMSK 0x70298
3790#define _SPRA_SURF 0x7029c
3791#define _SPRA_KEYMAX 0x702a0
3792#define _SPRA_TILEOFF 0x702a4
3793#define _SPRA_OFFSET 0x702a4
3794#define _SPRA_SURFLIVE 0x702ac
3795#define _SPRA_SCALE 0x70304
3796#define SPRITE_SCALE_ENABLE (1<<31)
3797#define SPRITE_FILTER_MASK (3<<29)
3798#define SPRITE_FILTER_MEDIUM (0<<29)
3799#define SPRITE_FILTER_ENHANCING (1<<29)
3800#define SPRITE_FILTER_SOFTENING (2<<29)
3801#define SPRITE_VERTICAL_OFFSET_HALF (1<<28) /* must be enabled below */
3802#define SPRITE_VERTICAL_OFFSET_ENABLE (1<<27)
3803#define _SPRA_GAMC 0x70400
3804
3805#define _SPRB_CTL 0x71280
3806#define _SPRB_LINOFF 0x71284
3807#define _SPRB_STRIDE 0x71288
3808#define _SPRB_POS 0x7128c
3809#define _SPRB_SIZE 0x71290
3810#define _SPRB_KEYVAL 0x71294
3811#define _SPRB_KEYMSK 0x71298
3812#define _SPRB_SURF 0x7129c
3813#define _SPRB_KEYMAX 0x712a0
3814#define _SPRB_TILEOFF 0x712a4
3815#define _SPRB_OFFSET 0x712a4
3816#define _SPRB_SURFLIVE 0x712ac
3817#define _SPRB_SCALE 0x71304
3818#define _SPRB_GAMC 0x71400
3819
3820#define SPRCTL(pipe) _PIPE(pipe, _SPRA_CTL, _SPRB_CTL)
3821#define SPRLINOFF(pipe) _PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF)
3822#define SPRSTRIDE(pipe) _PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE)
3823#define SPRPOS(pipe) _PIPE(pipe, _SPRA_POS, _SPRB_POS)
3824#define SPRSIZE(pipe) _PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE)
3825#define SPRKEYVAL(pipe) _PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL)
3826#define SPRKEYMSK(pipe) _PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK)
3827#define SPRSURF(pipe) _PIPE(pipe, _SPRA_SURF, _SPRB_SURF)
3828#define SPRKEYMAX(pipe) _PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX)
3829#define SPRTILEOFF(pipe) _PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF)
3830#define SPROFFSET(pipe) _PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET)
3831#define SPRSCALE(pipe) _PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE)
3832#define SPRGAMC(pipe) _PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC)
3833#define SPRSURFLIVE(pipe) _PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE)
3834
3835#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3836#define SP_ENABLE (1<<31)
3837#define SP_GAMMA_ENABLE (1<<30)
3838#define SP_PIXFORMAT_MASK (0xf<<26)
3839#define SP_FORMAT_YUV422 (0<<26)
3840#define SP_FORMAT_BGR565 (5<<26)
3841#define SP_FORMAT_BGRX8888 (6<<26)
3842#define SP_FORMAT_BGRA8888 (7<<26)
3843#define SP_FORMAT_RGBX1010102 (8<<26)
3844#define SP_FORMAT_RGBA1010102 (9<<26)
3845#define SP_FORMAT_RGBX8888 (0xe<<26)
3846#define SP_FORMAT_RGBA8888 (0xf<<26)
3847#define SP_SOURCE_KEY (1<<22)
3848#define SP_YUV_BYTE_ORDER_MASK (3<<16)
3849#define SP_YUV_ORDER_YUYV (0<<16)
3850#define SP_YUV_ORDER_UYVY (1<<16)
3851#define SP_YUV_ORDER_YVYU (2<<16)
3852#define SP_YUV_ORDER_VYUY (3<<16)
3853#define SP_TILED (1<<10)
3854#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184)
3855#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188)
3856#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c)
3857#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190)
3858#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194)
3859#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198)
3860#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c)
3861#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0)
3862#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4)
3863#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8)
3864#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721f4)
3865
3866#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280)
3867#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284)
3868#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288)
3869#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c)
3870#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290)
3871#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294)
3872#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298)
3873#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c)
3874#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0)
3875#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4)
3876#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8)
3877#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722f4)
3878
3879#define SPCNTR(pipe, plane) _PIPE(pipe * 2 + plane, _SPACNTR, _SPBCNTR)
3880#define SPLINOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPALINOFF, _SPBLINOFF)
3881#define SPSTRIDE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASTRIDE, _SPBSTRIDE)
3882#define SPPOS(pipe, plane) _PIPE(pipe * 2 + plane, _SPAPOS, _SPBPOS)
3883#define SPSIZE(pipe, plane) _PIPE(pipe * 2 + plane, _SPASIZE, _SPBSIZE)
3884#define SPKEYMINVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMINVAL, _SPBKEYMINVAL)
3885#define SPKEYMSK(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMSK, _SPBKEYMSK)
3886#define SPSURF(pipe, plane) _PIPE(pipe * 2 + plane, _SPASURF, _SPBSURF)
3887#define SPKEYMAXVAL(pipe, plane) _PIPE(pipe * 2 + plane, _SPAKEYMAXVAL, _SPBKEYMAXVAL)
3888#define SPTILEOFF(pipe, plane) _PIPE(pipe * 2 + plane, _SPATILEOFF, _SPBTILEOFF)
3889#define SPCONSTALPHA(pipe, plane) _PIPE(pipe * 2 + plane, _SPACONSTALPHA, _SPBCONSTALPHA)
3890#define SPGAMC(pipe, plane) _PIPE(pipe * 2 + plane, _SPAGAMC, _SPBGAMC)
3891
3892/* VBIOS regs */
3893#define VGACNTRL 0x71400
3894# define VGA_DISP_DISABLE (1 << 31)
3895# define VGA_2X_MODE (1 << 30)
3896# define VGA_PIPE_B_SELECT (1 << 29)
3897
3898#define VLV_VGACNTRL (VLV_DISPLAY_BASE + 0x71400)
3899
3900/* Ironlake */
3901
3902#define CPU_VGACNTRL 0x41000
3903
3904#define DIGITAL_PORT_HOTPLUG_CNTRL 0x44030
3905#define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4)
3906#define DIGITAL_PORTA_SHORT_PULSE_2MS (0 << 2)
3907#define DIGITAL_PORTA_SHORT_PULSE_4_5MS (1 << 2)
3908#define DIGITAL_PORTA_SHORT_PULSE_6MS (2 << 2)
3909#define DIGITAL_PORTA_SHORT_PULSE_100MS (3 << 2)
3910#define DIGITAL_PORTA_NO_DETECT (0 << 0)
3911#define DIGITAL_PORTA_LONG_PULSE_DETECT_MASK (1 << 1)
3912#define DIGITAL_PORTA_SHORT_PULSE_DETECT_MASK (1 << 0)
3913
3914/* refresh rate hardware control */
3915#define RR_HW_CTL 0x45300
3916#define RR_HW_LOW_POWER_FRAMES_MASK 0xff
3917#define RR_HW_HIGH_POWER_FRAMES_MASK 0xff00
3918
3919#define FDI_PLL_BIOS_0 0x46000
3920#define FDI_PLL_FB_CLOCK_MASK 0xff
3921#define FDI_PLL_BIOS_1 0x46004
3922#define FDI_PLL_BIOS_2 0x46008
3923#define DISPLAY_PORT_PLL_BIOS_0 0x4600c
3924#define DISPLAY_PORT_PLL_BIOS_1 0x46010
3925#define DISPLAY_PORT_PLL_BIOS_2 0x46014
3926
3927#define PCH_3DCGDIS0 0x46020
3928# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18)
3929# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1)
3930
3931#define PCH_3DCGDIS1 0x46024
3932# define VFMUNIT_CLOCK_GATE_DISABLE (1 << 11)
3933
3934#define FDI_PLL_FREQ_CTL 0x46030
3935#define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24)
3936#define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00
3937#define FDI_PLL_FREQ_DISABLE_COUNT_LIMIT_MASK 0xff
3938
3939
3940#define _PIPEA_DATA_M1 0x60030
3941#define PIPE_DATA_M1_OFFSET 0
3942#define _PIPEA_DATA_N1 0x60034
3943#define PIPE_DATA_N1_OFFSET 0
3944
3945#define _PIPEA_DATA_M2 0x60038
3946#define PIPE_DATA_M2_OFFSET 0
3947#define _PIPEA_DATA_N2 0x6003c
3948#define PIPE_DATA_N2_OFFSET 0
3949
3950#define _PIPEA_LINK_M1 0x60040
3951#define PIPE_LINK_M1_OFFSET 0
3952#define _PIPEA_LINK_N1 0x60044
3953#define PIPE_LINK_N1_OFFSET 0
3954
3955#define _PIPEA_LINK_M2 0x60048
3956#define PIPE_LINK_M2_OFFSET 0
3957#define _PIPEA_LINK_N2 0x6004c
3958#define PIPE_LINK_N2_OFFSET 0
3959
3960/* PIPEB timing regs are same start from 0x61000 */
3961
3962#define _PIPEB_DATA_M1 0x61030
3963#define _PIPEB_DATA_N1 0x61034
3964#define _PIPEB_DATA_M2 0x61038
3965#define _PIPEB_DATA_N2 0x6103c
3966#define _PIPEB_LINK_M1 0x61040
3967#define _PIPEB_LINK_N1 0x61044
3968#define _PIPEB_LINK_M2 0x61048
3969#define _PIPEB_LINK_N2 0x6104c
3970
3971#define PIPE_DATA_M1(tran) _TRANSCODER2(tran, _PIPEA_DATA_M1)
3972#define PIPE_DATA_N1(tran) _TRANSCODER2(tran, _PIPEA_DATA_N1)
3973#define PIPE_DATA_M2(tran) _TRANSCODER2(tran, _PIPEA_DATA_M2)
3974#define PIPE_DATA_N2(tran) _TRANSCODER2(tran, _PIPEA_DATA_N2)
3975#define PIPE_LINK_M1(tran) _TRANSCODER2(tran, _PIPEA_LINK_M1)
3976#define PIPE_LINK_N1(tran) _TRANSCODER2(tran, _PIPEA_LINK_N1)
3977#define PIPE_LINK_M2(tran) _TRANSCODER2(tran, _PIPEA_LINK_M2)
3978#define PIPE_LINK_N2(tran) _TRANSCODER2(tran, _PIPEA_LINK_N2)
3979
3980/* CPU panel fitter */
3981/* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */
3982#define _PFA_CTL_1 0x68080
3983#define _PFB_CTL_1 0x68880
3984#define PF_ENABLE (1<<31)
3985#define PF_PIPE_SEL_MASK_IVB (3<<29)
3986#define PF_PIPE_SEL_IVB(pipe) ((pipe)<<29)
3987#define PF_FILTER_MASK (3<<23)
3988#define PF_FILTER_PROGRAMMED (0<<23)
3989#define PF_FILTER_MED_3x3 (1<<23)
3990#define PF_FILTER_EDGE_ENHANCE (2<<23)
3991#define PF_FILTER_EDGE_SOFTEN (3<<23)
3992#define _PFA_WIN_SZ 0x68074
3993#define _PFB_WIN_SZ 0x68874
3994#define _PFA_WIN_POS 0x68070
3995#define _PFB_WIN_POS 0x68870
3996#define _PFA_VSCALE 0x68084
3997#define _PFB_VSCALE 0x68884
3998#define _PFA_HSCALE 0x68090
3999#define _PFB_HSCALE 0x68890
4000
4001#define PF_CTL(pipe) _PIPE(pipe, _PFA_CTL_1, _PFB_CTL_1)
4002#define PF_WIN_SZ(pipe) _PIPE(pipe, _PFA_WIN_SZ, _PFB_WIN_SZ)
4003#define PF_WIN_POS(pipe) _PIPE(pipe, _PFA_WIN_POS, _PFB_WIN_POS)
4004#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
4005#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
4006
4007/* legacy palette */
4008#define _LGC_PALETTE_A 0x4a000
4009#define _LGC_PALETTE_B 0x4a800
4010#define LGC_PALETTE(pipe) _PIPE(pipe, _LGC_PALETTE_A, _LGC_PALETTE_B)
4011
4012#define _GAMMA_MODE_A 0x4a480
4013#define _GAMMA_MODE_B 0x4ac80
4014#define GAMMA_MODE(pipe) _PIPE(pipe, _GAMMA_MODE_A, _GAMMA_MODE_B)
4015#define GAMMA_MODE_MODE_MASK (3 << 0)
4016#define GAMMA_MODE_MODE_8BIT (0 << 0)
4017#define GAMMA_MODE_MODE_10BIT (1 << 0)
4018#define GAMMA_MODE_MODE_12BIT (2 << 0)
4019#define GAMMA_MODE_MODE_SPLIT (3 << 0)
4020
4021/* interrupts */
4022#define DE_MASTER_IRQ_CONTROL (1 << 31)
4023#define DE_SPRITEB_FLIP_DONE (1 << 29)
4024#define DE_SPRITEA_FLIP_DONE (1 << 28)
4025#define DE_PLANEB_FLIP_DONE (1 << 27)
4026#define DE_PLANEA_FLIP_DONE (1 << 26)
4027#define DE_PLANE_FLIP_DONE(plane) (1 << (26 + (plane)))
4028#define DE_PCU_EVENT (1 << 25)
4029#define DE_GTT_FAULT (1 << 24)
4030#define DE_POISON (1 << 23)
4031#define DE_PERFORM_COUNTER (1 << 22)
4032#define DE_PCH_EVENT (1 << 21)
4033#define DE_AUX_CHANNEL_A (1 << 20)
4034#define DE_DP_A_HOTPLUG (1 << 19)
4035#define DE_GSE (1 << 18)
4036#define DE_PIPEB_VBLANK (1 << 15)
4037#define DE_PIPEB_EVEN_FIELD (1 << 14)
4038#define DE_PIPEB_ODD_FIELD (1 << 13)
4039#define DE_PIPEB_LINE_COMPARE (1 << 12)
4040#define DE_PIPEB_VSYNC (1 << 11)
4041#define DE_PIPEB_CRC_DONE (1 << 10)
4042#define DE_PIPEB_FIFO_UNDERRUN (1 << 8)
4043#define DE_PIPEA_VBLANK (1 << 7)
4044#define DE_PIPE_VBLANK(pipe) (1 << (7 + 8*(pipe)))
4045#define DE_PIPEA_EVEN_FIELD (1 << 6)
4046#define DE_PIPEA_ODD_FIELD (1 << 5)
4047#define DE_PIPEA_LINE_COMPARE (1 << 4)
4048#define DE_PIPEA_VSYNC (1 << 3)
4049#define DE_PIPEA_CRC_DONE (1 << 2)
4050#define DE_PIPE_CRC_DONE(pipe) (1 << (2 + 8*(pipe)))
4051#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
4052#define DE_PIPE_FIFO_UNDERRUN(pipe) (1 << (8*(pipe)))
4053
4054/* More Ivybridge lolz */
4055#define DE_ERR_INT_IVB (1<<30)
4056#define DE_GSE_IVB (1<<29)
4057#define DE_PCH_EVENT_IVB (1<<28)
4058#define DE_DP_A_HOTPLUG_IVB (1<<27)
4059#define DE_AUX_CHANNEL_A_IVB (1<<26)
4060#define DE_SPRITEC_FLIP_DONE_IVB (1<<14)
4061#define DE_PLANEC_FLIP_DONE_IVB (1<<13)
4062#define DE_PIPEC_VBLANK_IVB (1<<10)
4063#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
4064#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
4065#define DE_PIPEB_VBLANK_IVB (1<<5)
4066#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
4067#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
4068#define DE_PLANE_FLIP_DONE_IVB(plane) (1<< (3 + 5*(plane)))
4069#define DE_PIPEA_VBLANK_IVB (1<<0)
4070#define DE_PIPE_VBLANK_IVB(pipe) (1 << (pipe * 5))
4071
4072#define VLV_MASTER_IER 0x4400c /* Gunit master IER */
4073#define MASTER_INTERRUPT_ENABLE (1<<31)
4074
4075#define DEISR 0x44000
4076#define DEIMR 0x44004
4077#define DEIIR 0x44008
4078#define DEIER 0x4400c
4079
4080#define GTISR 0x44010
4081#define GTIMR 0x44014
4082#define GTIIR 0x44018
4083#define GTIER 0x4401c
4084
4085#define GEN8_MASTER_IRQ 0x44200
4086#define GEN8_MASTER_IRQ_CONTROL (1<<31)
4087#define GEN8_PCU_IRQ (1<<30)
4088#define GEN8_DE_PCH_IRQ (1<<23)
4089#define GEN8_DE_MISC_IRQ (1<<22)
4090#define GEN8_DE_PORT_IRQ (1<<20)
4091#define GEN8_DE_PIPE_C_IRQ (1<<18)
4092#define GEN8_DE_PIPE_B_IRQ (1<<17)
4093#define GEN8_DE_PIPE_A_IRQ (1<<16)
4094#define GEN8_DE_PIPE_IRQ(pipe) (1<<(16+pipe))
4095#define GEN8_GT_VECS_IRQ (1<<6)
4096#define GEN8_GT_VCS2_IRQ (1<<3)
4097#define GEN8_GT_VCS1_IRQ (1<<2)
4098#define GEN8_GT_BCS_IRQ (1<<1)
4099#define GEN8_GT_RCS_IRQ (1<<0)
4100
4101#define GEN8_GT_ISR(which) (0x44300 + (0x10 * (which)))
4102#define GEN8_GT_IMR(which) (0x44304 + (0x10 * (which)))
4103#define GEN8_GT_IIR(which) (0x44308 + (0x10 * (which)))
4104#define GEN8_GT_IER(which) (0x4430c + (0x10 * (which)))
4105
4106#define GEN8_BCS_IRQ_SHIFT 16
4107#define GEN8_RCS_IRQ_SHIFT 0
4108#define GEN8_VCS2_IRQ_SHIFT 16
4109#define GEN8_VCS1_IRQ_SHIFT 0
4110#define GEN8_VECS_IRQ_SHIFT 0
4111
4112#define GEN8_DE_PIPE_ISR(pipe) (0x44400 + (0x10 * (pipe)))
4113#define GEN8_DE_PIPE_IMR(pipe) (0x44404 + (0x10 * (pipe)))
4114#define GEN8_DE_PIPE_IIR(pipe) (0x44408 + (0x10 * (pipe)))
4115#define GEN8_DE_PIPE_IER(pipe) (0x4440c + (0x10 * (pipe)))
4116#define GEN8_PIPE_FIFO_UNDERRUN (1 << 31)
4117#define GEN8_PIPE_CDCLK_CRC_ERROR (1 << 29)
4118#define GEN8_PIPE_CDCLK_CRC_DONE (1 << 28)
4119#define GEN8_PIPE_CURSOR_FAULT (1 << 10)
4120#define GEN8_PIPE_SPRITE_FAULT (1 << 9)
4121#define GEN8_PIPE_PRIMARY_FAULT (1 << 8)
4122#define GEN8_PIPE_SPRITE_FLIP_DONE (1 << 5)
4123#define GEN8_PIPE_FLIP_DONE (1 << 4)
4124#define GEN8_PIPE_SCAN_LINE_EVENT (1 << 2)
4125#define GEN8_PIPE_VSYNC (1 << 1)
4126#define GEN8_PIPE_VBLANK (1 << 0)
4127#define GEN8_DE_PIPE_IRQ_FAULT_ERRORS \
4128 (GEN8_PIPE_CURSOR_FAULT | \
4129 GEN8_PIPE_SPRITE_FAULT | \
4130 GEN8_PIPE_PRIMARY_FAULT)
4131
4132#define GEN8_DE_PORT_ISR 0x44440
4133#define GEN8_DE_PORT_IMR 0x44444
4134#define GEN8_DE_PORT_IIR 0x44448
4135#define GEN8_DE_PORT_IER 0x4444c
4136#define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
4137#define GEN8_AUX_CHANNEL_A (1 << 0)
4138
4139#define GEN8_DE_MISC_ISR 0x44460
4140#define GEN8_DE_MISC_IMR 0x44464
4141#define GEN8_DE_MISC_IIR 0x44468
4142#define GEN8_DE_MISC_IER 0x4446c
4143#define GEN8_DE_MISC_GSE (1 << 27)
4144
4145#define GEN8_PCU_ISR 0x444e0
4146#define GEN8_PCU_IMR 0x444e4
4147#define GEN8_PCU_IIR 0x444e8
4148#define GEN8_PCU_IER 0x444ec
4149
4150#define ILK_DISPLAY_CHICKEN2 0x42004
4151/* Required on all Ironlake and Sandybridge according to the B-Spec. */
4152#define ILK_ELPIN_409_SELECT (1 << 25)
4153#define ILK_DPARB_GATE (1<<22)
4154#define ILK_VSDPFD_FULL (1<<21)
4155#define FUSE_STRAP 0x42014
4156#define ILK_INTERNAL_GRAPHICS_DISABLE (1 << 31)
4157#define ILK_INTERNAL_DISPLAY_DISABLE (1 << 30)
4158#define ILK_DISPLAY_DEBUG_DISABLE (1 << 29)
4159#define ILK_HDCP_DISABLE (1 << 25)
4160#define ILK_eDP_A_DISABLE (1 << 24)
4161#define HSW_CDCLK_LIMIT (1 << 24)
4162#define ILK_DESKTOP (1 << 23)
4163
4164#define ILK_DSPCLK_GATE_D 0x42020
4165#define ILK_VRHUNIT_CLOCK_GATE_DISABLE (1 << 28)
4166#define ILK_DPFCUNIT_CLOCK_GATE_DISABLE (1 << 9)
4167#define ILK_DPFCRUNIT_CLOCK_GATE_DISABLE (1 << 8)
4168#define ILK_DPFDUNIT_CLOCK_GATE_ENABLE (1 << 7)
4169#define ILK_DPARBUNIT_CLOCK_GATE_ENABLE (1 << 5)
4170
4171#define IVB_CHICKEN3 0x4200c
4172# define CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE (1 << 5)
4173# define CHICKEN3_DGMG_DONE_FIX_DISABLE (1 << 2)
4174
4175#define CHICKEN_PAR1_1 0x42080
4176#define DPA_MASK_VBLANK_SRD (1 << 15)
4177#define FORCE_ARB_IDLE_PLANES (1 << 14)
4178
4179#define _CHICKEN_PIPESL_1_A 0x420b0
4180#define _CHICKEN_PIPESL_1_B 0x420b4
4181#define HSW_FBCQ_DIS (1 << 22)
4182#define BDW_DPRS_MASK_VBLANK_SRD (1 << 0)
4183#define CHICKEN_PIPESL_1(pipe) _PIPE(pipe, _CHICKEN_PIPESL_1_A, _CHICKEN_PIPESL_1_B)
4184
4185#define DISP_ARB_CTL 0x45000
4186#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
4187#define DISP_FBC_WM_DIS (1<<15)
4188#define DISP_ARB_CTL2 0x45004
4189#define DISP_DATA_PARTITION_5_6 (1<<6)
4190#define GEN7_MSG_CTL 0x45010
4191#define WAIT_FOR_PCH_RESET_ACK (1<<1)
4192#define WAIT_FOR_PCH_FLR_ACK (1<<0)
4193#define HSW_NDE_RSTWRN_OPT 0x46408
4194#define RESET_PCH_HANDSHAKE_ENABLE (1<<4)
4195
4196/* GEN7 chicken */
4197#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
4198# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
4199#define COMMON_SLICE_CHICKEN2 0x7014
4200# define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0)
4201
4202#define GEN7_L3SQCREG1 0xB010
4203#define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000
4204
4205#define GEN7_L3CNTLREG1 0xB01C
4206#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C
4207#define GEN7_L3AGDIS (1<<19)
4208
4209#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
4210#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
4211
4212#define GEN7_L3SQCREG4 0xb034
4213#define L3SQ_URB_READ_CAM_MATCH_DISABLE (1<<27)
4214
4215/* GEN8 chicken */
4216#define HDC_CHICKEN0 0x7300
4217#define HDC_FORCE_NON_COHERENT (1<<4)
4218
4219/* WaCatErrorRejectionIssue */
4220#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
4221#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
4222
4223#define HSW_SCRATCH1 0xb038
4224#define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1<<27)
4225
4226/* PCH */
4227
4228/* south display engine interrupt: IBX */
4229#define SDE_AUDIO_POWER_D (1 << 27)
4230#define SDE_AUDIO_POWER_C (1 << 26)
4231#define SDE_AUDIO_POWER_B (1 << 25)
4232#define SDE_AUDIO_POWER_SHIFT (25)
4233#define SDE_AUDIO_POWER_MASK (7 << SDE_AUDIO_POWER_SHIFT)
4234#define SDE_GMBUS (1 << 24)
4235#define SDE_AUDIO_HDCP_TRANSB (1 << 23)
4236#define SDE_AUDIO_HDCP_TRANSA (1 << 22)
4237#define SDE_AUDIO_HDCP_MASK (3 << 22)
4238#define SDE_AUDIO_TRANSB (1 << 21)
4239#define SDE_AUDIO_TRANSA (1 << 20)
4240#define SDE_AUDIO_TRANS_MASK (3 << 20)
4241#define SDE_POISON (1 << 19)
4242/* 18 reserved */
4243#define SDE_FDI_RXB (1 << 17)
4244#define SDE_FDI_RXA (1 << 16)
4245#define SDE_FDI_MASK (3 << 16)
4246#define SDE_AUXD (1 << 15)
4247#define SDE_AUXC (1 << 14)
4248#define SDE_AUXB (1 << 13)
4249#define SDE_AUX_MASK (7 << 13)
4250/* 12 reserved */
4251#define SDE_CRT_HOTPLUG (1 << 11)
4252#define SDE_PORTD_HOTPLUG (1 << 10)
4253#define SDE_PORTC_HOTPLUG (1 << 9)
4254#define SDE_PORTB_HOTPLUG (1 << 8)
4255#define SDE_SDVOB_HOTPLUG (1 << 6)
4256#define SDE_HOTPLUG_MASK (SDE_CRT_HOTPLUG | \
4257 SDE_SDVOB_HOTPLUG | \
4258 SDE_PORTB_HOTPLUG | \
4259 SDE_PORTC_HOTPLUG | \
4260 SDE_PORTD_HOTPLUG)
4261#define SDE_TRANSB_CRC_DONE (1 << 5)
4262#define SDE_TRANSB_CRC_ERR (1 << 4)
4263#define SDE_TRANSB_FIFO_UNDER (1 << 3)
4264#define SDE_TRANSA_CRC_DONE (1 << 2)
4265#define SDE_TRANSA_CRC_ERR (1 << 1)
4266#define SDE_TRANSA_FIFO_UNDER (1 << 0)
4267#define SDE_TRANS_MASK (0x3f)
4268
4269/* south display engine interrupt: CPT/PPT */
4270#define SDE_AUDIO_POWER_D_CPT (1 << 31)
4271#define SDE_AUDIO_POWER_C_CPT (1 << 30)
4272#define SDE_AUDIO_POWER_B_CPT (1 << 29)
4273#define SDE_AUDIO_POWER_SHIFT_CPT 29
4274#define SDE_AUDIO_POWER_MASK_CPT (7 << 29)
4275#define SDE_AUXD_CPT (1 << 27)
4276#define SDE_AUXC_CPT (1 << 26)
4277#define SDE_AUXB_CPT (1 << 25)
4278#define SDE_AUX_MASK_CPT (7 << 25)
4279#define SDE_PORTD_HOTPLUG_CPT (1 << 23)
4280#define SDE_PORTC_HOTPLUG_CPT (1 << 22)
4281#define SDE_PORTB_HOTPLUG_CPT (1 << 21)
4282#define SDE_CRT_HOTPLUG_CPT (1 << 19)
4283#define SDE_SDVOB_HOTPLUG_CPT (1 << 18)
4284#define SDE_HOTPLUG_MASK_CPT (SDE_CRT_HOTPLUG_CPT | \
4285 SDE_SDVOB_HOTPLUG_CPT | \
4286 SDE_PORTD_HOTPLUG_CPT | \
4287 SDE_PORTC_HOTPLUG_CPT | \
4288 SDE_PORTB_HOTPLUG_CPT)
4289#define SDE_GMBUS_CPT (1 << 17)
4290#define SDE_ERROR_CPT (1 << 16)
4291#define SDE_AUDIO_CP_REQ_C_CPT (1 << 10)
4292#define SDE_AUDIO_CP_CHG_C_CPT (1 << 9)
4293#define SDE_FDI_RXC_CPT (1 << 8)
4294#define SDE_AUDIO_CP_REQ_B_CPT (1 << 6)
4295#define SDE_AUDIO_CP_CHG_B_CPT (1 << 5)
4296#define SDE_FDI_RXB_CPT (1 << 4)
4297#define SDE_AUDIO_CP_REQ_A_CPT (1 << 2)
4298#define SDE_AUDIO_CP_CHG_A_CPT (1 << 1)
4299#define SDE_FDI_RXA_CPT (1 << 0)
4300#define SDE_AUDIO_CP_REQ_CPT (SDE_AUDIO_CP_REQ_C_CPT | \
4301 SDE_AUDIO_CP_REQ_B_CPT | \
4302 SDE_AUDIO_CP_REQ_A_CPT)
4303#define SDE_AUDIO_CP_CHG_CPT (SDE_AUDIO_CP_CHG_C_CPT | \
4304 SDE_AUDIO_CP_CHG_B_CPT | \
4305 SDE_AUDIO_CP_CHG_A_CPT)
4306#define SDE_FDI_MASK_CPT (SDE_FDI_RXC_CPT | \
4307 SDE_FDI_RXB_CPT | \
4308 SDE_FDI_RXA_CPT)
4309
4310#define SDEISR 0xc4000
4311#define SDEIMR 0xc4004
4312#define SDEIIR 0xc4008
4313#define SDEIER 0xc400c
4314
4315#define SERR_INT 0xc4040
4316#define SERR_INT_POISON (1<<31)
4317#define SERR_INT_TRANS_C_FIFO_UNDERRUN (1<<6)
4318#define SERR_INT_TRANS_B_FIFO_UNDERRUN (1<<3)
4319#define SERR_INT_TRANS_A_FIFO_UNDERRUN (1<<0)
4320#define SERR_INT_TRANS_FIFO_UNDERRUN(pipe) (1<<(pipe*3))
4321
4322/* digital port hotplug */
4323#define PCH_PORT_HOTPLUG 0xc4030 /* SHOTPLUG_CTL */
4324#define PORTD_HOTPLUG_ENABLE (1 << 20)
4325#define PORTD_PULSE_DURATION_2ms (0)
4326#define PORTD_PULSE_DURATION_4_5ms (1 << 18)
4327#define PORTD_PULSE_DURATION_6ms (2 << 18)
4328#define PORTD_PULSE_DURATION_100ms (3 << 18)
4329#define PORTD_PULSE_DURATION_MASK (3 << 18)
4330#define PORTD_HOTPLUG_STATUS_MASK (0x3 << 16)
4331#define PORTD_HOTPLUG_NO_DETECT (0 << 16)
4332#define PORTD_HOTPLUG_SHORT_DETECT (1 << 16)
4333#define PORTD_HOTPLUG_LONG_DETECT (2 << 16)
4334#define PORTC_HOTPLUG_ENABLE (1 << 12)
4335#define PORTC_PULSE_DURATION_2ms (0)
4336#define PORTC_PULSE_DURATION_4_5ms (1 << 10)
4337#define PORTC_PULSE_DURATION_6ms (2 << 10)
4338#define PORTC_PULSE_DURATION_100ms (3 << 10)
4339#define PORTC_PULSE_DURATION_MASK (3 << 10)
4340#define PORTC_HOTPLUG_STATUS_MASK (0x3 << 8)
4341#define PORTC_HOTPLUG_NO_DETECT (0 << 8)
4342#define PORTC_HOTPLUG_SHORT_DETECT (1 << 8)
4343#define PORTC_HOTPLUG_LONG_DETECT (2 << 8)
4344#define PORTB_HOTPLUG_ENABLE (1 << 4)
4345#define PORTB_PULSE_DURATION_2ms (0)
4346#define PORTB_PULSE_DURATION_4_5ms (1 << 2)
4347#define PORTB_PULSE_DURATION_6ms (2 << 2)
4348#define PORTB_PULSE_DURATION_100ms (3 << 2)
4349#define PORTB_PULSE_DURATION_MASK (3 << 2)
4350#define PORTB_HOTPLUG_STATUS_MASK (0x3 << 0)
4351#define PORTB_HOTPLUG_NO_DETECT (0 << 0)
4352#define PORTB_HOTPLUG_SHORT_DETECT (1 << 0)
4353#define PORTB_HOTPLUG_LONG_DETECT (2 << 0)
4354
4355#define PCH_GPIOA 0xc5010
4356#define PCH_GPIOB 0xc5014
4357#define PCH_GPIOC 0xc5018
4358#define PCH_GPIOD 0xc501c
4359#define PCH_GPIOE 0xc5020
4360#define PCH_GPIOF 0xc5024
4361
4362#define PCH_GMBUS0 0xc5100
4363#define PCH_GMBUS1 0xc5104
4364#define PCH_GMBUS2 0xc5108
4365#define PCH_GMBUS3 0xc510c
4366#define PCH_GMBUS4 0xc5110
4367#define PCH_GMBUS5 0xc5120
4368
4369#define _PCH_DPLL_A 0xc6014
4370#define _PCH_DPLL_B 0xc6018
4371#define PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
4372
4373#define _PCH_FPA0 0xc6040
4374#define FP_CB_TUNE (0x3<<22)
4375#define _PCH_FPA1 0xc6044
4376#define _PCH_FPB0 0xc6048
4377#define _PCH_FPB1 0xc604c
4378#define PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
4379#define PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
4380
4381#define PCH_DPLL_TEST 0xc606c
4382
4383#define PCH_DREF_CONTROL 0xC6200
4384#define DREF_CONTROL_MASK 0x7fc3
4385#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0<<13)
4386#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2<<13)
4387#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3<<13)
4388#define DREF_CPU_SOURCE_OUTPUT_MASK (3<<13)
4389#define DREF_SSC_SOURCE_DISABLE (0<<11)
4390#define DREF_SSC_SOURCE_ENABLE (2<<11)
4391#define DREF_SSC_SOURCE_MASK (3<<11)
4392#define DREF_NONSPREAD_SOURCE_DISABLE (0<<9)
4393#define DREF_NONSPREAD_CK505_ENABLE (1<<9)
4394#define DREF_NONSPREAD_SOURCE_ENABLE (2<<9)
4395#define DREF_NONSPREAD_SOURCE_MASK (3<<9)
4396#define DREF_SUPERSPREAD_SOURCE_DISABLE (0<<7)
4397#define DREF_SUPERSPREAD_SOURCE_ENABLE (2<<7)
4398#define DREF_SUPERSPREAD_SOURCE_MASK (3<<7)
4399#define DREF_SSC4_DOWNSPREAD (0<<6)
4400#define DREF_SSC4_CENTERSPREAD (1<<6)
4401#define DREF_SSC1_DISABLE (0<<1)
4402#define DREF_SSC1_ENABLE (1<<1)
4403#define DREF_SSC4_DISABLE (0)
4404#define DREF_SSC4_ENABLE (1)
4405
4406#define PCH_RAWCLK_FREQ 0xc6204
4407#define FDL_TP1_TIMER_SHIFT 12
4408#define FDL_TP1_TIMER_MASK (3<<12)
4409#define FDL_TP2_TIMER_SHIFT 10
4410#define FDL_TP2_TIMER_MASK (3<<10)
4411#define RAWCLK_FREQ_MASK 0x3ff
4412
4413#define PCH_DPLL_TMR_CFG 0xc6208
4414
4415#define PCH_SSC4_PARMS 0xc6210
4416#define PCH_SSC4_AUX_PARMS 0xc6214
4417
4418#define PCH_DPLL_SEL 0xc7000
4419#define TRANS_DPLLB_SEL(pipe) (1 << (pipe * 4))
4420#define TRANS_DPLLA_SEL(pipe) 0
4421#define TRANS_DPLL_ENABLE(pipe) (1 << (pipe * 4 + 3))
4422
4423/* transcoder */
4424
4425#define _PCH_TRANS_HTOTAL_A 0xe0000
4426#define TRANS_HTOTAL_SHIFT 16
4427#define TRANS_HACTIVE_SHIFT 0
4428#define _PCH_TRANS_HBLANK_A 0xe0004
4429#define TRANS_HBLANK_END_SHIFT 16
4430#define TRANS_HBLANK_START_SHIFT 0
4431#define _PCH_TRANS_HSYNC_A 0xe0008
4432#define TRANS_HSYNC_END_SHIFT 16
4433#define TRANS_HSYNC_START_SHIFT 0
4434#define _PCH_TRANS_VTOTAL_A 0xe000c
4435#define TRANS_VTOTAL_SHIFT 16
4436#define TRANS_VACTIVE_SHIFT 0
4437#define _PCH_TRANS_VBLANK_A 0xe0010
4438#define TRANS_VBLANK_END_SHIFT 16
4439#define TRANS_VBLANK_START_SHIFT 0
4440#define _PCH_TRANS_VSYNC_A 0xe0014
4441#define TRANS_VSYNC_END_SHIFT 16
4442#define TRANS_VSYNC_START_SHIFT 0
4443#define _PCH_TRANS_VSYNCSHIFT_A 0xe0028
4444
4445#define _PCH_TRANSA_DATA_M1 0xe0030
4446#define _PCH_TRANSA_DATA_N1 0xe0034
4447#define _PCH_TRANSA_DATA_M2 0xe0038
4448#define _PCH_TRANSA_DATA_N2 0xe003c
4449#define _PCH_TRANSA_LINK_M1 0xe0040
4450#define _PCH_TRANSA_LINK_N1 0xe0044
4451#define _PCH_TRANSA_LINK_M2 0xe0048
4452#define _PCH_TRANSA_LINK_N2 0xe004c
4453
4454/* Per-transcoder DIP controls */
4455
4456#define _VIDEO_DIP_CTL_A 0xe0200
4457#define _VIDEO_DIP_DATA_A 0xe0208
4458#define _VIDEO_DIP_GCP_A 0xe0210
4459
4460#define _VIDEO_DIP_CTL_B 0xe1200
4461#define _VIDEO_DIP_DATA_B 0xe1208
4462#define _VIDEO_DIP_GCP_B 0xe1210
4463
4464#define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
4465#define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
4466#define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
4467
4468#define VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200)
4469#define VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208)
4470#define VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210)
4471
4472#define VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170)
4473#define VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174)
4474#define VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178)
4475
4476#define VLV_TVIDEO_DIP_CTL(pipe) \
4477 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
4478#define VLV_TVIDEO_DIP_DATA(pipe) \
4479 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
4480#define VLV_TVIDEO_DIP_GCP(pipe) \
4481 _PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
4482
4483/* Haswell DIP controls */
4484#define HSW_VIDEO_DIP_CTL_A 0x60200
4485#define HSW_VIDEO_DIP_AVI_DATA_A 0x60220
4486#define HSW_VIDEO_DIP_VS_DATA_A 0x60260
4487#define HSW_VIDEO_DIP_SPD_DATA_A 0x602A0
4488#define HSW_VIDEO_DIP_GMP_DATA_A 0x602E0
4489#define HSW_VIDEO_DIP_VSC_DATA_A 0x60320
4490#define HSW_VIDEO_DIP_AVI_ECC_A 0x60240
4491#define HSW_VIDEO_DIP_VS_ECC_A 0x60280
4492#define HSW_VIDEO_DIP_SPD_ECC_A 0x602C0
4493#define HSW_VIDEO_DIP_GMP_ECC_A 0x60300
4494#define HSW_VIDEO_DIP_VSC_ECC_A 0x60344
4495#define HSW_VIDEO_DIP_GCP_A 0x60210
4496
4497#define HSW_VIDEO_DIP_CTL_B 0x61200
4498#define HSW_VIDEO_DIP_AVI_DATA_B 0x61220
4499#define HSW_VIDEO_DIP_VS_DATA_B 0x61260
4500#define HSW_VIDEO_DIP_SPD_DATA_B 0x612A0
4501#define HSW_VIDEO_DIP_GMP_DATA_B 0x612E0
4502#define HSW_VIDEO_DIP_VSC_DATA_B 0x61320
4503#define HSW_VIDEO_DIP_BVI_ECC_B 0x61240
4504#define HSW_VIDEO_DIP_VS_ECC_B 0x61280
4505#define HSW_VIDEO_DIP_SPD_ECC_B 0x612C0
4506#define HSW_VIDEO_DIP_GMP_ECC_B 0x61300
4507#define HSW_VIDEO_DIP_VSC_ECC_B 0x61344
4508#define HSW_VIDEO_DIP_GCP_B 0x61210
4509
4510#define HSW_TVIDEO_DIP_CTL(trans) \
4511 _TRANSCODER2(trans, HSW_VIDEO_DIP_CTL_A)
4512#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
4513 _TRANSCODER2(trans, HSW_VIDEO_DIP_AVI_DATA_A)
4514#define HSW_TVIDEO_DIP_VS_DATA(trans) \
4515 _TRANSCODER2(trans, HSW_VIDEO_DIP_VS_DATA_A)
4516#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
4517 _TRANSCODER2(trans, HSW_VIDEO_DIP_SPD_DATA_A)
4518#define HSW_TVIDEO_DIP_GCP(trans) \
4519 _TRANSCODER2(trans, HSW_VIDEO_DIP_GCP_A)
4520#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
4521 _TRANSCODER2(trans, HSW_VIDEO_DIP_VSC_DATA_A)
4522
4523#define HSW_STEREO_3D_CTL_A 0x70020
4524#define S3D_ENABLE (1<<31)
4525#define HSW_STEREO_3D_CTL_B 0x71020
4526
4527#define HSW_STEREO_3D_CTL(trans) \
4528 _PIPE2(trans, HSW_STEREO_3D_CTL_A)
4529
4530#define _PCH_TRANS_HTOTAL_B 0xe1000
4531#define _PCH_TRANS_HBLANK_B 0xe1004
4532#define _PCH_TRANS_HSYNC_B 0xe1008
4533#define _PCH_TRANS_VTOTAL_B 0xe100c
4534#define _PCH_TRANS_VBLANK_B 0xe1010
4535#define _PCH_TRANS_VSYNC_B 0xe1014
4536#define _PCH_TRANS_VSYNCSHIFT_B 0xe1028
4537
4538#define PCH_TRANS_HTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_HTOTAL_A, _PCH_TRANS_HTOTAL_B)
4539#define PCH_TRANS_HBLANK(pipe) _PIPE(pipe, _PCH_TRANS_HBLANK_A, _PCH_TRANS_HBLANK_B)
4540#define PCH_TRANS_HSYNC(pipe) _PIPE(pipe, _PCH_TRANS_HSYNC_A, _PCH_TRANS_HSYNC_B)
4541#define PCH_TRANS_VTOTAL(pipe) _PIPE(pipe, _PCH_TRANS_VTOTAL_A, _PCH_TRANS_VTOTAL_B)
4542#define PCH_TRANS_VBLANK(pipe) _PIPE(pipe, _PCH_TRANS_VBLANK_A, _PCH_TRANS_VBLANK_B)
4543#define PCH_TRANS_VSYNC(pipe) _PIPE(pipe, _PCH_TRANS_VSYNC_A, _PCH_TRANS_VSYNC_B)
4544#define PCH_TRANS_VSYNCSHIFT(pipe) _PIPE(pipe, _PCH_TRANS_VSYNCSHIFT_A, \
4545 _PCH_TRANS_VSYNCSHIFT_B)
4546
4547#define _PCH_TRANSB_DATA_M1 0xe1030
4548#define _PCH_TRANSB_DATA_N1 0xe1034
4549#define _PCH_TRANSB_DATA_M2 0xe1038
4550#define _PCH_TRANSB_DATA_N2 0xe103c
4551#define _PCH_TRANSB_LINK_M1 0xe1040
4552#define _PCH_TRANSB_LINK_N1 0xe1044
4553#define _PCH_TRANSB_LINK_M2 0xe1048
4554#define _PCH_TRANSB_LINK_N2 0xe104c
4555
4556#define PCH_TRANS_DATA_M1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M1, _PCH_TRANSB_DATA_M1)
4557#define PCH_TRANS_DATA_N1(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N1, _PCH_TRANSB_DATA_N1)
4558#define PCH_TRANS_DATA_M2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_M2, _PCH_TRANSB_DATA_M2)
4559#define PCH_TRANS_DATA_N2(pipe) _PIPE(pipe, _PCH_TRANSA_DATA_N2, _PCH_TRANSB_DATA_N2)
4560#define PCH_TRANS_LINK_M1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M1, _PCH_TRANSB_LINK_M1)
4561#define PCH_TRANS_LINK_N1(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N1, _PCH_TRANSB_LINK_N1)
4562#define PCH_TRANS_LINK_M2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_M2, _PCH_TRANSB_LINK_M2)
4563#define PCH_TRANS_LINK_N2(pipe) _PIPE(pipe, _PCH_TRANSA_LINK_N2, _PCH_TRANSB_LINK_N2)
4564
4565#define _PCH_TRANSACONF 0xf0008
4566#define _PCH_TRANSBCONF 0xf1008
4567#define PCH_TRANSCONF(pipe) _PIPE(pipe, _PCH_TRANSACONF, _PCH_TRANSBCONF)
4568#define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
4569#define TRANS_DISABLE (0<<31)
4570#define TRANS_ENABLE (1<<31)
4571#define TRANS_STATE_MASK (1<<30)
4572#define TRANS_STATE_DISABLE (0<<30)
4573#define TRANS_STATE_ENABLE (1<<30)
4574#define TRANS_FSYNC_DELAY_HB1 (0<<27)
4575#define TRANS_FSYNC_DELAY_HB2 (1<<27)
4576#define TRANS_FSYNC_DELAY_HB3 (2<<27)
4577#define TRANS_FSYNC_DELAY_HB4 (3<<27)
4578#define TRANS_INTERLACE_MASK (7<<21)
4579#define TRANS_PROGRESSIVE (0<<21)
4580#define TRANS_INTERLACED (3<<21)
4581#define TRANS_LEGACY_INTERLACED_ILK (2<<21)
4582#define TRANS_8BPC (0<<5)
4583#define TRANS_10BPC (1<<5)
4584#define TRANS_6BPC (2<<5)
4585#define TRANS_12BPC (3<<5)
4586
4587#define _TRANSA_CHICKEN1 0xf0060
4588#define _TRANSB_CHICKEN1 0xf1060
4589#define TRANS_CHICKEN1(pipe) _PIPE(pipe, _TRANSA_CHICKEN1, _TRANSB_CHICKEN1)
4590#define TRANS_CHICKEN1_DP0UNIT_GC_DISABLE (1<<4)
4591#define _TRANSA_CHICKEN2 0xf0064
4592#define _TRANSB_CHICKEN2 0xf1064
4593#define TRANS_CHICKEN2(pipe) _PIPE(pipe, _TRANSA_CHICKEN2, _TRANSB_CHICKEN2)
4594#define TRANS_CHICKEN2_TIMING_OVERRIDE (1<<31)
4595#define TRANS_CHICKEN2_FDI_POLARITY_REVERSED (1<<29)
4596#define TRANS_CHICKEN2_FRAME_START_DELAY_MASK (3<<27)
4597#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER (1<<26)
4598#define TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH (1<<25)
4599
4600#define SOUTH_CHICKEN1 0xc2000
4601#define FDIA_PHASE_SYNC_SHIFT_OVR 19
4602#define FDIA_PHASE_SYNC_SHIFT_EN 18
4603#define FDI_PHASE_SYNC_OVR(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_OVR - ((pipe) * 2)))
4604#define FDI_PHASE_SYNC_EN(pipe) (1<<(FDIA_PHASE_SYNC_SHIFT_EN - ((pipe) * 2)))
4605#define FDI_BC_BIFURCATION_SELECT (1 << 12)
4606#define SOUTH_CHICKEN2 0xc2004
4607#define FDI_MPHY_IOSFSB_RESET_STATUS (1<<13)
4608#define FDI_MPHY_IOSFSB_RESET_CTL (1<<12)
4609#define DPLS_EDP_PPS_FIX_DIS (1<<0)
4610
4611#define _FDI_RXA_CHICKEN 0xc200c
4612#define _FDI_RXB_CHICKEN 0xc2010
4613#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
4614#define FDI_RX_PHASE_SYNC_POINTER_EN (1<<0)
4615#define FDI_RX_CHICKEN(pipe) _PIPE(pipe, _FDI_RXA_CHICKEN, _FDI_RXB_CHICKEN)
4616
4617#define SOUTH_DSPCLK_GATE_D 0xc2020
4618#define PCH_DPLUNIT_CLOCK_GATE_DISABLE (1<<30)
4619#define PCH_DPLSUNIT_CLOCK_GATE_DISABLE (1<<29)
4620#define PCH_CPUNIT_CLOCK_GATE_DISABLE (1<<14)
4621#define PCH_LP_PARTITION_LEVEL_DISABLE (1<<12)
4622
4623/* CPU: FDI_TX */
4624#define _FDI_TXA_CTL 0x60100
4625#define _FDI_TXB_CTL 0x61100
4626#define FDI_TX_CTL(pipe) _PIPE(pipe, _FDI_TXA_CTL, _FDI_TXB_CTL)
4627#define FDI_TX_DISABLE (0<<31)
4628#define FDI_TX_ENABLE (1<<31)
4629#define FDI_LINK_TRAIN_PATTERN_1 (0<<28)
4630#define FDI_LINK_TRAIN_PATTERN_2 (1<<28)
4631#define FDI_LINK_TRAIN_PATTERN_IDLE (2<<28)
4632#define FDI_LINK_TRAIN_NONE (3<<28)
4633#define FDI_LINK_TRAIN_VOLTAGE_0_4V (0<<25)
4634#define FDI_LINK_TRAIN_VOLTAGE_0_6V (1<<25)
4635#define FDI_LINK_TRAIN_VOLTAGE_0_8V (2<<25)
4636#define FDI_LINK_TRAIN_VOLTAGE_1_2V (3<<25)
4637#define FDI_LINK_TRAIN_PRE_EMPHASIS_NONE (0<<22)
4638#define FDI_LINK_TRAIN_PRE_EMPHASIS_1_5X (1<<22)
4639#define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2<<22)
4640#define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3<<22)
4641/* ILK always use 400mV 0dB for voltage swing and pre-emphasis level.
4642 SNB has different settings. */
4643/* SNB A-stepping */
4644#define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4645#define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4646#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4647#define FDI_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4648/* SNB B-stepping */
4649#define FDI_LINK_TRAIN_400MV_0DB_SNB_B (0x0<<22)
4650#define FDI_LINK_TRAIN_400MV_6DB_SNB_B (0x3a<<22)
4651#define FDI_LINK_TRAIN_600MV_3_5DB_SNB_B (0x39<<22)
4652#define FDI_LINK_TRAIN_800MV_0DB_SNB_B (0x38<<22)
4653#define FDI_LINK_TRAIN_VOL_EMP_MASK (0x3f<<22)
4654#define FDI_DP_PORT_WIDTH_SHIFT 19
4655#define FDI_DP_PORT_WIDTH_MASK (7 << FDI_DP_PORT_WIDTH_SHIFT)
4656#define FDI_DP_PORT_WIDTH(width) (((width) - 1) << FDI_DP_PORT_WIDTH_SHIFT)
4657#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
4658/* Ironlake: hardwired to 1 */
4659#define FDI_TX_PLL_ENABLE (1<<14)
4660
4661/* Ivybridge has different bits for lolz */
4662#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
4663#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
4664#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
4665#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
4666
4667/* both Tx and Rx */
4668#define FDI_COMPOSITE_SYNC (1<<11)
4669#define FDI_LINK_TRAIN_AUTO (1<<10)
4670#define FDI_SCRAMBLING_ENABLE (0<<7)
4671#define FDI_SCRAMBLING_DISABLE (1<<7)
4672
4673/* FDI_RX, FDI_X is hard-wired to Transcoder_X */
4674#define _FDI_RXA_CTL 0xf000c
4675#define _FDI_RXB_CTL 0xf100c
4676#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
4677#define FDI_RX_ENABLE (1<<31)
4678/* train, dp width same as FDI_TX */
4679#define FDI_FS_ERRC_ENABLE (1<<27)
4680#define FDI_FE_ERRC_ENABLE (1<<26)
4681#define FDI_RX_POLARITY_REVERSED_LPT (1<<16)
4682#define FDI_8BPC (0<<16)
4683#define FDI_10BPC (1<<16)
4684#define FDI_6BPC (2<<16)
4685#define FDI_12BPC (3<<16)
4686#define FDI_RX_LINK_REVERSAL_OVERRIDE (1<<15)
4687#define FDI_DMI_LINK_REVERSE_MASK (1<<14)
4688#define FDI_RX_PLL_ENABLE (1<<13)
4689#define FDI_FS_ERR_CORRECT_ENABLE (1<<11)
4690#define FDI_FE_ERR_CORRECT_ENABLE (1<<10)
4691#define FDI_FS_ERR_REPORT_ENABLE (1<<9)
4692#define FDI_FE_ERR_REPORT_ENABLE (1<<8)
4693#define FDI_RX_ENHANCE_FRAME_ENABLE (1<<6)
4694#define FDI_PCDCLK (1<<4)
4695/* CPT */
4696#define FDI_AUTO_TRAINING (1<<10)
4697#define FDI_LINK_TRAIN_PATTERN_1_CPT (0<<8)
4698#define FDI_LINK_TRAIN_PATTERN_2_CPT (1<<8)
4699#define FDI_LINK_TRAIN_PATTERN_IDLE_CPT (2<<8)
4700#define FDI_LINK_TRAIN_NORMAL_CPT (3<<8)
4701#define FDI_LINK_TRAIN_PATTERN_MASK_CPT (3<<8)
4702
4703#define _FDI_RXA_MISC 0xf0010
4704#define _FDI_RXB_MISC 0xf1010
4705#define FDI_RX_PWRDN_LANE1_MASK (3<<26)
4706#define FDI_RX_PWRDN_LANE1_VAL(x) ((x)<<26)
4707#define FDI_RX_PWRDN_LANE0_MASK (3<<24)
4708#define FDI_RX_PWRDN_LANE0_VAL(x) ((x)<<24)
4709#define FDI_RX_TP1_TO_TP2_48 (2<<20)
4710#define FDI_RX_TP1_TO_TP2_64 (3<<20)
4711#define FDI_RX_FDI_DELAY_90 (0x90<<0)
4712#define FDI_RX_MISC(pipe) _PIPE(pipe, _FDI_RXA_MISC, _FDI_RXB_MISC)
4713
4714#define _FDI_RXA_TUSIZE1 0xf0030
4715#define _FDI_RXA_TUSIZE2 0xf0038
4716#define _FDI_RXB_TUSIZE1 0xf1030
4717#define _FDI_RXB_TUSIZE2 0xf1038
4718#define FDI_RX_TUSIZE1(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE1, _FDI_RXB_TUSIZE1)
4719#define FDI_RX_TUSIZE2(pipe) _PIPE(pipe, _FDI_RXA_TUSIZE2, _FDI_RXB_TUSIZE2)
4720
4721/* FDI_RX interrupt register format */
4722#define FDI_RX_INTER_LANE_ALIGN (1<<10)
4723#define FDI_RX_SYMBOL_LOCK (1<<9) /* train 2 */
4724#define FDI_RX_BIT_LOCK (1<<8) /* train 1 */
4725#define FDI_RX_TRAIN_PATTERN_2_FAIL (1<<7)
4726#define FDI_RX_FS_CODE_ERR (1<<6)
4727#define FDI_RX_FE_CODE_ERR (1<<5)
4728#define FDI_RX_SYMBOL_ERR_RATE_ABOVE (1<<4)
4729#define FDI_RX_HDCP_LINK_FAIL (1<<3)
4730#define FDI_RX_PIXEL_FIFO_OVERFLOW (1<<2)
4731#define FDI_RX_CROSS_CLOCK_OVERFLOW (1<<1)
4732#define FDI_RX_SYMBOL_QUEUE_OVERFLOW (1<<0)
4733
4734#define _FDI_RXA_IIR 0xf0014
4735#define _FDI_RXA_IMR 0xf0018
4736#define _FDI_RXB_IIR 0xf1014
4737#define _FDI_RXB_IMR 0xf1018
4738#define FDI_RX_IIR(pipe) _PIPE(pipe, _FDI_RXA_IIR, _FDI_RXB_IIR)
4739#define FDI_RX_IMR(pipe) _PIPE(pipe, _FDI_RXA_IMR, _FDI_RXB_IMR)
4740
4741#define FDI_PLL_CTL_1 0xfe000
4742#define FDI_PLL_CTL_2 0xfe004
4743
4744#define PCH_LVDS 0xe1180
4745#define LVDS_DETECTED (1 << 1)
4746
4747/* vlv has 2 sets of panel control regs. */
4748#define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200)
4749#define PIPEA_PP_CONTROL (VLV_DISPLAY_BASE + 0x61204)
4750#define PIPEA_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61208)
4751#define PANEL_PORT_SELECT_DPB_VLV (1 << 30)
4752#define PANEL_PORT_SELECT_DPC_VLV (2 << 30)
4753#define PIPEA_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6120c)
4754#define PIPEA_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61210)
4755
4756#define PIPEB_PP_STATUS (VLV_DISPLAY_BASE + 0x61300)
4757#define PIPEB_PP_CONTROL (VLV_DISPLAY_BASE + 0x61304)
4758#define PIPEB_PP_ON_DELAYS (VLV_DISPLAY_BASE + 0x61308)
4759#define PIPEB_PP_OFF_DELAYS (VLV_DISPLAY_BASE + 0x6130c)
4760#define PIPEB_PP_DIVISOR (VLV_DISPLAY_BASE + 0x61310)
4761
4762#define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)
4763#define VLV_PIPE_PP_CONTROL(pipe) _PIPE(pipe, PIPEA_PP_CONTROL, PIPEB_PP_CONTROL)
4764#define VLV_PIPE_PP_ON_DELAYS(pipe) \
4765 _PIPE(pipe, PIPEA_PP_ON_DELAYS, PIPEB_PP_ON_DELAYS)
4766#define VLV_PIPE_PP_OFF_DELAYS(pipe) \
4767 _PIPE(pipe, PIPEA_PP_OFF_DELAYS, PIPEB_PP_OFF_DELAYS)
4768#define VLV_PIPE_PP_DIVISOR(pipe) \
4769 _PIPE(pipe, PIPEA_PP_DIVISOR, PIPEB_PP_DIVISOR)
4770
4771#define PCH_PP_STATUS 0xc7200
4772#define PCH_PP_CONTROL 0xc7204
4773#define PANEL_UNLOCK_REGS (0xabcd << 16)
4774#define PANEL_UNLOCK_MASK (0xffff << 16)
4775#define EDP_FORCE_VDD (1 << 3)
4776#define EDP_BLC_ENABLE (1 << 2)
4777#define PANEL_POWER_RESET (1 << 1)
4778#define PANEL_POWER_OFF (0 << 0)
4779#define PANEL_POWER_ON (1 << 0)
4780#define PCH_PP_ON_DELAYS 0xc7208
4781#define PANEL_PORT_SELECT_MASK (3 << 30)
4782#define PANEL_PORT_SELECT_LVDS (0 << 30)
4783#define PANEL_PORT_SELECT_DPA (1 << 30)
4784#define PANEL_PORT_SELECT_DPC (2 << 30)
4785#define PANEL_PORT_SELECT_DPD (3 << 30)
4786#define PANEL_POWER_UP_DELAY_MASK (0x1fff0000)
4787#define PANEL_POWER_UP_DELAY_SHIFT 16
4788#define PANEL_LIGHT_ON_DELAY_MASK (0x1fff)
4789#define PANEL_LIGHT_ON_DELAY_SHIFT 0
4790
4791#define PCH_PP_OFF_DELAYS 0xc720c
4792#define PANEL_POWER_DOWN_DELAY_MASK (0x1fff0000)
4793#define PANEL_POWER_DOWN_DELAY_SHIFT 16
4794#define PANEL_LIGHT_OFF_DELAY_MASK (0x1fff)
4795#define PANEL_LIGHT_OFF_DELAY_SHIFT 0
4796
4797#define PCH_PP_DIVISOR 0xc7210
4798#define PP_REFERENCE_DIVIDER_MASK (0xffffff00)
4799#define PP_REFERENCE_DIVIDER_SHIFT 8
4800#define PANEL_POWER_CYCLE_DELAY_MASK (0x1f)
4801#define PANEL_POWER_CYCLE_DELAY_SHIFT 0
4802
4803#define PCH_DP_B 0xe4100
4804#define PCH_DPB_AUX_CH_CTL 0xe4110
4805#define PCH_DPB_AUX_CH_DATA1 0xe4114
4806#define PCH_DPB_AUX_CH_DATA2 0xe4118
4807#define PCH_DPB_AUX_CH_DATA3 0xe411c
4808#define PCH_DPB_AUX_CH_DATA4 0xe4120
4809#define PCH_DPB_AUX_CH_DATA5 0xe4124
4810
4811#define PCH_DP_C 0xe4200
4812#define PCH_DPC_AUX_CH_CTL 0xe4210
4813#define PCH_DPC_AUX_CH_DATA1 0xe4214
4814#define PCH_DPC_AUX_CH_DATA2 0xe4218
4815#define PCH_DPC_AUX_CH_DATA3 0xe421c
4816#define PCH_DPC_AUX_CH_DATA4 0xe4220
4817#define PCH_DPC_AUX_CH_DATA5 0xe4224
4818
4819#define PCH_DP_D 0xe4300
4820#define PCH_DPD_AUX_CH_CTL 0xe4310
4821#define PCH_DPD_AUX_CH_DATA1 0xe4314
4822#define PCH_DPD_AUX_CH_DATA2 0xe4318
4823#define PCH_DPD_AUX_CH_DATA3 0xe431c
4824#define PCH_DPD_AUX_CH_DATA4 0xe4320
4825#define PCH_DPD_AUX_CH_DATA5 0xe4324
4826
4827/* CPT */
4828#define PORT_TRANS_A_SEL_CPT 0
4829#define PORT_TRANS_B_SEL_CPT (1<<29)
4830#define PORT_TRANS_C_SEL_CPT (2<<29)
4831#define PORT_TRANS_SEL_MASK (3<<29)
4832#define PORT_TRANS_SEL_CPT(pipe) ((pipe) << 29)
4833#define PORT_TO_PIPE(val) (((val) & (1<<30)) >> 30)
4834#define PORT_TO_PIPE_CPT(val) (((val) & PORT_TRANS_SEL_MASK) >> 29)
4835
4836#define TRANS_DP_CTL_A 0xe0300
4837#define TRANS_DP_CTL_B 0xe1300
4838#define TRANS_DP_CTL_C 0xe2300
4839#define TRANS_DP_CTL(pipe) _PIPE(pipe, TRANS_DP_CTL_A, TRANS_DP_CTL_B)
4840#define TRANS_DP_OUTPUT_ENABLE (1<<31)
4841#define TRANS_DP_PORT_SEL_B (0<<29)
4842#define TRANS_DP_PORT_SEL_C (1<<29)
4843#define TRANS_DP_PORT_SEL_D (2<<29)
4844#define TRANS_DP_PORT_SEL_NONE (3<<29)
4845#define TRANS_DP_PORT_SEL_MASK (3<<29)
4846#define TRANS_DP_AUDIO_ONLY (1<<26)
4847#define TRANS_DP_ENH_FRAMING (1<<18)
4848#define TRANS_DP_8BPC (0<<9)
4849#define TRANS_DP_10BPC (1<<9)
4850#define TRANS_DP_6BPC (2<<9)
4851#define TRANS_DP_12BPC (3<<9)
4852#define TRANS_DP_BPC_MASK (3<<9)
4853#define TRANS_DP_VSYNC_ACTIVE_HIGH (1<<4)
4854#define TRANS_DP_VSYNC_ACTIVE_LOW 0
4855#define TRANS_DP_HSYNC_ACTIVE_HIGH (1<<3)
4856#define TRANS_DP_HSYNC_ACTIVE_LOW 0
4857#define TRANS_DP_SYNC_MASK (3<<3)
4858
4859/* SNB eDP training params */
4860/* SNB A-stepping */
4861#define EDP_LINK_TRAIN_400MV_0DB_SNB_A (0x38<<22)
4862#define EDP_LINK_TRAIN_400MV_6DB_SNB_A (0x02<<22)
4863#define EDP_LINK_TRAIN_600MV_3_5DB_SNB_A (0x01<<22)
4864#define EDP_LINK_TRAIN_800MV_0DB_SNB_A (0x0<<22)
4865/* SNB B-stepping */
4866#define EDP_LINK_TRAIN_400_600MV_0DB_SNB_B (0x0<<22)
4867#define EDP_LINK_TRAIN_400MV_3_5DB_SNB_B (0x1<<22)
4868#define EDP_LINK_TRAIN_400_600MV_6DB_SNB_B (0x3a<<22)
4869#define EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B (0x39<<22)
4870#define EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B (0x38<<22)
4871#define EDP_LINK_TRAIN_VOL_EMP_MASK_SNB (0x3f<<22)
4872
4873/* IVB */
4874#define EDP_LINK_TRAIN_400MV_0DB_IVB (0x24 <<22)
4875#define EDP_LINK_TRAIN_400MV_3_5DB_IVB (0x2a <<22)
4876#define EDP_LINK_TRAIN_400MV_6DB_IVB (0x2f <<22)
4877#define EDP_LINK_TRAIN_600MV_0DB_IVB (0x30 <<22)
4878#define EDP_LINK_TRAIN_600MV_3_5DB_IVB (0x36 <<22)
4879#define EDP_LINK_TRAIN_800MV_0DB_IVB (0x38 <<22)
4880#define EDP_LINK_TRAIN_800MV_3_5DB_IVB (0x3e <<22)
4881
4882/* legacy values */
4883#define EDP_LINK_TRAIN_500MV_0DB_IVB (0x00 <<22)
4884#define EDP_LINK_TRAIN_1000MV_0DB_IVB (0x20 <<22)
4885#define EDP_LINK_TRAIN_500MV_3_5DB_IVB (0x02 <<22)
4886#define EDP_LINK_TRAIN_1000MV_3_5DB_IVB (0x22 <<22)
4887#define EDP_LINK_TRAIN_1000MV_6DB_IVB (0x23 <<22)
4888
4889#define EDP_LINK_TRAIN_VOL_EMP_MASK_IVB (0x3f<<22)
4890
4891#define FORCEWAKE 0xA18C
4892#define FORCEWAKE_VLV 0x1300b0
4893#define FORCEWAKE_ACK_VLV 0x1300b4
4894#define FORCEWAKE_MEDIA_VLV 0x1300b8
4895#define FORCEWAKE_ACK_MEDIA_VLV 0x1300bc
4896#define FORCEWAKE_ACK_HSW 0x130044
4897#define FORCEWAKE_ACK 0x130090
4898#define VLV_GTLC_WAKE_CTRL 0x130090
4899#define VLV_GTLC_PW_STATUS 0x130094
4900#define VLV_GTLC_PW_RENDER_STATUS_MASK 0x80
4901#define VLV_GTLC_PW_MEDIA_STATUS_MASK 0x20
4902#define FORCEWAKE_MT 0xa188 /* multi-threaded */
4903#define FORCEWAKE_KERNEL 0x1
4904#define FORCEWAKE_USER 0x2
4905#define FORCEWAKE_MT_ACK 0x130040
4906#define ECOBUS 0xa180
4907#define FORCEWAKE_MT_ENABLE (1<<5)
4908
4909#define GTFIFODBG 0x120000
4910#define GT_FIFO_SBDROPERR (1<<6)
4911#define GT_FIFO_BLOBDROPERR (1<<5)
4912#define GT_FIFO_SB_READ_ABORTERR (1<<4)
4913#define GT_FIFO_DROPERR (1<<3)
4914#define GT_FIFO_OVFERR (1<<2)
4915#define GT_FIFO_IAWRERR (1<<1)
4916#define GT_FIFO_IARDERR (1<<0)
4917
4918#define GTFIFOCTL 0x120008
4919#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
4920#define GT_FIFO_NUM_RESERVED_ENTRIES 20
4921
4922#define HSW_IDICR 0x9008
4923#define IDIHASHMSK(x) (((x) & 0x3f) << 16)
4924#define HSW_EDRAM_PRESENT 0x120010
4925
4926#define GEN6_UCGCTL1 0x9400
4927# define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5)
4928# define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7)
4929
4930#define GEN6_UCGCTL2 0x9404
4931# define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30)
4932# define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22)
4933# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
4934# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
4935# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
4936
4937#define GEN7_UCGCTL4 0x940c
4938#define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25)
4939
4940#define GEN8_UCGCTL6 0x9430
4941#define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1<<14)
4942
4943#define GEN6_RPNSWREQ 0xA008
4944#define GEN6_TURBO_DISABLE (1<<31)
4945#define GEN6_FREQUENCY(x) ((x)<<25)
4946#define HSW_FREQUENCY(x) ((x)<<24)
4947#define GEN6_OFFSET(x) ((x)<<19)
4948#define GEN6_AGGRESSIVE_TURBO (0<<15)
4949#define GEN6_RC_VIDEO_FREQ 0xA00C
4950#define GEN6_RC_CONTROL 0xA090
4951#define GEN6_RC_CTL_RC6pp_ENABLE (1<<16)
4952#define GEN6_RC_CTL_RC6p_ENABLE (1<<17)
4953#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4954#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4955#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4956#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
4957#define GEN7_RC_CTL_TO_MODE (1<<28)
4958#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4959#define GEN6_RC_CTL_HW_ENABLE (1<<31)
4960#define GEN6_RP_DOWN_TIMEOUT 0xA010
4961#define GEN6_RP_INTERRUPT_LIMITS 0xA014
4962#define GEN6_RPSTAT1 0xA01C
4963#define GEN6_CAGF_SHIFT 8
4964#define HSW_CAGF_SHIFT 7
4965#define GEN6_CAGF_MASK (0x7f << GEN6_CAGF_SHIFT)
4966#define HSW_CAGF_MASK (0x7f << HSW_CAGF_SHIFT)
4967#define GEN6_RP_CONTROL 0xA024
4968#define GEN6_RP_MEDIA_TURBO (1<<11)
4969#define GEN6_RP_MEDIA_MODE_MASK (3<<9)
4970#define GEN6_RP_MEDIA_HW_TURBO_MODE (3<<9)
4971#define GEN6_RP_MEDIA_HW_NORMAL_MODE (2<<9)
4972#define GEN6_RP_MEDIA_HW_MODE (1<<9)
4973#define GEN6_RP_MEDIA_SW_MODE (0<<9)
4974#define GEN6_RP_MEDIA_IS_GFX (1<<8)
4975#define GEN6_RP_ENABLE (1<<7)
4976#define GEN6_RP_UP_IDLE_MIN (0x1<<3)
4977#define GEN6_RP_UP_BUSY_AVG (0x2<<3)
4978#define GEN6_RP_UP_BUSY_CONT (0x4<<3)
4979#define GEN6_RP_DOWN_IDLE_AVG (0x2<<0)
4980#define GEN6_RP_DOWN_IDLE_CONT (0x1<<0)
4981#define GEN6_RP_UP_THRESHOLD 0xA02C
4982#define GEN6_RP_DOWN_THRESHOLD 0xA030
4983#define GEN6_RP_CUR_UP_EI 0xA050
4984#define GEN6_CURICONT_MASK 0xffffff
4985#define GEN6_RP_CUR_UP 0xA054
4986#define GEN6_CURBSYTAVG_MASK 0xffffff
4987#define GEN6_RP_PREV_UP 0xA058
4988#define GEN6_RP_CUR_DOWN_EI 0xA05C
4989#define GEN6_CURIAVG_MASK 0xffffff
4990#define GEN6_RP_CUR_DOWN 0xA060
4991#define GEN6_RP_PREV_DOWN 0xA064
4992#define GEN6_RP_UP_EI 0xA068
4993#define GEN6_RP_DOWN_EI 0xA06C
4994#define GEN6_RP_IDLE_HYSTERSIS 0xA070
4995#define GEN6_RC_STATE 0xA094
4996#define GEN6_RC1_WAKE_RATE_LIMIT 0xA098
4997#define GEN6_RC6_WAKE_RATE_LIMIT 0xA09C
4998#define GEN6_RC6pp_WAKE_RATE_LIMIT 0xA0A0
4999#define GEN6_RC_EVALUATION_INTERVAL 0xA0A8
5000#define GEN6_RC_IDLE_HYSTERSIS 0xA0AC
5001#define GEN6_RC_SLEEP 0xA0B0
5002#define GEN6_RC1e_THRESHOLD 0xA0B4
5003#define GEN6_RC6_THRESHOLD 0xA0B8
5004#define GEN6_RC6p_THRESHOLD 0xA0BC
5005#define GEN6_RC6pp_THRESHOLD 0xA0C0
5006#define GEN6_PMINTRMSK 0xA168
5007
5008#define GEN6_PMISR 0x44020
5009#define GEN6_PMIMR 0x44024 /* rps_lock */
5010#define GEN6_PMIIR 0x44028
5011#define GEN6_PMIER 0x4402C
5012#define GEN6_PM_MBOX_EVENT (1<<25)
5013#define GEN6_PM_THERMAL_EVENT (1<<24)
5014#define GEN6_PM_RP_DOWN_TIMEOUT (1<<6)
5015#define GEN6_PM_RP_UP_THRESHOLD (1<<5)
5016#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
5017#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
5018#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
5019#define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
5020 GEN6_PM_RP_DOWN_THRESHOLD | \
5021 GEN6_PM_RP_DOWN_TIMEOUT)
5022
5023#define VLV_GTLC_SURVIVABILITY_REG 0x130098
5024#define VLV_GFX_CLK_STATUS_BIT (1<<3)
5025#define VLV_GFX_CLK_FORCE_ON_BIT (1<<2)
5026
5027#define GEN6_GT_GFX_RC6_LOCKED 0x138104
5028#define VLV_COUNTER_CONTROL 0x138104
5029#define VLV_COUNT_RANGE_HIGH (1<<15)
5030#define VLV_MEDIA_RC6_COUNT_EN (1<<1)
5031#define VLV_RENDER_RC6_COUNT_EN (1<<0)
5032#define GEN6_GT_GFX_RC6 0x138108
5033#define GEN6_GT_GFX_RC6p 0x13810C
5034#define GEN6_GT_GFX_RC6pp 0x138110
5035
5036#define GEN6_PCODE_MAILBOX 0x138124
5037#define GEN6_PCODE_READY (1<<31)
5038#define GEN6_READ_OC_PARAMS 0xc
5039#define GEN6_PCODE_WRITE_MIN_FREQ_TABLE 0x8
5040#define GEN6_PCODE_READ_MIN_FREQ_TABLE 0x9
5041#define GEN6_PCODE_WRITE_RC6VIDS 0x4
5042#define GEN6_PCODE_READ_RC6VIDS 0x5
5043#define GEN6_PCODE_READ_D_COMP 0x10
5044#define GEN6_PCODE_WRITE_D_COMP 0x11
5045#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
5046#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
5047#define DISPLAY_IPS_CONTROL 0x19
5048#define GEN6_PCODE_DATA 0x138128
5049#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
5050#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
5051
5052#define GEN6_GT_CORE_STATUS 0x138060
5053#define GEN6_CORE_CPD_STATE_MASK (7<<4)
5054#define GEN6_RCn_MASK 7
5055#define GEN6_RC0 0
5056#define GEN6_RC3 2
5057#define GEN6_RC6 3
5058#define GEN6_RC7 4
5059
5060#define GEN7_MISCCPCTL (0x9424)
5061#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
5062
5063/* IVYBRIDGE DPF */
5064#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
5065#define HSW_L3CDERRST11 0xB208 /* L3CD Error Status register 1 slice 1 */
5066#define GEN7_L3CDERRST1_ROW_MASK (0x7ff<<14)
5067#define GEN7_PARITY_ERROR_VALID (1<<13)
5068#define GEN7_L3CDERRST1_BANK_MASK (3<<11)
5069#define GEN7_L3CDERRST1_SUBBANK_MASK (7<<8)
5070#define GEN7_PARITY_ERROR_ROW(reg) \
5071 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14)
5072#define GEN7_PARITY_ERROR_BANK(reg) \
5073 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11)
5074#define GEN7_PARITY_ERROR_SUBBANK(reg) \
5075 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
5076#define GEN7_L3CDERRST1_ENABLE (1<<7)
5077
5078#define GEN7_L3LOG_BASE 0xB070
5079#define HSW_L3LOG_BASE_SLICE1 0xB270
5080#define GEN7_L3LOG_SIZE 0x80
5081
5082#define GEN7_HALF_SLICE_CHICKEN1 0xe100 /* IVB GT1 + VLV */
5083#define GEN7_HALF_SLICE_CHICKEN1_GT2 0xf100
5084#define GEN7_MAX_PS_THREAD_DEP (8<<12)
5085#define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1<<10)
5086#define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1<<3)
5087
5088#define GEN8_ROW_CHICKEN 0xe4f0
5089#define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE (1<<8)
5090#define STALL_DOP_GATING_DISABLE (1<<5)
5091
5092#define GEN7_ROW_CHICKEN2 0xe4f4
5093#define GEN7_ROW_CHICKEN2_GT2 0xf4f4
5094#define DOP_CLOCK_GATING_DISABLE (1<<0)
5095
5096#define HSW_ROW_CHICKEN3 0xe49c
5097#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
5098
5099#define HALF_SLICE_CHICKEN3 0xe184
5100#define GEN8_CENTROID_PIXEL_OPT_DIS (1<<8)
5101#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
5102
5103#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
5104#define INTEL_AUDIO_DEVCL 0x808629FB
5105#define INTEL_AUDIO_DEVBLC 0x80862801
5106#define INTEL_AUDIO_DEVCTG 0x80862802
5107
5108#define G4X_AUD_CNTL_ST 0x620B4
5109#define G4X_ELDV_DEVCL_DEVBLC (1 << 13)
5110#define G4X_ELDV_DEVCTG (1 << 14)
5111#define G4X_ELD_ADDR (0xf << 5)
5112#define G4X_ELD_ACK (1 << 4)
5113#define G4X_HDMIW_HDMIEDID 0x6210C
5114
5115#define IBX_HDMIW_HDMIEDID_A 0xE2050
5116#define IBX_HDMIW_HDMIEDID_B 0xE2150
5117#define IBX_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5118 IBX_HDMIW_HDMIEDID_A, \
5119 IBX_HDMIW_HDMIEDID_B)
5120#define IBX_AUD_CNTL_ST_A 0xE20B4
5121#define IBX_AUD_CNTL_ST_B 0xE21B4
5122#define IBX_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5123 IBX_AUD_CNTL_ST_A, \
5124 IBX_AUD_CNTL_ST_B)
5125#define IBX_ELD_BUFFER_SIZE (0x1f << 10)
5126#define IBX_ELD_ADDRESS (0x1f << 5)
5127#define IBX_ELD_ACK (1 << 4)
5128#define IBX_AUD_CNTL_ST2 0xE20C0
5129#define IBX_ELD_VALIDB (1 << 0)
5130#define IBX_CP_READYB (1 << 1)
5131
5132#define CPT_HDMIW_HDMIEDID_A 0xE5050
5133#define CPT_HDMIW_HDMIEDID_B 0xE5150
5134#define CPT_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5135 CPT_HDMIW_HDMIEDID_A, \
5136 CPT_HDMIW_HDMIEDID_B)
5137#define CPT_AUD_CNTL_ST_A 0xE50B4
5138#define CPT_AUD_CNTL_ST_B 0xE51B4
5139#define CPT_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5140 CPT_AUD_CNTL_ST_A, \
5141 CPT_AUD_CNTL_ST_B)
5142#define CPT_AUD_CNTRL_ST2 0xE50C0
5143
5144#define VLV_HDMIW_HDMIEDID_A (VLV_DISPLAY_BASE + 0x62050)
5145#define VLV_HDMIW_HDMIEDID_B (VLV_DISPLAY_BASE + 0x62150)
5146#define VLV_HDMIW_HDMIEDID(pipe) _PIPE(pipe, \
5147 VLV_HDMIW_HDMIEDID_A, \
5148 VLV_HDMIW_HDMIEDID_B)
5149#define VLV_AUD_CNTL_ST_A (VLV_DISPLAY_BASE + 0x620B4)
5150#define VLV_AUD_CNTL_ST_B (VLV_DISPLAY_BASE + 0x621B4)
5151#define VLV_AUD_CNTL_ST(pipe) _PIPE(pipe, \
5152 VLV_AUD_CNTL_ST_A, \
5153 VLV_AUD_CNTL_ST_B)
5154#define VLV_AUD_CNTL_ST2 (VLV_DISPLAY_BASE + 0x620C0)
5155
5156/* These are the 4 32-bit write offset registers for each stream
5157 * output buffer. It determines the offset from the
5158 * 3DSTATE_SO_BUFFERs that the next streamed vertex output goes to.
5159 */
5160#define GEN7_SO_WRITE_OFFSET(n) (0x5280 + (n) * 4)
5161
5162#define IBX_AUD_CONFIG_A 0xe2000
5163#define IBX_AUD_CONFIG_B 0xe2100
5164#define IBX_AUD_CFG(pipe) _PIPE(pipe, \
5165 IBX_AUD_CONFIG_A, \
5166 IBX_AUD_CONFIG_B)
5167#define CPT_AUD_CONFIG_A 0xe5000
5168#define CPT_AUD_CONFIG_B 0xe5100
5169#define CPT_AUD_CFG(pipe) _PIPE(pipe, \
5170 CPT_AUD_CONFIG_A, \
5171 CPT_AUD_CONFIG_B)
5172#define VLV_AUD_CONFIG_A (VLV_DISPLAY_BASE + 0x62000)
5173#define VLV_AUD_CONFIG_B (VLV_DISPLAY_BASE + 0x62100)
5174#define VLV_AUD_CFG(pipe) _PIPE(pipe, \
5175 VLV_AUD_CONFIG_A, \
5176 VLV_AUD_CONFIG_B)
5177
5178#define AUD_CONFIG_N_VALUE_INDEX (1 << 29)
5179#define AUD_CONFIG_N_PROG_ENABLE (1 << 28)
5180#define AUD_CONFIG_UPPER_N_SHIFT 20
5181#define AUD_CONFIG_UPPER_N_VALUE (0xff << 20)
5182#define AUD_CONFIG_LOWER_N_SHIFT 4
5183#define AUD_CONFIG_LOWER_N_VALUE (0xfff << 4)
5184#define AUD_CONFIG_PIXEL_CLOCK_HDMI_SHIFT 16
5185#define AUD_CONFIG_PIXEL_CLOCK_HDMI_MASK (0xf << 16)
5186#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 (0 << 16)
5187#define AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 (1 << 16)
5188#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 (2 << 16)
5189#define AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 (3 << 16)
5190#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 (4 << 16)
5191#define AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 (5 << 16)
5192#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 (6 << 16)
5193#define AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 (7 << 16)
5194#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 (8 << 16)
5195#define AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 (9 << 16)
5196#define AUD_CONFIG_DISABLE_NCTS (1 << 3)
5197
5198/* HSW Audio */
5199#define HSW_AUD_CONFIG_A 0x65000 /* Audio Configuration Transcoder A */
5200#define HSW_AUD_CONFIG_B 0x65100 /* Audio Configuration Transcoder B */
5201#define HSW_AUD_CFG(pipe) _PIPE(pipe, \
5202 HSW_AUD_CONFIG_A, \
5203 HSW_AUD_CONFIG_B)
5204
5205#define HSW_AUD_MISC_CTRL_A 0x65010 /* Audio Misc Control Convert 1 */
5206#define HSW_AUD_MISC_CTRL_B 0x65110 /* Audio Misc Control Convert 2 */
5207#define HSW_AUD_MISC_CTRL(pipe) _PIPE(pipe, \
5208 HSW_AUD_MISC_CTRL_A, \
5209 HSW_AUD_MISC_CTRL_B)
5210
5211#define HSW_AUD_DIP_ELD_CTRL_ST_A 0x650b4 /* Audio DIP and ELD Control State Transcoder A */
5212#define HSW_AUD_DIP_ELD_CTRL_ST_B 0x651b4 /* Audio DIP and ELD Control State Transcoder B */
5213#define HSW_AUD_DIP_ELD_CTRL(pipe) _PIPE(pipe, \
5214 HSW_AUD_DIP_ELD_CTRL_ST_A, \
5215 HSW_AUD_DIP_ELD_CTRL_ST_B)
5216
5217/* Audio Digital Converter */
5218#define HSW_AUD_DIG_CNVT_1 0x65080 /* Audio Converter 1 */
5219#define HSW_AUD_DIG_CNVT_2 0x65180 /* Audio Converter 1 */
5220#define AUD_DIG_CNVT(pipe) _PIPE(pipe, \
5221 HSW_AUD_DIG_CNVT_1, \
5222 HSW_AUD_DIG_CNVT_2)
5223#define DIP_PORT_SEL_MASK 0x3
5224
5225#define HSW_AUD_EDID_DATA_A 0x65050
5226#define HSW_AUD_EDID_DATA_B 0x65150
5227#define HSW_AUD_EDID_DATA(pipe) _PIPE(pipe, \
5228 HSW_AUD_EDID_DATA_A, \
5229 HSW_AUD_EDID_DATA_B)
5230
5231#define HSW_AUD_PIPE_CONV_CFG 0x6507c /* Audio pipe and converter configs */
5232#define HSW_AUD_PIN_ELD_CP_VLD 0x650c0 /* Audio ELD and CP Ready Status */
5233#define AUDIO_INACTIVE_C (1<<11)
5234#define AUDIO_INACTIVE_B (1<<7)
5235#define AUDIO_INACTIVE_A (1<<3)
5236#define AUDIO_OUTPUT_ENABLE_A (1<<2)
5237#define AUDIO_OUTPUT_ENABLE_B (1<<6)
5238#define AUDIO_OUTPUT_ENABLE_C (1<<10)
5239#define AUDIO_ELD_VALID_A (1<<0)
5240#define AUDIO_ELD_VALID_B (1<<4)
5241#define AUDIO_ELD_VALID_C (1<<8)
5242#define AUDIO_CP_READY_A (1<<1)
5243#define AUDIO_CP_READY_B (1<<5)
5244#define AUDIO_CP_READY_C (1<<9)
5245
5246/* HSW Power Wells */
5247#define HSW_PWR_WELL_BIOS 0x45400 /* CTL1 */
5248#define HSW_PWR_WELL_DRIVER 0x45404 /* CTL2 */
5249#define HSW_PWR_WELL_KVMR 0x45408 /* CTL3 */
5250#define HSW_PWR_WELL_DEBUG 0x4540C /* CTL4 */
5251#define HSW_PWR_WELL_ENABLE_REQUEST (1<<31)
5252#define HSW_PWR_WELL_STATE_ENABLED (1<<30)
5253#define HSW_PWR_WELL_CTL5 0x45410
5254#define HSW_PWR_WELL_ENABLE_SINGLE_STEP (1<<31)
5255#define HSW_PWR_WELL_PWR_GATE_OVERRIDE (1<<20)
5256#define HSW_PWR_WELL_FORCE_ON (1<<19)
5257#define HSW_PWR_WELL_CTL6 0x45414
5258
5259/* Per-pipe DDI Function Control */
5260#define TRANS_DDI_FUNC_CTL_A 0x60400
5261#define TRANS_DDI_FUNC_CTL_B 0x61400
5262#define TRANS_DDI_FUNC_CTL_C 0x62400
5263#define TRANS_DDI_FUNC_CTL_EDP 0x6F400
5264#define TRANS_DDI_FUNC_CTL(tran) _TRANSCODER2(tran, TRANS_DDI_FUNC_CTL_A)
5265
5266#define TRANS_DDI_FUNC_ENABLE (1<<31)
5267/* Those bits are ignored by pipe EDP since it can only connect to DDI A */
5268#define TRANS_DDI_PORT_MASK (7<<28)
5269#define TRANS_DDI_SELECT_PORT(x) ((x)<<28)
5270#define TRANS_DDI_PORT_NONE (0<<28)
5271#define TRANS_DDI_MODE_SELECT_MASK (7<<24)
5272#define TRANS_DDI_MODE_SELECT_HDMI (0<<24)
5273#define TRANS_DDI_MODE_SELECT_DVI (1<<24)
5274#define TRANS_DDI_MODE_SELECT_DP_SST (2<<24)
5275#define TRANS_DDI_MODE_SELECT_DP_MST (3<<24)
5276#define TRANS_DDI_MODE_SELECT_FDI (4<<24)
5277#define TRANS_DDI_BPC_MASK (7<<20)
5278#define TRANS_DDI_BPC_8 (0<<20)
5279#define TRANS_DDI_BPC_10 (1<<20)
5280#define TRANS_DDI_BPC_6 (2<<20)
5281#define TRANS_DDI_BPC_12 (3<<20)
5282#define TRANS_DDI_PVSYNC (1<<17)
5283#define TRANS_DDI_PHSYNC (1<<16)
5284#define TRANS_DDI_EDP_INPUT_MASK (7<<12)
5285#define TRANS_DDI_EDP_INPUT_A_ON (0<<12)
5286#define TRANS_DDI_EDP_INPUT_A_ONOFF (4<<12)
5287#define TRANS_DDI_EDP_INPUT_B_ONOFF (5<<12)
5288#define TRANS_DDI_EDP_INPUT_C_ONOFF (6<<12)
5289#define TRANS_DDI_BFI_ENABLE (1<<4)
5290
5291/* DisplayPort Transport Control */
5292#define DP_TP_CTL_A 0x64040
5293#define DP_TP_CTL_B 0x64140
5294#define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B)
5295#define DP_TP_CTL_ENABLE (1<<31)
5296#define DP_TP_CTL_MODE_SST (0<<27)
5297#define DP_TP_CTL_MODE_MST (1<<27)
5298#define DP_TP_CTL_ENHANCED_FRAME_ENABLE (1<<18)
5299#define DP_TP_CTL_FDI_AUTOTRAIN (1<<15)
5300#define DP_TP_CTL_LINK_TRAIN_MASK (7<<8)
5301#define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8)
5302#define DP_TP_CTL_LINK_TRAIN_PAT2 (1<<8)
5303#define DP_TP_CTL_LINK_TRAIN_PAT3 (4<<8)
5304#define DP_TP_CTL_LINK_TRAIN_IDLE (2<<8)
5305#define DP_TP_CTL_LINK_TRAIN_NORMAL (3<<8)
5306#define DP_TP_CTL_SCRAMBLE_DISABLE (1<<7)
5307
5308/* DisplayPort Transport Status */
5309#define DP_TP_STATUS_A 0x64044
5310#define DP_TP_STATUS_B 0x64144
5311#define DP_TP_STATUS(port) _PORT(port, DP_TP_STATUS_A, DP_TP_STATUS_B)
5312#define DP_TP_STATUS_IDLE_DONE (1<<25)
5313#define DP_TP_STATUS_AUTOTRAIN_DONE (1<<12)
5314
5315/* DDI Buffer Control */
5316#define DDI_BUF_CTL_A 0x64000
5317#define DDI_BUF_CTL_B 0x64100
5318#define DDI_BUF_CTL(port) _PORT(port, DDI_BUF_CTL_A, DDI_BUF_CTL_B)
5319#define DDI_BUF_CTL_ENABLE (1<<31)
5320/* Haswell */
5321#define DDI_BUF_EMP_400MV_0DB_HSW (0<<24) /* Sel0 */
5322#define DDI_BUF_EMP_400MV_3_5DB_HSW (1<<24) /* Sel1 */
5323#define DDI_BUF_EMP_400MV_6DB_HSW (2<<24) /* Sel2 */
5324#define DDI_BUF_EMP_400MV_9_5DB_HSW (3<<24) /* Sel3 */
5325#define DDI_BUF_EMP_600MV_0DB_HSW (4<<24) /* Sel4 */
5326#define DDI_BUF_EMP_600MV_3_5DB_HSW (5<<24) /* Sel5 */
5327#define DDI_BUF_EMP_600MV_6DB_HSW (6<<24) /* Sel6 */
5328#define DDI_BUF_EMP_800MV_0DB_HSW (7<<24) /* Sel7 */
5329#define DDI_BUF_EMP_800MV_3_5DB_HSW (8<<24) /* Sel8 */
5330/* Broadwell */
5331#define DDI_BUF_EMP_400MV_0DB_BDW (0<<24) /* Sel0 */
5332#define DDI_BUF_EMP_400MV_3_5DB_BDW (1<<24) /* Sel1 */
5333#define DDI_BUF_EMP_400MV_6DB_BDW (2<<24) /* Sel2 */
5334#define DDI_BUF_EMP_600MV_0DB_BDW (3<<24) /* Sel3 */
5335#define DDI_BUF_EMP_600MV_3_5DB_BDW (4<<24) /* Sel4 */
5336#define DDI_BUF_EMP_600MV_6DB_BDW (5<<24) /* Sel5 */
5337#define DDI_BUF_EMP_800MV_0DB_BDW (6<<24) /* Sel6 */
5338#define DDI_BUF_EMP_800MV_3_5DB_BDW (7<<24) /* Sel7 */
5339#define DDI_BUF_EMP_1200MV_0DB_BDW (8<<24) /* Sel8 */
5340#define DDI_BUF_EMP_MASK (0xf<<24)
5341#define DDI_BUF_PORT_REVERSAL (1<<16)
5342#define DDI_BUF_IS_IDLE (1<<7)
5343#define DDI_A_4_LANES (1<<4)
5344#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
5345#define DDI_INIT_DISPLAY_DETECTED (1<<0)
5346
5347/* DDI Buffer Translations */
5348#define DDI_BUF_TRANS_A 0x64E00
5349#define DDI_BUF_TRANS_B 0x64E60
5350#define DDI_BUF_TRANS(port) _PORT(port, DDI_BUF_TRANS_A, DDI_BUF_TRANS_B)
5351
5352/* Sideband Interface (SBI) is programmed indirectly, via
5353 * SBI_ADDR, which contains the register offset; and SBI_DATA,
5354 * which contains the payload */
5355#define SBI_ADDR 0xC6000
5356#define SBI_DATA 0xC6004
5357#define SBI_CTL_STAT 0xC6008
5358#define SBI_CTL_DEST_ICLK (0x0<<16)
5359#define SBI_CTL_DEST_MPHY (0x1<<16)
5360#define SBI_CTL_OP_IORD (0x2<<8)
5361#define SBI_CTL_OP_IOWR (0x3<<8)
5362#define SBI_CTL_OP_CRRD (0x6<<8)
5363#define SBI_CTL_OP_CRWR (0x7<<8)
5364#define SBI_RESPONSE_FAIL (0x1<<1)
5365#define SBI_RESPONSE_SUCCESS (0x0<<1)
5366#define SBI_BUSY (0x1<<0)
5367#define SBI_READY (0x0<<0)
5368
5369/* SBI offsets */
5370#define SBI_SSCDIVINTPHASE6 0x0600
5371#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1)
5372#define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1)
5373#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8)
5374#define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8)
5375#define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15)
5376#define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0)
5377#define SBI_SSCCTL 0x020c
5378#define SBI_SSCCTL6 0x060C
5379#define SBI_SSCCTL_PATHALT (1<<3)
5380#define SBI_SSCCTL_DISABLE (1<<0)
5381#define SBI_SSCAUXDIV6 0x0610
5382#define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4)
5383#define SBI_DBUFF0 0x2a00
5384#define SBI_GEN0 0x1f00
5385#define SBI_GEN0_CFG_BUFFENABLE_DISABLE (1<<0)
5386
5387/* LPT PIXCLK_GATE */
5388#define PIXCLK_GATE 0xC6020
5389#define PIXCLK_GATE_UNGATE (1<<0)
5390#define PIXCLK_GATE_GATE (0<<0)
5391
5392/* SPLL */
5393#define SPLL_CTL 0x46020
5394#define SPLL_PLL_ENABLE (1<<31)
5395#define SPLL_PLL_SSC (1<<28)
5396#define SPLL_PLL_NON_SSC (2<<28)
5397#define SPLL_PLL_LCPLL (3<<28)
5398#define SPLL_PLL_REF_MASK (3<<28)
5399#define SPLL_PLL_FREQ_810MHz (0<<26)
5400#define SPLL_PLL_FREQ_1350MHz (1<<26)
5401#define SPLL_PLL_FREQ_2700MHz (2<<26)
5402#define SPLL_PLL_FREQ_MASK (3<<26)
5403
5404/* WRPLL */
5405#define WRPLL_CTL1 0x46040
5406#define WRPLL_CTL2 0x46060
5407#define WRPLL_PLL_ENABLE (1<<31)
5408#define WRPLL_PLL_SELECT_SSC (0x01<<28)
5409#define WRPLL_PLL_SELECT_NON_SSC (0x02<<28)
5410#define WRPLL_PLL_SELECT_LCPLL_2700 (0x03<<28)
5411/* WRPLL divider programming */
5412#define WRPLL_DIVIDER_REFERENCE(x) ((x)<<0)
5413#define WRPLL_DIVIDER_REF_MASK (0xff)
5414#define WRPLL_DIVIDER_POST(x) ((x)<<8)
5415#define WRPLL_DIVIDER_POST_MASK (0x3f<<8)
5416#define WRPLL_DIVIDER_POST_SHIFT 8
5417#define WRPLL_DIVIDER_FEEDBACK(x) ((x)<<16)
5418#define WRPLL_DIVIDER_FB_SHIFT 16
5419#define WRPLL_DIVIDER_FB_MASK (0xff<<16)
5420
5421/* Port clock selection */
5422#define PORT_CLK_SEL_A 0x46100
5423#define PORT_CLK_SEL_B 0x46104
5424#define PORT_CLK_SEL(port) _PORT(port, PORT_CLK_SEL_A, PORT_CLK_SEL_B)
5425#define PORT_CLK_SEL_LCPLL_2700 (0<<29)
5426#define PORT_CLK_SEL_LCPLL_1350 (1<<29)
5427#define PORT_CLK_SEL_LCPLL_810 (2<<29)
5428#define PORT_CLK_SEL_SPLL (3<<29)
5429#define PORT_CLK_SEL_WRPLL1 (4<<29)
5430#define PORT_CLK_SEL_WRPLL2 (5<<29)
5431#define PORT_CLK_SEL_NONE (7<<29)
5432#define PORT_CLK_SEL_MASK (7<<29)
5433
5434/* Transcoder clock selection */
5435#define TRANS_CLK_SEL_A 0x46140
5436#define TRANS_CLK_SEL_B 0x46144
5437#define TRANS_CLK_SEL(tran) _TRANSCODER(tran, TRANS_CLK_SEL_A, TRANS_CLK_SEL_B)
5438/* For each transcoder, we need to select the corresponding port clock */
5439#define TRANS_CLK_SEL_DISABLED (0x0<<29)
5440#define TRANS_CLK_SEL_PORT(x) ((x+1)<<29)
5441
5442#define TRANSA_MSA_MISC 0x60410
5443#define TRANSB_MSA_MISC 0x61410
5444#define TRANSC_MSA_MISC 0x62410
5445#define TRANS_EDP_MSA_MISC 0x6f410
5446#define TRANS_MSA_MISC(tran) _TRANSCODER2(tran, TRANSA_MSA_MISC)
5447
5448#define TRANS_MSA_SYNC_CLK (1<<0)
5449#define TRANS_MSA_6_BPC (0<<5)
5450#define TRANS_MSA_8_BPC (1<<5)
5451#define TRANS_MSA_10_BPC (2<<5)
5452#define TRANS_MSA_12_BPC (3<<5)
5453#define TRANS_MSA_16_BPC (4<<5)
5454
5455/* LCPLL Control */
5456#define LCPLL_CTL 0x130040
5457#define LCPLL_PLL_DISABLE (1<<31)
5458#define LCPLL_PLL_LOCK (1<<30)
5459#define LCPLL_CLK_FREQ_MASK (3<<26)
5460#define LCPLL_CLK_FREQ_450 (0<<26)
5461#define LCPLL_CLK_FREQ_54O_BDW (1<<26)
5462#define LCPLL_CLK_FREQ_337_5_BDW (2<<26)
5463#define LCPLL_CLK_FREQ_675_BDW (3<<26)
5464#define LCPLL_CD_CLOCK_DISABLE (1<<25)
5465#define LCPLL_CD2X_CLOCK_DISABLE (1<<23)
5466#define LCPLL_POWER_DOWN_ALLOW (1<<22)
5467#define LCPLL_CD_SOURCE_FCLK (1<<21)
5468#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
5469
5470#define D_COMP (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
5471#define D_COMP_RCOMP_IN_PROGRESS (1<<9)
5472#define D_COMP_COMP_FORCE (1<<8)
5473#define D_COMP_COMP_DISABLE (1<<0)
5474
5475/* Pipe WM_LINETIME - watermark line time */
5476#define PIPE_WM_LINETIME_A 0x45270
5477#define PIPE_WM_LINETIME_B 0x45274
5478#define PIPE_WM_LINETIME(pipe) _PIPE(pipe, PIPE_WM_LINETIME_A, \
5479 PIPE_WM_LINETIME_B)
5480#define PIPE_WM_LINETIME_MASK (0x1ff)
5481#define PIPE_WM_LINETIME_TIME(x) ((x))
5482#define PIPE_WM_LINETIME_IPS_LINETIME_MASK (0x1ff<<16)
5483#define PIPE_WM_LINETIME_IPS_LINETIME(x) ((x)<<16)
5484
5485/* SFUSE_STRAP */
5486#define SFUSE_STRAP 0xc2014
5487#define SFUSE_STRAP_FUSE_LOCK (1<<13)
5488#define SFUSE_STRAP_DISPLAY_DISABLED (1<<7)
5489#define SFUSE_STRAP_DDIB_DETECTED (1<<2)
5490#define SFUSE_STRAP_DDIC_DETECTED (1<<1)
5491#define SFUSE_STRAP_DDID_DETECTED (1<<0)
5492
5493#define WM_MISC 0x45260
5494#define WM_MISC_DATA_PARTITION_5_6 (1 << 0)
5495
5496#define WM_DBG 0x45280
5497#define WM_DBG_DISALLOW_MULTIPLE_LP (1<<0)
5498#define WM_DBG_DISALLOW_MAXFIFO (1<<1)
5499#define WM_DBG_DISALLOW_SPRITE (1<<2)
5500
5501/* pipe CSC */
5502#define _PIPE_A_CSC_COEFF_RY_GY 0x49010
5503#define _PIPE_A_CSC_COEFF_BY 0x49014
5504#define _PIPE_A_CSC_COEFF_RU_GU 0x49018
5505#define _PIPE_A_CSC_COEFF_BU 0x4901c
5506#define _PIPE_A_CSC_COEFF_RV_GV 0x49020
5507#define _PIPE_A_CSC_COEFF_BV 0x49024
5508#define _PIPE_A_CSC_MODE 0x49028
5509#define CSC_BLACK_SCREEN_OFFSET (1 << 2)
5510#define CSC_POSITION_BEFORE_GAMMA (1 << 1)
5511#define CSC_MODE_YUV_TO_RGB (1 << 0)
5512#define _PIPE_A_CSC_PREOFF_HI 0x49030
5513#define _PIPE_A_CSC_PREOFF_ME 0x49034
5514#define _PIPE_A_CSC_PREOFF_LO 0x49038
5515#define _PIPE_A_CSC_POSTOFF_HI 0x49040
5516#define _PIPE_A_CSC_POSTOFF_ME 0x49044
5517#define _PIPE_A_CSC_POSTOFF_LO 0x49048
5518
5519#define _PIPE_B_CSC_COEFF_RY_GY 0x49110
5520#define _PIPE_B_CSC_COEFF_BY 0x49114
5521#define _PIPE_B_CSC_COEFF_RU_GU 0x49118
5522#define _PIPE_B_CSC_COEFF_BU 0x4911c
5523#define _PIPE_B_CSC_COEFF_RV_GV 0x49120
5524#define _PIPE_B_CSC_COEFF_BV 0x49124
5525#define _PIPE_B_CSC_MODE 0x49128
5526#define _PIPE_B_CSC_PREOFF_HI 0x49130
5527#define _PIPE_B_CSC_PREOFF_ME 0x49134
5528#define _PIPE_B_CSC_PREOFF_LO 0x49138
5529#define _PIPE_B_CSC_POSTOFF_HI 0x49140
5530#define _PIPE_B_CSC_POSTOFF_ME 0x49144
5531#define _PIPE_B_CSC_POSTOFF_LO 0x49148
5532
5533#define PIPE_CSC_COEFF_RY_GY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RY_GY, _PIPE_B_CSC_COEFF_RY_GY)
5534#define PIPE_CSC_COEFF_BY(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BY, _PIPE_B_CSC_COEFF_BY)
5535#define PIPE_CSC_COEFF_RU_GU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RU_GU, _PIPE_B_CSC_COEFF_RU_GU)
5536#define PIPE_CSC_COEFF_BU(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BU, _PIPE_B_CSC_COEFF_BU)
5537#define PIPE_CSC_COEFF_RV_GV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_RV_GV, _PIPE_B_CSC_COEFF_RV_GV)
5538#define PIPE_CSC_COEFF_BV(pipe) _PIPE(pipe, _PIPE_A_CSC_COEFF_BV, _PIPE_B_CSC_COEFF_BV)
5539#define PIPE_CSC_MODE(pipe) _PIPE(pipe, _PIPE_A_CSC_MODE, _PIPE_B_CSC_MODE)
5540#define PIPE_CSC_PREOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_HI, _PIPE_B_CSC_PREOFF_HI)
5541#define PIPE_CSC_PREOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_ME, _PIPE_B_CSC_PREOFF_ME)
5542#define PIPE_CSC_PREOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_PREOFF_LO, _PIPE_B_CSC_PREOFF_LO)
5543#define PIPE_CSC_POSTOFF_HI(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_HI, _PIPE_B_CSC_POSTOFF_HI)
5544#define PIPE_CSC_POSTOFF_ME(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_ME, _PIPE_B_CSC_POSTOFF_ME)
5545#define PIPE_CSC_POSTOFF_LO(pipe) _PIPE(pipe, _PIPE_A_CSC_POSTOFF_LO, _PIPE_B_CSC_POSTOFF_LO)
5546
5547/* VLV MIPI registers */
5548
5549#define _MIPIA_PORT_CTRL (VLV_DISPLAY_BASE + 0x61190)
5550#define _MIPIB_PORT_CTRL (VLV_DISPLAY_BASE + 0x61700)
5551#define MIPI_PORT_CTRL(pipe) _PIPE(pipe, _MIPIA_PORT_CTRL, _MIPIB_PORT_CTRL)
5552#define DPI_ENABLE (1 << 31) /* A + B */
5553#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
5554#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
5555#define DUAL_LINK_MODE_MASK (1 << 26)
5556#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
5557#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
5558#define DITHERING_ENABLE (1 << 25) /* A + B */
5559#define FLOPPED_HSTX (1 << 23)
5560#define DE_INVERT (1 << 19) /* XXX */
5561#define MIPIA_FLISDSI_DELAY_COUNT_SHIFT 18
5562#define MIPIA_FLISDSI_DELAY_COUNT_MASK (0xf << 18)
5563#define AFE_LATCHOUT (1 << 17)
5564#define LP_OUTPUT_HOLD (1 << 16)
5565#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_SHIFT 15
5566#define MIPIB_FLISDSI_DELAY_COUNT_HIGH_MASK (1 << 15)
5567#define MIPIB_MIPI4DPHY_DELAY_COUNT_SHIFT 11
5568#define MIPIB_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 11)
5569#define CSB_SHIFT 9
5570#define CSB_MASK (3 << 9)
5571#define CSB_20MHZ (0 << 9)
5572#define CSB_10MHZ (1 << 9)
5573#define CSB_40MHZ (2 << 9)
5574#define BANDGAP_MASK (1 << 8)
5575#define BANDGAP_PNW_CIRCUIT (0 << 8)
5576#define BANDGAP_LNC_CIRCUIT (1 << 8)
5577#define MIPIB_FLISDSI_DELAY_COUNT_LOW_SHIFT 5
5578#define MIPIB_FLISDSI_DELAY_COUNT_LOW_MASK (7 << 5)
5579#define TEARING_EFFECT_DELAY (1 << 4) /* A + B */
5580#define TEARING_EFFECT_SHIFT 2 /* A + B */
5581#define TEARING_EFFECT_MASK (3 << 2)
5582#define TEARING_EFFECT_OFF (0 << 2)
5583#define TEARING_EFFECT_DSI (1 << 2)
5584#define TEARING_EFFECT_GPIO (2 << 2)
5585#define LANE_CONFIGURATION_SHIFT 0
5586#define LANE_CONFIGURATION_MASK (3 << 0)
5587#define LANE_CONFIGURATION_4LANE (0 << 0)
5588#define LANE_CONFIGURATION_DUAL_LINK_A (1 << 0)
5589#define LANE_CONFIGURATION_DUAL_LINK_B (2 << 0)
5590
5591#define _MIPIA_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61194)
5592#define _MIPIB_TEARING_CTRL (VLV_DISPLAY_BASE + 0x61704)
5593#define MIPI_TEARING_CTRL(pipe) _PIPE(pipe, _MIPIA_TEARING_CTRL, _MIPIB_TEARING_CTRL)
5594#define TEARING_EFFECT_DELAY_SHIFT 0
5595#define TEARING_EFFECT_DELAY_MASK (0xffff << 0)
5596
5597/* XXX: all bits reserved */
5598#define _MIPIA_AUTOPWG (VLV_DISPLAY_BASE + 0x611a0)
5599
5600/* MIPI DSI Controller and D-PHY registers */
5601
5602#define _MIPIA_DEVICE_READY (VLV_DISPLAY_BASE + 0xb000)
5603#define _MIPIB_DEVICE_READY (VLV_DISPLAY_BASE + 0xb800)
5604#define MIPI_DEVICE_READY(pipe) _PIPE(pipe, _MIPIA_DEVICE_READY, _MIPIB_DEVICE_READY)
5605#define BUS_POSSESSION (1 << 3) /* set to give bus to receiver */
5606#define ULPS_STATE_MASK (3 << 1)
5607#define ULPS_STATE_ENTER (2 << 1)
5608#define ULPS_STATE_EXIT (1 << 1)
5609#define ULPS_STATE_NORMAL_OPERATION (0 << 1)
5610#define DEVICE_READY (1 << 0)
5611
5612#define _MIPIA_INTR_STAT (VLV_DISPLAY_BASE + 0xb004)
5613#define _MIPIB_INTR_STAT (VLV_DISPLAY_BASE + 0xb804)
5614#define MIPI_INTR_STAT(pipe) _PIPE(pipe, _MIPIA_INTR_STAT, _MIPIB_INTR_STAT)
5615#define _MIPIA_INTR_EN (VLV_DISPLAY_BASE + 0xb008)
5616#define _MIPIB_INTR_EN (VLV_DISPLAY_BASE + 0xb808)
5617#define MIPI_INTR_EN(pipe) _PIPE(pipe, _MIPIA_INTR_EN, _MIPIB_INTR_EN)
5618#define TEARING_EFFECT (1 << 31)
5619#define SPL_PKT_SENT_INTERRUPT (1 << 30)
5620#define GEN_READ_DATA_AVAIL (1 << 29)
5621#define LP_GENERIC_WR_FIFO_FULL (1 << 28)
5622#define HS_GENERIC_WR_FIFO_FULL (1 << 27)
5623#define RX_PROT_VIOLATION (1 << 26)
5624#define RX_INVALID_TX_LENGTH (1 << 25)
5625#define ACK_WITH_NO_ERROR (1 << 24)
5626#define TURN_AROUND_ACK_TIMEOUT (1 << 23)
5627#define LP_RX_TIMEOUT (1 << 22)
5628#define HS_TX_TIMEOUT (1 << 21)
5629#define DPI_FIFO_UNDERRUN (1 << 20)
5630#define LOW_CONTENTION (1 << 19)
5631#define HIGH_CONTENTION (1 << 18)
5632#define TXDSI_VC_ID_INVALID (1 << 17)
5633#define TXDSI_DATA_TYPE_NOT_RECOGNISED (1 << 16)
5634#define TXCHECKSUM_ERROR (1 << 15)
5635#define TXECC_MULTIBIT_ERROR (1 << 14)
5636#define TXECC_SINGLE_BIT_ERROR (1 << 13)
5637#define TXFALSE_CONTROL_ERROR (1 << 12)
5638#define RXDSI_VC_ID_INVALID (1 << 11)
5639#define RXDSI_DATA_TYPE_NOT_REGOGNISED (1 << 10)
5640#define RXCHECKSUM_ERROR (1 << 9)
5641#define RXECC_MULTIBIT_ERROR (1 << 8)
5642#define RXECC_SINGLE_BIT_ERROR (1 << 7)
5643#define RXFALSE_CONTROL_ERROR (1 << 6)
5644#define RXHS_RECEIVE_TIMEOUT_ERROR (1 << 5)
5645#define RX_LP_TX_SYNC_ERROR (1 << 4)
5646#define RXEXCAPE_MODE_ENTRY_ERROR (1 << 3)
5647#define RXEOT_SYNC_ERROR (1 << 2)
5648#define RXSOT_SYNC_ERROR (1 << 1)
5649#define RXSOT_ERROR (1 << 0)
5650
5651#define _MIPIA_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb00c)
5652#define _MIPIB_DSI_FUNC_PRG (VLV_DISPLAY_BASE + 0xb80c)
5653#define MIPI_DSI_FUNC_PRG(pipe) _PIPE(pipe, _MIPIA_DSI_FUNC_PRG, _MIPIB_DSI_FUNC_PRG)
5654#define CMD_MODE_DATA_WIDTH_MASK (7 << 13)
5655#define CMD_MODE_NOT_SUPPORTED (0 << 13)
5656#define CMD_MODE_DATA_WIDTH_16_BIT (1 << 13)
5657#define CMD_MODE_DATA_WIDTH_9_BIT (2 << 13)
5658#define CMD_MODE_DATA_WIDTH_8_BIT (3 << 13)
5659#define CMD_MODE_DATA_WIDTH_OPTION1 (4 << 13)
5660#define CMD_MODE_DATA_WIDTH_OPTION2 (5 << 13)
5661#define VID_MODE_FORMAT_MASK (0xf << 7)
5662#define VID_MODE_NOT_SUPPORTED (0 << 7)
5663#define VID_MODE_FORMAT_RGB565 (1 << 7)
5664#define VID_MODE_FORMAT_RGB666 (2 << 7)
5665#define VID_MODE_FORMAT_RGB666_LOOSE (3 << 7)
5666#define VID_MODE_FORMAT_RGB888 (4 << 7)
5667#define CMD_MODE_CHANNEL_NUMBER_SHIFT 5
5668#define CMD_MODE_CHANNEL_NUMBER_MASK (3 << 5)
5669#define VID_MODE_CHANNEL_NUMBER_SHIFT 3
5670#define VID_MODE_CHANNEL_NUMBER_MASK (3 << 3)
5671#define DATA_LANES_PRG_REG_SHIFT 0
5672#define DATA_LANES_PRG_REG_MASK (7 << 0)
5673
5674#define _MIPIA_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb010)
5675#define _MIPIB_HS_TX_TIMEOUT (VLV_DISPLAY_BASE + 0xb810)
5676#define MIPI_HS_TX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_HS_TX_TIMEOUT, _MIPIB_HS_TX_TIMEOUT)
5677#define HIGH_SPEED_TX_TIMEOUT_COUNTER_MASK 0xffffff
5678
5679#define _MIPIA_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb014)
5680#define _MIPIB_LP_RX_TIMEOUT (VLV_DISPLAY_BASE + 0xb814)
5681#define MIPI_LP_RX_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_LP_RX_TIMEOUT, _MIPIB_LP_RX_TIMEOUT)
5682#define LOW_POWER_RX_TIMEOUT_COUNTER_MASK 0xffffff
5683
5684#define _MIPIA_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb018)
5685#define _MIPIB_TURN_AROUND_TIMEOUT (VLV_DISPLAY_BASE + 0xb818)
5686#define MIPI_TURN_AROUND_TIMEOUT(pipe) _PIPE(pipe, _MIPIA_TURN_AROUND_TIMEOUT, _MIPIB_TURN_AROUND_TIMEOUT)
5687#define TURN_AROUND_TIMEOUT_MASK 0x3f
5688
5689#define _MIPIA_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb01c)
5690#define _MIPIB_DEVICE_RESET_TIMER (VLV_DISPLAY_BASE + 0xb81c)
5691#define MIPI_DEVICE_RESET_TIMER(pipe) _PIPE(pipe, _MIPIA_DEVICE_RESET_TIMER, _MIPIB_DEVICE_RESET_TIMER)
5692#define DEVICE_RESET_TIMER_MASK 0xffff
5693
5694#define _MIPIA_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb020)
5695#define _MIPIB_DPI_RESOLUTION (VLV_DISPLAY_BASE + 0xb820)
5696#define MIPI_DPI_RESOLUTION(pipe) _PIPE(pipe, _MIPIA_DPI_RESOLUTION, _MIPIB_DPI_RESOLUTION)
5697#define VERTICAL_ADDRESS_SHIFT 16
5698#define VERTICAL_ADDRESS_MASK (0xffff << 16)
5699#define HORIZONTAL_ADDRESS_SHIFT 0
5700#define HORIZONTAL_ADDRESS_MASK 0xffff
5701
5702#define _MIPIA_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb024)
5703#define _MIPIB_DBI_FIFO_THROTTLE (VLV_DISPLAY_BASE + 0xb824)
5704#define MIPI_DBI_FIFO_THROTTLE(pipe) _PIPE(pipe, _MIPIA_DBI_FIFO_THROTTLE, _MIPIB_DBI_FIFO_THROTTLE)
5705#define DBI_FIFO_EMPTY_HALF (0 << 0)
5706#define DBI_FIFO_EMPTY_QUARTER (1 << 0)
5707#define DBI_FIFO_EMPTY_7_LOCATIONS (2 << 0)
5708
5709/* regs below are bits 15:0 */
5710#define _MIPIA_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb028)
5711#define _MIPIB_HSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb828)
5712#define MIPI_HSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_HSYNC_PADDING_COUNT, _MIPIB_HSYNC_PADDING_COUNT)
5713
5714#define _MIPIA_HBP_COUNT (VLV_DISPLAY_BASE + 0xb02c)
5715#define _MIPIB_HBP_COUNT (VLV_DISPLAY_BASE + 0xb82c)
5716#define MIPI_HBP_COUNT(pipe) _PIPE(pipe, _MIPIA_HBP_COUNT, _MIPIB_HBP_COUNT)
5717
5718#define _MIPIA_HFP_COUNT (VLV_DISPLAY_BASE + 0xb030)
5719#define _MIPIB_HFP_COUNT (VLV_DISPLAY_BASE + 0xb830)
5720#define MIPI_HFP_COUNT(pipe) _PIPE(pipe, _MIPIA_HFP_COUNT, _MIPIB_HFP_COUNT)
5721
5722#define _MIPIA_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb034)
5723#define _MIPIB_HACTIVE_AREA_COUNT (VLV_DISPLAY_BASE + 0xb834)
5724#define MIPI_HACTIVE_AREA_COUNT(pipe) _PIPE(pipe, _MIPIA_HACTIVE_AREA_COUNT, _MIPIB_HACTIVE_AREA_COUNT)
5725
5726#define _MIPIA_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb038)
5727#define _MIPIB_VSYNC_PADDING_COUNT (VLV_DISPLAY_BASE + 0xb838)
5728#define MIPI_VSYNC_PADDING_COUNT(pipe) _PIPE(pipe, _MIPIA_VSYNC_PADDING_COUNT, _MIPIB_VSYNC_PADDING_COUNT)
5729
5730#define _MIPIA_VBP_COUNT (VLV_DISPLAY_BASE + 0xb03c)
5731#define _MIPIB_VBP_COUNT (VLV_DISPLAY_BASE + 0xb83c)
5732#define MIPI_VBP_COUNT(pipe) _PIPE(pipe, _MIPIA_VBP_COUNT, _MIPIB_VBP_COUNT)
5733
5734#define _MIPIA_VFP_COUNT (VLV_DISPLAY_BASE + 0xb040)
5735#define _MIPIB_VFP_COUNT (VLV_DISPLAY_BASE + 0xb840)
5736#define MIPI_VFP_COUNT(pipe) _PIPE(pipe, _MIPIA_VFP_COUNT, _MIPIB_VFP_COUNT)
5737
5738#define _MIPIA_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb044)
5739#define _MIPIB_HIGH_LOW_SWITCH_COUNT (VLV_DISPLAY_BASE + 0xb844)
5740#define MIPI_HIGH_LOW_SWITCH_COUNT(pipe) _PIPE(pipe, _MIPIA_HIGH_LOW_SWITCH_COUNT, _MIPIB_HIGH_LOW_SWITCH_COUNT)
5741/* regs above are bits 15:0 */
5742
5743#define _MIPIA_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb048)
5744#define _MIPIB_DPI_CONTROL (VLV_DISPLAY_BASE + 0xb848)
5745#define MIPI_DPI_CONTROL(pipe) _PIPE(pipe, _MIPIA_DPI_CONTROL, _MIPIB_DPI_CONTROL)
5746#define DPI_LP_MODE (1 << 6)
5747#define BACKLIGHT_OFF (1 << 5)
5748#define BACKLIGHT_ON (1 << 4)
5749#define COLOR_MODE_OFF (1 << 3)
5750#define COLOR_MODE_ON (1 << 2)
5751#define TURN_ON (1 << 1)
5752#define SHUTDOWN (1 << 0)
5753
5754#define _MIPIA_DPI_DATA (VLV_DISPLAY_BASE + 0xb04c)
5755#define _MIPIB_DPI_DATA (VLV_DISPLAY_BASE + 0xb84c)
5756#define MIPI_DPI_DATA(pipe) _PIPE(pipe, _MIPIA_DPI_DATA, _MIPIB_DPI_DATA)
5757#define COMMAND_BYTE_SHIFT 0
5758#define COMMAND_BYTE_MASK (0x3f << 0)
5759
5760#define _MIPIA_INIT_COUNT (VLV_DISPLAY_BASE + 0xb050)
5761#define _MIPIB_INIT_COUNT (VLV_DISPLAY_BASE + 0xb850)
5762#define MIPI_INIT_COUNT(pipe) _PIPE(pipe, _MIPIA_INIT_COUNT, _MIPIB_INIT_COUNT)
5763#define MASTER_INIT_TIMER_SHIFT 0
5764#define MASTER_INIT_TIMER_MASK (0xffff << 0)
5765
5766#define _MIPIA_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb054)
5767#define _MIPIB_MAX_RETURN_PKT_SIZE (VLV_DISPLAY_BASE + 0xb854)
5768#define MIPI_MAX_RETURN_PKT_SIZE(pipe) _PIPE(pipe, _MIPIA_MAX_RETURN_PKT_SIZE, _MIPIB_MAX_RETURN_PKT_SIZE)
5769#define MAX_RETURN_PKT_SIZE_SHIFT 0
5770#define MAX_RETURN_PKT_SIZE_MASK (0x3ff << 0)
5771
5772#define _MIPIA_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb058)
5773#define _MIPIB_VIDEO_MODE_FORMAT (VLV_DISPLAY_BASE + 0xb858)
5774#define MIPI_VIDEO_MODE_FORMAT(pipe) _PIPE(pipe, _MIPIA_VIDEO_MODE_FORMAT, _MIPIB_VIDEO_MODE_FORMAT)
5775#define RANDOM_DPI_DISPLAY_RESOLUTION (1 << 4)
5776#define DISABLE_VIDEO_BTA (1 << 3)
5777#define IP_TG_CONFIG (1 << 2)
5778#define VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE (1 << 0)
5779#define VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS (2 << 0)
5780#define VIDEO_MODE_BURST (3 << 0)
5781
5782#define _MIPIA_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb05c)
5783#define _MIPIB_EOT_DISABLE (VLV_DISPLAY_BASE + 0xb85c)
5784#define MIPI_EOT_DISABLE(pipe) _PIPE(pipe, _MIPIA_EOT_DISABLE, _MIPIB_EOT_DISABLE)
5785#define LP_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 7)
5786#define HS_RX_TIMEOUT_ERROR_RECOVERY_DISABLE (1 << 6)
5787#define LOW_CONTENTION_RECOVERY_DISABLE (1 << 5)
5788#define HIGH_CONTENTION_RECOVERY_DISABLE (1 << 4)
5789#define TXDSI_TYPE_NOT_RECOGNISED_ERROR_RECOVERY_DISABLE (1 << 3)
5790#define TXECC_MULTIBIT_ERROR_RECOVERY_DISABLE (1 << 2)
5791#define CLOCKSTOP (1 << 1)
5792#define EOT_DISABLE (1 << 0)
5793
5794#define _MIPIA_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb060)
5795#define _MIPIB_LP_BYTECLK (VLV_DISPLAY_BASE + 0xb860)
5796#define MIPI_LP_BYTECLK(pipe) _PIPE(pipe, _MIPIA_LP_BYTECLK, _MIPIB_LP_BYTECLK)
5797#define LP_BYTECLK_SHIFT 0
5798#define LP_BYTECLK_MASK (0xffff << 0)
5799
5800/* bits 31:0 */
5801#define _MIPIA_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb064)
5802#define _MIPIB_LP_GEN_DATA (VLV_DISPLAY_BASE + 0xb864)
5803#define MIPI_LP_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_LP_GEN_DATA, _MIPIB_LP_GEN_DATA)
5804
5805/* bits 31:0 */
5806#define _MIPIA_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb068)
5807#define _MIPIB_HS_GEN_DATA (VLV_DISPLAY_BASE + 0xb868)
5808#define MIPI_HS_GEN_DATA(pipe) _PIPE(pipe, _MIPIA_HS_GEN_DATA, _MIPIB_HS_GEN_DATA)
5809
5810#define _MIPIA_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb06c)
5811#define _MIPIB_LP_GEN_CTRL (VLV_DISPLAY_BASE + 0xb86c)
5812#define MIPI_LP_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_LP_GEN_CTRL, _MIPIB_LP_GEN_CTRL)
5813#define _MIPIA_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb070)
5814#define _MIPIB_HS_GEN_CTRL (VLV_DISPLAY_BASE + 0xb870)
5815#define MIPI_HS_GEN_CTRL(pipe) _PIPE(pipe, _MIPIA_HS_GEN_CTRL, _MIPIB_HS_GEN_CTRL)
5816#define LONG_PACKET_WORD_COUNT_SHIFT 8
5817#define LONG_PACKET_WORD_COUNT_MASK (0xffff << 8)
5818#define SHORT_PACKET_PARAM_SHIFT 8
5819#define SHORT_PACKET_PARAM_MASK (0xffff << 8)
5820#define VIRTUAL_CHANNEL_SHIFT 6
5821#define VIRTUAL_CHANNEL_MASK (3 << 6)
5822#define DATA_TYPE_SHIFT 0
5823#define DATA_TYPE_MASK (3f << 0)
5824/* data type values, see include/video/mipi_display.h */
5825
5826#define _MIPIA_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb074)
5827#define _MIPIB_GEN_FIFO_STAT (VLV_DISPLAY_BASE + 0xb874)
5828#define MIPI_GEN_FIFO_STAT(pipe) _PIPE(pipe, _MIPIA_GEN_FIFO_STAT, _MIPIB_GEN_FIFO_STAT)
5829#define DPI_FIFO_EMPTY (1 << 28)
5830#define DBI_FIFO_EMPTY (1 << 27)
5831#define LP_CTRL_FIFO_EMPTY (1 << 26)
5832#define LP_CTRL_FIFO_HALF_EMPTY (1 << 25)
5833#define LP_CTRL_FIFO_FULL (1 << 24)
5834#define HS_CTRL_FIFO_EMPTY (1 << 18)
5835#define HS_CTRL_FIFO_HALF_EMPTY (1 << 17)
5836#define HS_CTRL_FIFO_FULL (1 << 16)
5837#define LP_DATA_FIFO_EMPTY (1 << 10)
5838#define LP_DATA_FIFO_HALF_EMPTY (1 << 9)
5839#define LP_DATA_FIFO_FULL (1 << 8)
5840#define HS_DATA_FIFO_EMPTY (1 << 2)
5841#define HS_DATA_FIFO_HALF_EMPTY (1 << 1)
5842#define HS_DATA_FIFO_FULL (1 << 0)
5843
5844#define _MIPIA_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb078)
5845#define _MIPIB_HS_LS_DBI_ENABLE (VLV_DISPLAY_BASE + 0xb878)
5846#define MIPI_HS_LP_DBI_ENABLE(pipe) _PIPE(pipe, _MIPIA_HS_LS_DBI_ENABLE, _MIPIB_HS_LS_DBI_ENABLE)
5847#define DBI_HS_LP_MODE_MASK (1 << 0)
5848#define DBI_LP_MODE (1 << 0)
5849#define DBI_HS_MODE (0 << 0)
5850
5851#define _MIPIA_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb080)
5852#define _MIPIB_DPHY_PARAM (VLV_DISPLAY_BASE + 0xb880)
5853#define MIPI_DPHY_PARAM(pipe) _PIPE(pipe, _MIPIA_DPHY_PARAM, _MIPIB_DPHY_PARAM)
5854#define EXIT_ZERO_COUNT_SHIFT 24
5855#define EXIT_ZERO_COUNT_MASK (0x3f << 24)
5856#define TRAIL_COUNT_SHIFT 16
5857#define TRAIL_COUNT_MASK (0x1f << 16)
5858#define CLK_ZERO_COUNT_SHIFT 8
5859#define CLK_ZERO_COUNT_MASK (0xff << 8)
5860#define PREPARE_COUNT_SHIFT 0
5861#define PREPARE_COUNT_MASK (0x3f << 0)
5862
5863/* bits 31:0 */
5864#define _MIPIA_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb084)
5865#define _MIPIB_DBI_BW_CTRL (VLV_DISPLAY_BASE + 0xb884)
5866#define MIPI_DBI_BW_CTRL(pipe) _PIPE(pipe, _MIPIA_DBI_BW_CTRL, _MIPIB_DBI_BW_CTRL)
5867
5868#define _MIPIA_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb088)
5869#define _MIPIB_CLK_LANE_SWITCH_TIME_CNT (VLV_DISPLAY_BASE + 0xb888)
5870#define MIPI_CLK_LANE_SWITCH_TIME_CNT(pipe) _PIPE(pipe, _MIPIA_CLK_LANE_SWITCH_TIME_CNT, _MIPIB_CLK_LANE_SWITCH_TIME_CNT)
5871#define LP_HS_SSW_CNT_SHIFT 16
5872#define LP_HS_SSW_CNT_MASK (0xffff << 16)
5873#define HS_LP_PWR_SW_CNT_SHIFT 0
5874#define HS_LP_PWR_SW_CNT_MASK (0xffff << 0)
5875
5876#define _MIPIA_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb08c)
5877#define _MIPIB_STOP_STATE_STALL (VLV_DISPLAY_BASE + 0xb88c)
5878#define MIPI_STOP_STATE_STALL(pipe) _PIPE(pipe, _MIPIA_STOP_STATE_STALL, _MIPIB_STOP_STATE_STALL)
5879#define STOP_STATE_STALL_COUNTER_SHIFT 0
5880#define STOP_STATE_STALL_COUNTER_MASK (0xff << 0)
5881
5882#define _MIPIA_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb090)
5883#define _MIPIB_INTR_STAT_REG_1 (VLV_DISPLAY_BASE + 0xb890)
5884#define MIPI_INTR_STAT_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_STAT_REG_1, _MIPIB_INTR_STAT_REG_1)
5885#define _MIPIA_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb094)
5886#define _MIPIB_INTR_EN_REG_1 (VLV_DISPLAY_BASE + 0xb894)
5887#define MIPI_INTR_EN_REG_1(pipe) _PIPE(pipe, _MIPIA_INTR_EN_REG_1, _MIPIB_INTR_EN_REG_1)
5888#define RX_CONTENTION_DETECTED (1 << 0)
5889
5890/* XXX: only pipe A ?!? */
5891#define MIPIA_DBI_TYPEC_CTRL (VLV_DISPLAY_BASE + 0xb100)
5892#define DBI_TYPEC_ENABLE (1 << 31)
5893#define DBI_TYPEC_WIP (1 << 30)
5894#define DBI_TYPEC_OPTION_SHIFT 28
5895#define DBI_TYPEC_OPTION_MASK (3 << 28)
5896#define DBI_TYPEC_FREQ_SHIFT 24
5897#define DBI_TYPEC_FREQ_MASK (0xf << 24)
5898#define DBI_TYPEC_OVERRIDE (1 << 8)
5899#define DBI_TYPEC_OVERRIDE_COUNTER_SHIFT 0
5900#define DBI_TYPEC_OVERRIDE_COUNTER_MASK (0xff << 0)
5901
5902
5903/* MIPI adapter registers */
5904
5905#define _MIPIA_CTRL (VLV_DISPLAY_BASE + 0xb104)
5906#define _MIPIB_CTRL (VLV_DISPLAY_BASE + 0xb904)
5907#define MIPI_CTRL(pipe) _PIPE(pipe, _MIPIA_CTRL, _MIPIB_CTRL)
5908#define ESCAPE_CLOCK_DIVIDER_SHIFT 5 /* A only */
5909#define ESCAPE_CLOCK_DIVIDER_MASK (3 << 5)
5910#define ESCAPE_CLOCK_DIVIDER_1 (0 << 5)
5911#define ESCAPE_CLOCK_DIVIDER_2 (1 << 5)
5912#define ESCAPE_CLOCK_DIVIDER_4 (2 << 5)
5913#define READ_REQUEST_PRIORITY_SHIFT 3
5914#define READ_REQUEST_PRIORITY_MASK (3 << 3)
5915#define READ_REQUEST_PRIORITY_LOW (0 << 3)
5916#define READ_REQUEST_PRIORITY_HIGH (3 << 3)
5917#define RGB_FLIP_TO_BGR (1 << 2)
5918
5919#define _MIPIA_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb108)
5920#define _MIPIB_DATA_ADDRESS (VLV_DISPLAY_BASE + 0xb908)
5921#define MIPI_DATA_ADDRESS(pipe) _PIPE(pipe, _MIPIA_DATA_ADDRESS, _MIPIB_DATA_ADDRESS)
5922#define DATA_MEM_ADDRESS_SHIFT 5
5923#define DATA_MEM_ADDRESS_MASK (0x7ffffff << 5)
5924#define DATA_VALID (1 << 0)
5925
5926#define _MIPIA_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb10c)
5927#define _MIPIB_DATA_LENGTH (VLV_DISPLAY_BASE + 0xb90c)
5928#define MIPI_DATA_LENGTH(pipe) _PIPE(pipe, _MIPIA_DATA_LENGTH, _MIPIB_DATA_LENGTH)
5929#define DATA_LENGTH_SHIFT 0
5930#define DATA_LENGTH_MASK (0xfffff << 0)
5931
5932#define _MIPIA_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb110)
5933#define _MIPIB_COMMAND_ADDRESS (VLV_DISPLAY_BASE + 0xb910)
5934#define MIPI_COMMAND_ADDRESS(pipe) _PIPE(pipe, _MIPIA_COMMAND_ADDRESS, _MIPIB_COMMAND_ADDRESS)
5935#define COMMAND_MEM_ADDRESS_SHIFT 5
5936#define COMMAND_MEM_ADDRESS_MASK (0x7ffffff << 5)
5937#define AUTO_PWG_ENABLE (1 << 2)
5938#define MEMORY_WRITE_DATA_FROM_PIPE_RENDERING (1 << 1)
5939#define COMMAND_VALID (1 << 0)
5940
5941#define _MIPIA_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb114)
5942#define _MIPIB_COMMAND_LENGTH (VLV_DISPLAY_BASE + 0xb914)
5943#define MIPI_COMMAND_LENGTH(pipe) _PIPE(pipe, _MIPIA_COMMAND_LENGTH, _MIPIB_COMMAND_LENGTH)
5944#define COMMAND_LENGTH_SHIFT(n) (8 * (n)) /* n: 0...3 */
5945#define COMMAND_LENGTH_MASK(n) (0xff << (8 * (n)))
5946
5947#define _MIPIA_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb118)
5948#define _MIPIB_READ_DATA_RETURN0 (VLV_DISPLAY_BASE + 0xb918)
5949#define MIPI_READ_DATA_RETURN(pipe, n) \
5950 (_PIPE(pipe, _MIPIA_READ_DATA_RETURN0, _MIPIB_READ_DATA_RETURN0) + 4 * (n)) /* n: 0...7 */
5951
5952#define _MIPIA_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb138)
5953#define _MIPIB_READ_DATA_VALID (VLV_DISPLAY_BASE + 0xb938)
5954#define MIPI_READ_DATA_VALID(pipe) _PIPE(pipe, _MIPIA_READ_DATA_VALID, _MIPIB_READ_DATA_VALID)
5955#define READ_DATA_VALID(n) (1 << (n))
5956
5957/* For UMS only (deprecated): */
5958#define _PALETTE_A (dev_priv->info.display_mmio_offset + 0xa000)
5959#define _PALETTE_B (dev_priv->info.display_mmio_offset + 0xa800)
5960#define _DPLL_A (dev_priv->info.display_mmio_offset + 0x6014)
5961#define _DPLL_B (dev_priv->info.display_mmio_offset + 0x6018)
5962#define _DPLL_A_MD (dev_priv->info.display_mmio_offset + 0x601c)
5963#define _DPLL_B_MD (dev_priv->info.display_mmio_offset + 0x6020)
5964
5965#endif /* _I915_REG_H_ */