1/*
  2 * GPIOs on MPC512x/8349/8572/8610 and compatible
  3 *
  4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk>
  5 *
  6 * This file is licensed under the terms of the GNU General Public License
  7 * version 2.  This program is licensed "as is" without any warranty of any
  8 * kind, whether express or implied.
  9 */
 10
 11#include <linux/kernel.h>
 12#include <linux/init.h>
 13#include <linux/spinlock.h>
 14#include <linux/io.h>
 15#include <linux/of.h>
 16#include <linux/of_gpio.h>
 17#include <linux/of_irq.h>
 18#include <linux/gpio.h>
 19#include <linux/slab.h>
 20#include <linux/irq.h>
 21
 22#define MPC8XXX_GPIO_PINS	32
 23
 24#define GPIO_DIR		0x00
 25#define GPIO_ODR		0x04
 26#define GPIO_DAT		0x08
 27#define GPIO_IER		0x0c
 28#define GPIO_IMR		0x10
 29#define GPIO_ICR		0x14
 30#define GPIO_ICR2		0x18
 31
 32struct mpc8xxx_gpio_chip {
 33	struct of_mm_gpio_chip mm_gc;
 34	spinlock_t lock;
 35
 36	/*
 37	 * shadowed data register to be able to clear/set output pins in
 38	 * open drain mode safely
 39	 */
 40	u32 data;
 41	struct irq_domain *irq;
 42	const void *of_dev_id_data;
 43};
 44
 45static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
 46{
 47	return 1u << (MPC8XXX_GPIO_PINS - 1 - gpio);
 48}
 49
 50static inline struct mpc8xxx_gpio_chip *
 51to_mpc8xxx_gpio_chip(struct of_mm_gpio_chip *mm)
 52{
 53	return container_of(mm, struct mpc8xxx_gpio_chip, mm_gc);
 54}
 55
 56static void mpc8xxx_gpio_save_regs(struct of_mm_gpio_chip *mm)
 57{
 58	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 59
 60	mpc8xxx_gc->data = in_be32(mm->regs + GPIO_DAT);
 61}
 62
 63/* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs
 64 * defined as output cannot be determined by reading GPDAT register,
 65 * so we use shadow data register instead. The status of input pins
 66 * is determined by reading GPDAT register.
 67 */
 68static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 69{
 70	u32 val;
 71	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 72	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 73	u32 out_mask, out_shadow;
 74
 75	out_mask = in_be32(mm->regs + GPIO_DIR);
 76
 77	val = in_be32(mm->regs + GPIO_DAT) & ~out_mask;
 78	out_shadow = mpc8xxx_gc->data & out_mask;
 79
 80	return (val | out_shadow) & mpc8xxx_gpio2mask(gpio);
 81}
 82
 83static int mpc8xxx_gpio_get(struct gpio_chip *gc, unsigned int gpio)
 84{
 85	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 86
 87	return in_be32(mm->regs + GPIO_DAT) & mpc8xxx_gpio2mask(gpio);
 88}
 89
 90static void mpc8xxx_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
 91{
 92	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
 93	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
 94	unsigned long flags;
 95
 96	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
 97
 98	if (val)
 99		mpc8xxx_gc->data |= mpc8xxx_gpio2mask(gpio);
100	else
101		mpc8xxx_gc->data &= ~mpc8xxx_gpio2mask(gpio);
102
103	out_be32(mm->regs + GPIO_DAT, mpc8xxx_gc->data);
104
105	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
106}
107
108static int mpc8xxx_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
109{
110	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
111	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
112	unsigned long flags;
113
114	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
115
116	clrbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
117
118	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
119
120	return 0;
121}
122
123static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
124{
125	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
126	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
127	unsigned long flags;
128
129	mpc8xxx_gpio_set(gc, gpio, val);
130
131	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
132
133	setbits32(mm->regs + GPIO_DIR, mpc8xxx_gpio2mask(gpio));
134
135	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
136
137	return 0;
138}
139
140static int mpc5121_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
141{
142	/* GPIO 28..31 are input only on MPC5121 */
143	if (gpio >= 28)
144		return -EINVAL;
145
146	return mpc8xxx_gpio_dir_out(gc, gpio, val);
147}
148
149static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
150{
151	struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
152	struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
153
154	if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
155		return irq_create_mapping(mpc8xxx_gc->irq, offset);
156	else
157		return -ENXIO;
158}
159
160static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
161{
162	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc);
163	struct irq_chip *chip = irq_desc_get_chip(desc);
164	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
165	unsigned int mask;
166
167	mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
168	if (mask)
169		generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
170						     32 - ffs(mask)));
171	if (chip->irq_eoi)
172		chip->irq_eoi(&desc->irq_data);
173}
174
175static void mpc8xxx_irq_unmask(struct irq_data *d)
176{
177	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
178	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
179	unsigned long flags;
180
181	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
182
183	setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
184
185	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
186}
187
188static void mpc8xxx_irq_mask(struct irq_data *d)
189{
190	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
191	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
192	unsigned long flags;
193
194	spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
195
196	clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
197
198	spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
199}
200
201static void mpc8xxx_irq_ack(struct irq_data *d)
202{
203	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
204	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
205
206	out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
207}
208
209static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type)
210{
211	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
212	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
213	unsigned long flags;
214
215	switch (flow_type) {
216	case IRQ_TYPE_EDGE_FALLING:
217		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
218		setbits32(mm->regs + GPIO_ICR,
219			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
220		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
221		break;
222
223	case IRQ_TYPE_EDGE_BOTH:
224		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
225		clrbits32(mm->regs + GPIO_ICR,
226			  mpc8xxx_gpio2mask(irqd_to_hwirq(d)));
227		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
228		break;
229
230	default:
231		return -EINVAL;
232	}
233
234	return 0;
235}
236
237static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type)
238{
239	struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d);
240	struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
241	unsigned long gpio = irqd_to_hwirq(d);
242	void __iomem *reg;
243	unsigned int shift;
244	unsigned long flags;
245
246	if (gpio < 16) {
247		reg = mm->regs + GPIO_ICR;
248		shift = (15 - gpio) * 2;
249	} else {
250		reg = mm->regs + GPIO_ICR2;
251		shift = (15 - (gpio % 16)) * 2;
252	}
253
254	switch (flow_type) {
255	case IRQ_TYPE_EDGE_FALLING:
256	case IRQ_TYPE_LEVEL_LOW:
257		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
258		clrsetbits_be32(reg, 3 << shift, 2 << shift);
259		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
260		break;
261
262	case IRQ_TYPE_EDGE_RISING:
263	case IRQ_TYPE_LEVEL_HIGH:
264		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
265		clrsetbits_be32(reg, 3 << shift, 1 << shift);
266		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
267		break;
268
269	case IRQ_TYPE_EDGE_BOTH:
270		spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
271		clrbits32(reg, 3 << shift);
272		spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
273		break;
274
275	default:
276		return -EINVAL;
277	}
278
279	return 0;
280}
281
282static struct irq_chip mpc8xxx_irq_chip = {
283	.name		= "mpc8xxx-gpio",
284	.irq_unmask	= mpc8xxx_irq_unmask,
285	.irq_mask	= mpc8xxx_irq_mask,
286	.irq_ack	= mpc8xxx_irq_ack,
287	.irq_set_type	= mpc8xxx_irq_set_type,
288};
289
290static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
291				irq_hw_number_t hwirq)
292{
293	struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;
294
295	if (mpc8xxx_gc->of_dev_id_data)
296		mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;
297
298	irq_set_chip_data(irq, h->host_data);
299	irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);
300
301	return 0;
302}
303
304static struct irq_domain_ops mpc8xxx_gpio_irq_ops = {
305	.map	= mpc8xxx_gpio_irq_map,
306	.xlate	= irq_domain_xlate_twocell,
307};
308
309static struct of_device_id mpc8xxx_gpio_ids[] __initdata = {
310	{ .compatible = "fsl,mpc8349-gpio", },
311	{ .compatible = "fsl,mpc8572-gpio", },
312	{ .compatible = "fsl,mpc8610-gpio", },
313	{ .compatible = "fsl,mpc5121-gpio", .data = mpc512x_irq_set_type, },
314	{ .compatible = "fsl,pq3-gpio",     },
315	{ .compatible = "fsl,qoriq-gpio",   },
316	{}
317};
318
319static void __init mpc8xxx_add_controller(struct device_node *np)
320{
321	struct mpc8xxx_gpio_chip *mpc8xxx_gc;
322	struct of_mm_gpio_chip *mm_gc;
323	struct gpio_chip *gc;
324	const struct of_device_id *id;
325	unsigned hwirq;
326	int ret;
327
328	mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
329	if (!mpc8xxx_gc) {
330		ret = -ENOMEM;
331		goto err;
332	}
333
334	spin_lock_init(&mpc8xxx_gc->lock);
335
336	mm_gc = &mpc8xxx_gc->mm_gc;
337	gc = &mm_gc->gc;
338
339	mm_gc->save_regs = mpc8xxx_gpio_save_regs;
340	gc->ngpio = MPC8XXX_GPIO_PINS;
341	gc->direction_input = mpc8xxx_gpio_dir_in;
342	gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
343		mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
344	gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
345		mpc8572_gpio_get : mpc8xxx_gpio_get;
346	gc->set = mpc8xxx_gpio_set;
347	gc->to_irq = mpc8xxx_gpio_to_irq;
348
349	ret = of_mm_gpiochip_add(np, mm_gc);
350	if (ret)
351		goto err;
352
353	hwirq = irq_of_parse_and_map(np, 0);
354	if (hwirq == NO_IRQ)
355		goto skip_irq;
356
357	mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
358					&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
359	if (!mpc8xxx_gc->irq)
360		goto skip_irq;
361
362	id = of_match_node(mpc8xxx_gpio_ids, np);
363	if (id)
364		mpc8xxx_gc->of_dev_id_data = id->data;
365
366	/* ack and mask all irqs */
367	out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
368	out_be32(mm_gc->regs + GPIO_IMR, 0);
369
370	irq_set_handler_data(hwirq, mpc8xxx_gc);
371	irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
372
373skip_irq:
374	return;
375
376err:
377	pr_err("%s: registration failed with status %d\n",
378	       np->full_name, ret);
379	kfree(mpc8xxx_gc);
380
381	return;
382}
383
384static int __init mpc8xxx_add_gpiochips(void)
385{
386	struct device_node *np;
387
388	for_each_matching_node(np, mpc8xxx_gpio_ids)
389		mpc8xxx_add_controller(np);
390
391	return 0;
392}
393arch_initcall(mpc8xxx_add_gpiochips);