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1/*
2 * common clks module for all SiRF SoCs
3 *
4 * Copyright (c) 2011 - 2014 Cambridge Silicon Radio Limited, a CSR plc group
5 * company.
6 *
7 * Licensed under GPLv2 or later.
8 */
9
10#define KHZ 1000
11#define MHZ (KHZ * KHZ)
12
13static void *sirfsoc_clk_vbase;
14static void *sirfsoc_rsc_vbase;
15static struct clk_onecell_data clk_data;
16
17/*
18 * SiRFprimaII clock controller
19 * - 2 oscillators: osc-26MHz, rtc-32.768KHz
20 * - 3 standard configurable plls: pll1, pll2 & pll3
21 * - 2 exclusive plls: usb phy pll and sata phy pll
22 * - 8 clock domains: cpu/cpudiv, mem/memdiv, sys/io, dsp, graphic, multimedia,
23 * display and sdphy.
24 * Each clock domain can select its own clock source from five clock sources,
25 * X_XIN, X_XINW, PLL1, PLL2 and PLL3. The domain clock is used as the source
26 * clock of the group clock.
27 * - dsp domain: gps, mf
28 * - io domain: dmac, nand, audio, uart, i2c, spi, usp, pwm, pulse
29 * - sys domain: security
30 */
31
32struct clk_pll {
33 struct clk_hw hw;
34 unsigned short regofs; /* register offset */
35};
36
37#define to_pllclk(_hw) container_of(_hw, struct clk_pll, hw)
38
39struct clk_dmn {
40 struct clk_hw hw;
41 signed char enable_bit; /* enable bit: 0 ~ 63 */
42 unsigned short regofs; /* register offset */
43};
44
45#define to_dmnclk(_hw) container_of(_hw, struct clk_dmn, hw)
46
47struct clk_std {
48 struct clk_hw hw;
49 signed char enable_bit; /* enable bit: 0 ~ 63 */
50};
51
52#define to_stdclk(_hw) container_of(_hw, struct clk_std, hw)
53
54static int std_clk_is_enabled(struct clk_hw *hw);
55static int std_clk_enable(struct clk_hw *hw);
56static void std_clk_disable(struct clk_hw *hw);
57
58static inline unsigned long clkc_readl(unsigned reg)
59{
60 return readl(sirfsoc_clk_vbase + reg);
61}
62
63static inline void clkc_writel(u32 val, unsigned reg)
64{
65 writel(val, sirfsoc_clk_vbase + reg);
66}
67
68/*
69 * std pll
70 */
71
72static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
73 unsigned long parent_rate)
74{
75 unsigned long fin = parent_rate;
76 struct clk_pll *clk = to_pllclk(hw);
77 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 -
78 SIRFSOC_CLKC_PLL1_CFG0;
79
80 if (clkc_readl(regcfg2) & BIT(2)) {
81 /* pll bypass mode */
82 return fin;
83 } else {
84 /* fout = fin * nf / nr / od */
85 u32 cfg0 = clkc_readl(clk->regofs);
86 u32 nf = (cfg0 & (BIT(13) - 1)) + 1;
87 u32 nr = ((cfg0 >> 13) & (BIT(6) - 1)) + 1;
88 u32 od = ((cfg0 >> 19) & (BIT(4) - 1)) + 1;
89 WARN_ON(fin % MHZ);
90 return fin / MHZ * nf / nr / od * MHZ;
91 }
92}
93
94static long pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
95 unsigned long *parent_rate)
96{
97 unsigned long fin, nf, nr, od;
98 u64 dividend;
99
100 /*
101 * fout = fin * nf / (nr * od);
102 * set od = 1, nr = fin/MHz, so fout = nf * MHz
103 */
104 rate = rate - rate % MHZ;
105
106 nf = rate / MHZ;
107 if (nf > BIT(13))
108 nf = BIT(13);
109 if (nf < 1)
110 nf = 1;
111
112 fin = *parent_rate;
113
114 nr = fin / MHZ;
115 if (nr > BIT(6))
116 nr = BIT(6);
117 od = 1;
118
119 dividend = (u64)fin * nf;
120 do_div(dividend, nr * od);
121
122 return (long)dividend;
123}
124
125static int pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
126 unsigned long parent_rate)
127{
128 struct clk_pll *clk = to_pllclk(hw);
129 unsigned long fin, nf, nr, od, reg;
130
131 /*
132 * fout = fin * nf / (nr * od);
133 * set od = 1, nr = fin/MHz, so fout = nf * MHz
134 */
135
136 nf = rate / MHZ;
137 if (unlikely((rate % MHZ) || nf > BIT(13) || nf < 1))
138 return -EINVAL;
139
140 fin = parent_rate;
141 BUG_ON(fin < MHZ);
142
143 nr = fin / MHZ;
144 BUG_ON((fin % MHZ) || nr > BIT(6));
145
146 od = 1;
147
148 reg = (nf - 1) | ((nr - 1) << 13) | ((od - 1) << 19);
149 clkc_writel(reg, clk->regofs);
150
151 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0;
152 clkc_writel((nf >> 1) - 1, reg);
153
154 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0;
155 while (!(clkc_readl(reg) & BIT(6)))
156 cpu_relax();
157
158 return 0;
159}
160
161static long cpu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
162 unsigned long *parent_rate)
163{
164 /*
165 * SiRF SoC has not cpu clock control,
166 * So bypass to it's parent pll.
167 */
168 struct clk *parent_clk = clk_get_parent(hw->clk);
169 struct clk *pll_parent_clk = clk_get_parent(parent_clk);
170 unsigned long pll_parent_rate = clk_get_rate(pll_parent_clk);
171 return pll_clk_round_rate(__clk_get_hw(parent_clk), rate, &pll_parent_rate);
172}
173
174static unsigned long cpu_clk_recalc_rate(struct clk_hw *hw,
175 unsigned long parent_rate)
176{
177 /*
178 * SiRF SoC has not cpu clock control,
179 * So return the parent pll rate.
180 */
181 struct clk *parent_clk = clk_get_parent(hw->clk);
182 return __clk_get_rate(parent_clk);
183}
184
185static struct clk_ops std_pll_ops = {
186 .recalc_rate = pll_clk_recalc_rate,
187 .round_rate = pll_clk_round_rate,
188 .set_rate = pll_clk_set_rate,
189};
190
191static const char *pll_clk_parents[] = {
192 "osc",
193};
194
195static struct clk_init_data clk_pll1_init = {
196 .name = "pll1",
197 .ops = &std_pll_ops,
198 .parent_names = pll_clk_parents,
199 .num_parents = ARRAY_SIZE(pll_clk_parents),
200};
201
202static struct clk_init_data clk_pll2_init = {
203 .name = "pll2",
204 .ops = &std_pll_ops,
205 .parent_names = pll_clk_parents,
206 .num_parents = ARRAY_SIZE(pll_clk_parents),
207};
208
209static struct clk_init_data clk_pll3_init = {
210 .name = "pll3",
211 .ops = &std_pll_ops,
212 .parent_names = pll_clk_parents,
213 .num_parents = ARRAY_SIZE(pll_clk_parents),
214};
215
216static struct clk_pll clk_pll1 = {
217 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
218 .hw = {
219 .init = &clk_pll1_init,
220 },
221};
222
223static struct clk_pll clk_pll2 = {
224 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
225 .hw = {
226 .init = &clk_pll2_init,
227 },
228};
229
230static struct clk_pll clk_pll3 = {
231 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
232 .hw = {
233 .init = &clk_pll3_init,
234 },
235};
236
237/*
238 * usb uses specified pll
239 */
240
241static int usb_pll_clk_enable(struct clk_hw *hw)
242{
243 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
244 reg &= ~(SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
245 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
246 while (!(readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL) &
247 SIRFSOC_USBPHY_PLL_LOCK))
248 cpu_relax();
249
250 return 0;
251}
252
253static void usb_pll_clk_disable(struct clk_hw *clk)
254{
255 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
256 reg |= (SIRFSOC_USBPHY_PLL_POWERDOWN | SIRFSOC_USBPHY_PLL_BYPASS);
257 writel(reg, sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
258}
259
260static unsigned long usb_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
261{
262 u32 reg = readl(sirfsoc_rsc_vbase + SIRFSOC_USBPHY_PLL_CTRL);
263 return (reg & SIRFSOC_USBPHY_PLL_BYPASS) ? parent_rate : 48*MHZ;
264}
265
266static struct clk_ops usb_pll_ops = {
267 .enable = usb_pll_clk_enable,
268 .disable = usb_pll_clk_disable,
269 .recalc_rate = usb_pll_clk_recalc_rate,
270};
271
272static struct clk_init_data clk_usb_pll_init = {
273 .name = "usb_pll",
274 .ops = &usb_pll_ops,
275 .parent_names = pll_clk_parents,
276 .num_parents = ARRAY_SIZE(pll_clk_parents),
277};
278
279static struct clk_hw usb_pll_clk_hw = {
280 .init = &clk_usb_pll_init,
281};
282
283/*
284 * clock domains - cpu, mem, sys/io, dsp, gfx
285 */
286
287static const char *dmn_clk_parents[] = {
288 "rtc",
289 "osc",
290 "pll1",
291 "pll2",
292 "pll3",
293};
294
295static u8 dmn_clk_get_parent(struct clk_hw *hw)
296{
297 struct clk_dmn *clk = to_dmnclk(hw);
298 u32 cfg = clkc_readl(clk->regofs);
299
300 /* parent of io domain can only be pll3 */
301 if (strcmp(hw->init->name, "io") == 0)
302 return 4;
303
304 WARN_ON((cfg & (BIT(3) - 1)) > 4);
305
306 return cfg & (BIT(3) - 1);
307}
308
309static int dmn_clk_set_parent(struct clk_hw *hw, u8 parent)
310{
311 struct clk_dmn *clk = to_dmnclk(hw);
312 u32 cfg = clkc_readl(clk->regofs);
313
314 /* parent of io domain can only be pll3 */
315 if (strcmp(hw->init->name, "io") == 0)
316 return -EINVAL;
317
318 cfg &= ~(BIT(3) - 1);
319 clkc_writel(cfg | parent, clk->regofs);
320 /* BIT(3) - switching status: 1 - busy, 0 - done */
321 while (clkc_readl(clk->regofs) & BIT(3))
322 cpu_relax();
323
324 return 0;
325}
326
327static unsigned long dmn_clk_recalc_rate(struct clk_hw *hw,
328 unsigned long parent_rate)
329
330{
331 unsigned long fin = parent_rate;
332 struct clk_dmn *clk = to_dmnclk(hw);
333
334 u32 cfg = clkc_readl(clk->regofs);
335
336 if (cfg & BIT(24)) {
337 /* fcd bypass mode */
338 return fin;
339 } else {
340 /*
341 * wait count: bit[19:16], hold count: bit[23:20]
342 */
343 u32 wait = (cfg >> 16) & (BIT(4) - 1);
344 u32 hold = (cfg >> 20) & (BIT(4) - 1);
345
346 return fin / (wait + hold + 2);
347 }
348}
349
350static long dmn_clk_round_rate(struct clk_hw *hw, unsigned long rate,
351 unsigned long *parent_rate)
352{
353 unsigned long fin;
354 unsigned ratio, wait, hold;
355 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
356
357 fin = *parent_rate;
358 ratio = fin / rate;
359
360 if (ratio < 2)
361 ratio = 2;
362 if (ratio > BIT(bits + 1))
363 ratio = BIT(bits + 1);
364
365 wait = (ratio >> 1) - 1;
366 hold = ratio - wait - 2;
367
368 return fin / (wait + hold + 2);
369}
370
371static int dmn_clk_set_rate(struct clk_hw *hw, unsigned long rate,
372 unsigned long parent_rate)
373{
374 struct clk_dmn *clk = to_dmnclk(hw);
375 unsigned long fin;
376 unsigned ratio, wait, hold, reg;
377 unsigned bits = (strcmp(hw->init->name, "mem") == 0) ? 3 : 4;
378
379 fin = parent_rate;
380 ratio = fin / rate;
381
382 if (unlikely(ratio < 2 || ratio > BIT(bits + 1)))
383 return -EINVAL;
384
385 WARN_ON(fin % rate);
386
387 wait = (ratio >> 1) - 1;
388 hold = ratio - wait - 2;
389
390 reg = clkc_readl(clk->regofs);
391 reg &= ~(((BIT(bits) - 1) << 16) | ((BIT(bits) - 1) << 20));
392 reg |= (wait << 16) | (hold << 20) | BIT(25);
393 clkc_writel(reg, clk->regofs);
394
395 /* waiting FCD been effective */
396 while (clkc_readl(clk->regofs) & BIT(25))
397 cpu_relax();
398
399 return 0;
400}
401
402static int cpu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
403 unsigned long parent_rate)
404{
405 int ret1, ret2;
406 struct clk *cur_parent;
407
408 if (rate == clk_get_rate(clk_pll1.hw.clk)) {
409 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
410 return ret1;
411 }
412
413 if (rate == clk_get_rate(clk_pll2.hw.clk)) {
414 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
415 return ret1;
416 }
417
418 if (rate == clk_get_rate(clk_pll3.hw.clk)) {
419 ret1 = clk_set_parent(hw->clk, clk_pll3.hw.clk);
420 return ret1;
421 }
422
423 cur_parent = clk_get_parent(hw->clk);
424
425 /* switch to tmp pll before setting parent clock's rate */
426 if (cur_parent == clk_pll1.hw.clk) {
427 ret1 = clk_set_parent(hw->clk, clk_pll2.hw.clk);
428 BUG_ON(ret1);
429 }
430
431 ret2 = clk_set_rate(clk_pll1.hw.clk, rate);
432
433 ret1 = clk_set_parent(hw->clk, clk_pll1.hw.clk);
434
435 return ret2 ? ret2 : ret1;
436}
437
438static struct clk_ops msi_ops = {
439 .set_rate = dmn_clk_set_rate,
440 .round_rate = dmn_clk_round_rate,
441 .recalc_rate = dmn_clk_recalc_rate,
442 .set_parent = dmn_clk_set_parent,
443 .get_parent = dmn_clk_get_parent,
444};
445
446static struct clk_init_data clk_mem_init = {
447 .name = "mem",
448 .ops = &msi_ops,
449 .parent_names = dmn_clk_parents,
450 .num_parents = ARRAY_SIZE(dmn_clk_parents),
451};
452
453static struct clk_dmn clk_mem = {
454 .regofs = SIRFSOC_CLKC_MEM_CFG,
455 .hw = {
456 .init = &clk_mem_init,
457 },
458};
459
460static struct clk_init_data clk_sys_init = {
461 .name = "sys",
462 .ops = &msi_ops,
463 .parent_names = dmn_clk_parents,
464 .num_parents = ARRAY_SIZE(dmn_clk_parents),
465 .flags = CLK_SET_RATE_GATE,
466};
467
468static struct clk_dmn clk_sys = {
469 .regofs = SIRFSOC_CLKC_SYS_CFG,
470 .hw = {
471 .init = &clk_sys_init,
472 },
473};
474
475static struct clk_init_data clk_io_init = {
476 .name = "io",
477 .ops = &msi_ops,
478 .parent_names = dmn_clk_parents,
479 .num_parents = ARRAY_SIZE(dmn_clk_parents),
480};
481
482static struct clk_dmn clk_io = {
483 .regofs = SIRFSOC_CLKC_IO_CFG,
484 .hw = {
485 .init = &clk_io_init,
486 },
487};
488
489static struct clk_ops cpu_ops = {
490 .set_parent = dmn_clk_set_parent,
491 .get_parent = dmn_clk_get_parent,
492 .set_rate = cpu_clk_set_rate,
493 .round_rate = cpu_clk_round_rate,
494 .recalc_rate = cpu_clk_recalc_rate,
495};
496
497static struct clk_init_data clk_cpu_init = {
498 .name = "cpu",
499 .ops = &cpu_ops,
500 .parent_names = dmn_clk_parents,
501 .num_parents = ARRAY_SIZE(dmn_clk_parents),
502 .flags = CLK_SET_RATE_PARENT,
503};
504
505static struct clk_dmn clk_cpu = {
506 .regofs = SIRFSOC_CLKC_CPU_CFG,
507 .hw = {
508 .init = &clk_cpu_init,
509 },
510};
511
512static struct clk_ops dmn_ops = {
513 .is_enabled = std_clk_is_enabled,
514 .enable = std_clk_enable,
515 .disable = std_clk_disable,
516 .set_rate = dmn_clk_set_rate,
517 .round_rate = dmn_clk_round_rate,
518 .recalc_rate = dmn_clk_recalc_rate,
519 .set_parent = dmn_clk_set_parent,
520 .get_parent = dmn_clk_get_parent,
521};
522
523/* dsp, gfx, mm, lcd and vpp domain */
524
525static struct clk_init_data clk_dsp_init = {
526 .name = "dsp",
527 .ops = &dmn_ops,
528 .parent_names = dmn_clk_parents,
529 .num_parents = ARRAY_SIZE(dmn_clk_parents),
530};
531
532static struct clk_dmn clk_dsp = {
533 .regofs = SIRFSOC_CLKC_DSP_CFG,
534 .enable_bit = 0,
535 .hw = {
536 .init = &clk_dsp_init,
537 },
538};
539
540static struct clk_init_data clk_gfx_init = {
541 .name = "gfx",
542 .ops = &dmn_ops,
543 .parent_names = dmn_clk_parents,
544 .num_parents = ARRAY_SIZE(dmn_clk_parents),
545};
546
547static struct clk_dmn clk_gfx = {
548 .regofs = SIRFSOC_CLKC_GFX_CFG,
549 .enable_bit = 8,
550 .hw = {
551 .init = &clk_gfx_init,
552 },
553};
554
555static struct clk_init_data clk_mm_init = {
556 .name = "mm",
557 .ops = &dmn_ops,
558 .parent_names = dmn_clk_parents,
559 .num_parents = ARRAY_SIZE(dmn_clk_parents),
560};
561
562static struct clk_dmn clk_mm = {
563 .regofs = SIRFSOC_CLKC_MM_CFG,
564 .enable_bit = 9,
565 .hw = {
566 .init = &clk_mm_init,
567 },
568};
569
570/*
571 * for atlas6, gfx2d holds the bit of prima2's clk_mm
572 */
573#define clk_gfx2d clk_mm
574
575static struct clk_init_data clk_lcd_init = {
576 .name = "lcd",
577 .ops = &dmn_ops,
578 .parent_names = dmn_clk_parents,
579 .num_parents = ARRAY_SIZE(dmn_clk_parents),
580};
581
582static struct clk_dmn clk_lcd = {
583 .regofs = SIRFSOC_CLKC_LCD_CFG,
584 .enable_bit = 10,
585 .hw = {
586 .init = &clk_lcd_init,
587 },
588};
589
590static struct clk_init_data clk_vpp_init = {
591 .name = "vpp",
592 .ops = &dmn_ops,
593 .parent_names = dmn_clk_parents,
594 .num_parents = ARRAY_SIZE(dmn_clk_parents),
595};
596
597static struct clk_dmn clk_vpp = {
598 .regofs = SIRFSOC_CLKC_LCD_CFG,
599 .enable_bit = 11,
600 .hw = {
601 .init = &clk_vpp_init,
602 },
603};
604
605static struct clk_init_data clk_mmc01_init = {
606 .name = "mmc01",
607 .ops = &dmn_ops,
608 .parent_names = dmn_clk_parents,
609 .num_parents = ARRAY_SIZE(dmn_clk_parents),
610};
611
612static struct clk_init_data clk_mmc23_init = {
613 .name = "mmc23",
614 .ops = &dmn_ops,
615 .parent_names = dmn_clk_parents,
616 .num_parents = ARRAY_SIZE(dmn_clk_parents),
617};
618
619static struct clk_init_data clk_mmc45_init = {
620 .name = "mmc45",
621 .ops = &dmn_ops,
622 .parent_names = dmn_clk_parents,
623 .num_parents = ARRAY_SIZE(dmn_clk_parents),
624};
625
626/*
627 * peripheral controllers in io domain
628 */
629
630static int std_clk_is_enabled(struct clk_hw *hw)
631{
632 u32 reg;
633 int bit;
634 struct clk_std *clk = to_stdclk(hw);
635
636 bit = clk->enable_bit % 32;
637 reg = clk->enable_bit / 32;
638 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
639
640 return !!(clkc_readl(reg) & BIT(bit));
641}
642
643static int std_clk_enable(struct clk_hw *hw)
644{
645 u32 val, reg;
646 int bit;
647 struct clk_std *clk = to_stdclk(hw);
648
649 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
650
651 bit = clk->enable_bit % 32;
652 reg = clk->enable_bit / 32;
653 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
654
655 val = clkc_readl(reg) | BIT(bit);
656 clkc_writel(val, reg);
657 return 0;
658}
659
660static void std_clk_disable(struct clk_hw *hw)
661{
662 u32 val, reg;
663 int bit;
664 struct clk_std *clk = to_stdclk(hw);
665
666 BUG_ON(clk->enable_bit < 0 || clk->enable_bit > 63);
667
668 bit = clk->enable_bit % 32;
669 reg = clk->enable_bit / 32;
670 reg = SIRFSOC_CLKC_CLK_EN0 + reg * sizeof(reg);
671
672 val = clkc_readl(reg) & ~BIT(bit);
673 clkc_writel(val, reg);
674}
675
676static const char *std_clk_io_parents[] = {
677 "io",
678};
679
680static struct clk_ops ios_ops = {
681 .is_enabled = std_clk_is_enabled,
682 .enable = std_clk_enable,
683 .disable = std_clk_disable,
684};
685
686static struct clk_init_data clk_cphif_init = {
687 .name = "cphif",
688 .ops = &ios_ops,
689 .parent_names = std_clk_io_parents,
690 .num_parents = ARRAY_SIZE(std_clk_io_parents),
691};
692
693static struct clk_std clk_cphif = {
694 .enable_bit = 20,
695 .hw = {
696 .init = &clk_cphif_init,
697 },
698};
699
700static struct clk_init_data clk_dmac0_init = {
701 .name = "dmac0",
702 .ops = &ios_ops,
703 .parent_names = std_clk_io_parents,
704 .num_parents = ARRAY_SIZE(std_clk_io_parents),
705};
706
707static struct clk_std clk_dmac0 = {
708 .enable_bit = 32,
709 .hw = {
710 .init = &clk_dmac0_init,
711 },
712};
713
714static struct clk_init_data clk_dmac1_init = {
715 .name = "dmac1",
716 .ops = &ios_ops,
717 .parent_names = std_clk_io_parents,
718 .num_parents = ARRAY_SIZE(std_clk_io_parents),
719};
720
721static struct clk_std clk_dmac1 = {
722 .enable_bit = 33,
723 .hw = {
724 .init = &clk_dmac1_init,
725 },
726};
727
728static struct clk_init_data clk_audio_init = {
729 .name = "audio",
730 .ops = &ios_ops,
731 .parent_names = std_clk_io_parents,
732 .num_parents = ARRAY_SIZE(std_clk_io_parents),
733};
734
735static struct clk_std clk_audio = {
736 .enable_bit = 35,
737 .hw = {
738 .init = &clk_audio_init,
739 },
740};
741
742static struct clk_init_data clk_uart0_init = {
743 .name = "uart0",
744 .ops = &ios_ops,
745 .parent_names = std_clk_io_parents,
746 .num_parents = ARRAY_SIZE(std_clk_io_parents),
747};
748
749static struct clk_std clk_uart0 = {
750 .enable_bit = 36,
751 .hw = {
752 .init = &clk_uart0_init,
753 },
754};
755
756static struct clk_init_data clk_uart1_init = {
757 .name = "uart1",
758 .ops = &ios_ops,
759 .parent_names = std_clk_io_parents,
760 .num_parents = ARRAY_SIZE(std_clk_io_parents),
761};
762
763static struct clk_std clk_uart1 = {
764 .enable_bit = 37,
765 .hw = {
766 .init = &clk_uart1_init,
767 },
768};
769
770static struct clk_init_data clk_uart2_init = {
771 .name = "uart2",
772 .ops = &ios_ops,
773 .parent_names = std_clk_io_parents,
774 .num_parents = ARRAY_SIZE(std_clk_io_parents),
775};
776
777static struct clk_std clk_uart2 = {
778 .enable_bit = 38,
779 .hw = {
780 .init = &clk_uart2_init,
781 },
782};
783
784static struct clk_init_data clk_usp0_init = {
785 .name = "usp0",
786 .ops = &ios_ops,
787 .parent_names = std_clk_io_parents,
788 .num_parents = ARRAY_SIZE(std_clk_io_parents),
789};
790
791static struct clk_std clk_usp0 = {
792 .enable_bit = 39,
793 .hw = {
794 .init = &clk_usp0_init,
795 },
796};
797
798static struct clk_init_data clk_usp1_init = {
799 .name = "usp1",
800 .ops = &ios_ops,
801 .parent_names = std_clk_io_parents,
802 .num_parents = ARRAY_SIZE(std_clk_io_parents),
803};
804
805static struct clk_std clk_usp1 = {
806 .enable_bit = 40,
807 .hw = {
808 .init = &clk_usp1_init,
809 },
810};
811
812static struct clk_init_data clk_usp2_init = {
813 .name = "usp2",
814 .ops = &ios_ops,
815 .parent_names = std_clk_io_parents,
816 .num_parents = ARRAY_SIZE(std_clk_io_parents),
817};
818
819static struct clk_std clk_usp2 = {
820 .enable_bit = 41,
821 .hw = {
822 .init = &clk_usp2_init,
823 },
824};
825
826static struct clk_init_data clk_vip_init = {
827 .name = "vip",
828 .ops = &ios_ops,
829 .parent_names = std_clk_io_parents,
830 .num_parents = ARRAY_SIZE(std_clk_io_parents),
831};
832
833static struct clk_std clk_vip = {
834 .enable_bit = 42,
835 .hw = {
836 .init = &clk_vip_init,
837 },
838};
839
840static struct clk_init_data clk_spi0_init = {
841 .name = "spi0",
842 .ops = &ios_ops,
843 .parent_names = std_clk_io_parents,
844 .num_parents = ARRAY_SIZE(std_clk_io_parents),
845};
846
847static struct clk_std clk_spi0 = {
848 .enable_bit = 43,
849 .hw = {
850 .init = &clk_spi0_init,
851 },
852};
853
854static struct clk_init_data clk_spi1_init = {
855 .name = "spi1",
856 .ops = &ios_ops,
857 .parent_names = std_clk_io_parents,
858 .num_parents = ARRAY_SIZE(std_clk_io_parents),
859};
860
861static struct clk_std clk_spi1 = {
862 .enable_bit = 44,
863 .hw = {
864 .init = &clk_spi1_init,
865 },
866};
867
868static struct clk_init_data clk_tsc_init = {
869 .name = "tsc",
870 .ops = &ios_ops,
871 .parent_names = std_clk_io_parents,
872 .num_parents = ARRAY_SIZE(std_clk_io_parents),
873};
874
875static struct clk_std clk_tsc = {
876 .enable_bit = 45,
877 .hw = {
878 .init = &clk_tsc_init,
879 },
880};
881
882static struct clk_init_data clk_i2c0_init = {
883 .name = "i2c0",
884 .ops = &ios_ops,
885 .parent_names = std_clk_io_parents,
886 .num_parents = ARRAY_SIZE(std_clk_io_parents),
887};
888
889static struct clk_std clk_i2c0 = {
890 .enable_bit = 46,
891 .hw = {
892 .init = &clk_i2c0_init,
893 },
894};
895
896static struct clk_init_data clk_i2c1_init = {
897 .name = "i2c1",
898 .ops = &ios_ops,
899 .parent_names = std_clk_io_parents,
900 .num_parents = ARRAY_SIZE(std_clk_io_parents),
901};
902
903static struct clk_std clk_i2c1 = {
904 .enable_bit = 47,
905 .hw = {
906 .init = &clk_i2c1_init,
907 },
908};
909
910static struct clk_init_data clk_pwmc_init = {
911 .name = "pwmc",
912 .ops = &ios_ops,
913 .parent_names = std_clk_io_parents,
914 .num_parents = ARRAY_SIZE(std_clk_io_parents),
915};
916
917static struct clk_std clk_pwmc = {
918 .enable_bit = 48,
919 .hw = {
920 .init = &clk_pwmc_init,
921 },
922};
923
924static struct clk_init_data clk_efuse_init = {
925 .name = "efuse",
926 .ops = &ios_ops,
927 .parent_names = std_clk_io_parents,
928 .num_parents = ARRAY_SIZE(std_clk_io_parents),
929};
930
931static struct clk_std clk_efuse = {
932 .enable_bit = 49,
933 .hw = {
934 .init = &clk_efuse_init,
935 },
936};
937
938static struct clk_init_data clk_pulse_init = {
939 .name = "pulse",
940 .ops = &ios_ops,
941 .parent_names = std_clk_io_parents,
942 .num_parents = ARRAY_SIZE(std_clk_io_parents),
943};
944
945static struct clk_std clk_pulse = {
946 .enable_bit = 50,
947 .hw = {
948 .init = &clk_pulse_init,
949 },
950};
951
952static const char *std_clk_dsp_parents[] = {
953 "dsp",
954};
955
956static struct clk_init_data clk_gps_init = {
957 .name = "gps",
958 .ops = &ios_ops,
959 .parent_names = std_clk_dsp_parents,
960 .num_parents = ARRAY_SIZE(std_clk_dsp_parents),
961};
962
963static struct clk_std clk_gps = {
964 .enable_bit = 1,
965 .hw = {
966 .init = &clk_gps_init,
967 },
968};
969
970static struct clk_init_data clk_mf_init = {
971 .name = "mf",
972 .ops = &ios_ops,
973 .parent_names = std_clk_io_parents,
974 .num_parents = ARRAY_SIZE(std_clk_io_parents),
975};
976
977static struct clk_std clk_mf = {
978 .enable_bit = 2,
979 .hw = {
980 .init = &clk_mf_init,
981 },
982};
983
984static const char *std_clk_sys_parents[] = {
985 "sys",
986};
987
988static struct clk_init_data clk_security_init = {
989 .name = "security",
990 .ops = &ios_ops,
991 .parent_names = std_clk_sys_parents,
992 .num_parents = ARRAY_SIZE(std_clk_sys_parents),
993};
994
995static struct clk_std clk_security = {
996 .enable_bit = 19,
997 .hw = {
998 .init = &clk_security_init,
999 },
1000};
1001
1002static const char *std_clk_usb_parents[] = {
1003 "usb_pll",
1004};
1005
1006static struct clk_init_data clk_usb0_init = {
1007 .name = "usb0",
1008 .ops = &ios_ops,
1009 .parent_names = std_clk_usb_parents,
1010 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1011};
1012
1013static struct clk_std clk_usb0 = {
1014 .enable_bit = 16,
1015 .hw = {
1016 .init = &clk_usb0_init,
1017 },
1018};
1019
1020static struct clk_init_data clk_usb1_init = {
1021 .name = "usb1",
1022 .ops = &ios_ops,
1023 .parent_names = std_clk_usb_parents,
1024 .num_parents = ARRAY_SIZE(std_clk_usb_parents),
1025};
1026
1027static struct clk_std clk_usb1 = {
1028 .enable_bit = 17,
1029 .hw = {
1030 .init = &clk_usb1_init,
1031 },
1032};