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1#include <linux/kernel.h>
2#include <linux/sched.h>
3#include <linux/init.h>
4#include <linux/module.h>
5#include <linux/timer.h>
6#include <linux/acpi_pmtmr.h>
7#include <linux/cpufreq.h>
8#include <linux/delay.h>
9#include <linux/clocksource.h>
10#include <linux/percpu.h>
11#include <linux/timex.h>
12
13#include <asm/hpet.h>
14#include <asm/timer.h>
15#include <asm/vgtod.h>
16#include <asm/time.h>
17#include <asm/delay.h>
18#include <asm/hypervisor.h>
19#include <asm/nmi.h>
20#include <asm/x86_init.h>
21
22unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
23EXPORT_SYMBOL(cpu_khz);
24
25unsigned int __read_mostly tsc_khz;
26EXPORT_SYMBOL(tsc_khz);
27
28/*
29 * TSC can be unstable due to cpufreq or due to unsynced TSCs
30 */
31static int __read_mostly tsc_unstable;
32
33/* native_sched_clock() is called before tsc_init(), so
34 we must start with the TSC soft disabled to prevent
35 erroneous rdtsc usage on !cpu_has_tsc processors */
36static int __read_mostly tsc_disabled = -1;
37
38static int tsc_clocksource_reliable;
39/*
40 * Scheduler clock - returns current time in nanosec units.
41 */
42u64 native_sched_clock(void)
43{
44 u64 this_offset;
45
46 /*
47 * Fall back to jiffies if there's no TSC available:
48 * ( But note that we still use it if the TSC is marked
49 * unstable. We do this because unlike Time Of Day,
50 * the scheduler clock tolerates small errors and it's
51 * very important for it to be as fast as the platform
52 * can achieve it. )
53 */
54 if (unlikely(tsc_disabled)) {
55 /* No locking but a rare wrong value is not a big deal: */
56 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
57 }
58
59 /* read the Time Stamp Counter: */
60 rdtscll(this_offset);
61
62 /* return the value in ns */
63 return __cycles_2_ns(this_offset);
64}
65
66/* We need to define a real function for sched_clock, to override the
67 weak default version */
68#ifdef CONFIG_PARAVIRT
69unsigned long long sched_clock(void)
70{
71 return paravirt_sched_clock();
72}
73#else
74unsigned long long
75sched_clock(void) __attribute__((alias("native_sched_clock")));
76#endif
77
78int check_tsc_unstable(void)
79{
80 return tsc_unstable;
81}
82EXPORT_SYMBOL_GPL(check_tsc_unstable);
83
84#ifdef CONFIG_X86_TSC
85int __init notsc_setup(char *str)
86{
87 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, "
88 "cannot disable TSC completely.\n");
89 tsc_disabled = 1;
90 return 1;
91}
92#else
93/*
94 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
95 * in cpu/common.c
96 */
97int __init notsc_setup(char *str)
98{
99 setup_clear_cpu_cap(X86_FEATURE_TSC);
100 return 1;
101}
102#endif
103
104__setup("notsc", notsc_setup);
105
106static int no_sched_irq_time;
107
108static int __init tsc_setup(char *str)
109{
110 if (!strcmp(str, "reliable"))
111 tsc_clocksource_reliable = 1;
112 if (!strncmp(str, "noirqtime", 9))
113 no_sched_irq_time = 1;
114 return 1;
115}
116
117__setup("tsc=", tsc_setup);
118
119#define MAX_RETRIES 5
120#define SMI_TRESHOLD 50000
121
122/*
123 * Read TSC and the reference counters. Take care of SMI disturbance
124 */
125static u64 tsc_read_refs(u64 *p, int hpet)
126{
127 u64 t1, t2;
128 int i;
129
130 for (i = 0; i < MAX_RETRIES; i++) {
131 t1 = get_cycles();
132 if (hpet)
133 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
134 else
135 *p = acpi_pm_read_early();
136 t2 = get_cycles();
137 if ((t2 - t1) < SMI_TRESHOLD)
138 return t2;
139 }
140 return ULLONG_MAX;
141}
142
143/*
144 * Calculate the TSC frequency from HPET reference
145 */
146static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
147{
148 u64 tmp;
149
150 if (hpet2 < hpet1)
151 hpet2 += 0x100000000ULL;
152 hpet2 -= hpet1;
153 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
154 do_div(tmp, 1000000);
155 do_div(deltatsc, tmp);
156
157 return (unsigned long) deltatsc;
158}
159
160/*
161 * Calculate the TSC frequency from PMTimer reference
162 */
163static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
164{
165 u64 tmp;
166
167 if (!pm1 && !pm2)
168 return ULONG_MAX;
169
170 if (pm2 < pm1)
171 pm2 += (u64)ACPI_PM_OVRRUN;
172 pm2 -= pm1;
173 tmp = pm2 * 1000000000LL;
174 do_div(tmp, PMTMR_TICKS_PER_SEC);
175 do_div(deltatsc, tmp);
176
177 return (unsigned long) deltatsc;
178}
179
180#define CAL_MS 10
181#define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS))
182#define CAL_PIT_LOOPS 1000
183
184#define CAL2_MS 50
185#define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS))
186#define CAL2_PIT_LOOPS 5000
187
188
189/*
190 * Try to calibrate the TSC against the Programmable
191 * Interrupt Timer and return the frequency of the TSC
192 * in kHz.
193 *
194 * Return ULONG_MAX on failure to calibrate.
195 */
196static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
197{
198 u64 tsc, t1, t2, delta;
199 unsigned long tscmin, tscmax;
200 int pitcnt;
201
202 /* Set the Gate high, disable speaker */
203 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
204
205 /*
206 * Setup CTC channel 2* for mode 0, (interrupt on terminal
207 * count mode), binary count. Set the latch register to 50ms
208 * (LSB then MSB) to begin countdown.
209 */
210 outb(0xb0, 0x43);
211 outb(latch & 0xff, 0x42);
212 outb(latch >> 8, 0x42);
213
214 tsc = t1 = t2 = get_cycles();
215
216 pitcnt = 0;
217 tscmax = 0;
218 tscmin = ULONG_MAX;
219 while ((inb(0x61) & 0x20) == 0) {
220 t2 = get_cycles();
221 delta = t2 - tsc;
222 tsc = t2;
223 if ((unsigned long) delta < tscmin)
224 tscmin = (unsigned int) delta;
225 if ((unsigned long) delta > tscmax)
226 tscmax = (unsigned int) delta;
227 pitcnt++;
228 }
229
230 /*
231 * Sanity checks:
232 *
233 * If we were not able to read the PIT more than loopmin
234 * times, then we have been hit by a massive SMI
235 *
236 * If the maximum is 10 times larger than the minimum,
237 * then we got hit by an SMI as well.
238 */
239 if (pitcnt < loopmin || tscmax > 10 * tscmin)
240 return ULONG_MAX;
241
242 /* Calculate the PIT value */
243 delta = t2 - t1;
244 do_div(delta, ms);
245 return delta;
246}
247
248/*
249 * This reads the current MSB of the PIT counter, and
250 * checks if we are running on sufficiently fast and
251 * non-virtualized hardware.
252 *
253 * Our expectations are:
254 *
255 * - the PIT is running at roughly 1.19MHz
256 *
257 * - each IO is going to take about 1us on real hardware,
258 * but we allow it to be much faster (by a factor of 10) or
259 * _slightly_ slower (ie we allow up to a 2us read+counter
260 * update - anything else implies a unacceptably slow CPU
261 * or PIT for the fast calibration to work.
262 *
263 * - with 256 PIT ticks to read the value, we have 214us to
264 * see the same MSB (and overhead like doing a single TSC
265 * read per MSB value etc).
266 *
267 * - We're doing 2 reads per loop (LSB, MSB), and we expect
268 * them each to take about a microsecond on real hardware.
269 * So we expect a count value of around 100. But we'll be
270 * generous, and accept anything over 50.
271 *
272 * - if the PIT is stuck, and we see *many* more reads, we
273 * return early (and the next caller of pit_expect_msb()
274 * then consider it a failure when they don't see the
275 * next expected value).
276 *
277 * These expectations mean that we know that we have seen the
278 * transition from one expected value to another with a fairly
279 * high accuracy, and we didn't miss any events. We can thus
280 * use the TSC value at the transitions to calculate a pretty
281 * good value for the TSC frequencty.
282 */
283static inline int pit_verify_msb(unsigned char val)
284{
285 /* Ignore LSB */
286 inb(0x42);
287 return inb(0x42) == val;
288}
289
290static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
291{
292 int count;
293 u64 tsc = 0;
294
295 for (count = 0; count < 50000; count++) {
296 if (!pit_verify_msb(val))
297 break;
298 tsc = get_cycles();
299 }
300 *deltap = get_cycles() - tsc;
301 *tscp = tsc;
302
303 /*
304 * We require _some_ success, but the quality control
305 * will be based on the error terms on the TSC values.
306 */
307 return count > 5;
308}
309
310/*
311 * How many MSB values do we want to see? We aim for
312 * a maximum error rate of 500ppm (in practice the
313 * real error is much smaller), but refuse to spend
314 * more than 25ms on it.
315 */
316#define MAX_QUICK_PIT_MS 25
317#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
318
319static unsigned long quick_pit_calibrate(void)
320{
321 int i;
322 u64 tsc, delta;
323 unsigned long d1, d2;
324
325 /* Set the Gate high, disable speaker */
326 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
327
328 /*
329 * Counter 2, mode 0 (one-shot), binary count
330 *
331 * NOTE! Mode 2 decrements by two (and then the
332 * output is flipped each time, giving the same
333 * final output frequency as a decrement-by-one),
334 * so mode 0 is much better when looking at the
335 * individual counts.
336 */
337 outb(0xb0, 0x43);
338
339 /* Start at 0xffff */
340 outb(0xff, 0x42);
341 outb(0xff, 0x42);
342
343 /*
344 * The PIT starts counting at the next edge, so we
345 * need to delay for a microsecond. The easiest way
346 * to do that is to just read back the 16-bit counter
347 * once from the PIT.
348 */
349 pit_verify_msb(0);
350
351 if (pit_expect_msb(0xff, &tsc, &d1)) {
352 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
353 if (!pit_expect_msb(0xff-i, &delta, &d2))
354 break;
355
356 /*
357 * Iterate until the error is less than 500 ppm
358 */
359 delta -= tsc;
360 if (d1+d2 >= delta >> 11)
361 continue;
362
363 /*
364 * Check the PIT one more time to verify that
365 * all TSC reads were stable wrt the PIT.
366 *
367 * This also guarantees serialization of the
368 * last cycle read ('d2') in pit_expect_msb.
369 */
370 if (!pit_verify_msb(0xfe - i))
371 break;
372 goto success;
373 }
374 }
375 printk("Fast TSC calibration failed\n");
376 return 0;
377
378success:
379 /*
380 * Ok, if we get here, then we've seen the
381 * MSB of the PIT decrement 'i' times, and the
382 * error has shrunk to less than 500 ppm.
383 *
384 * As a result, we can depend on there not being
385 * any odd delays anywhere, and the TSC reads are
386 * reliable (within the error). We also adjust the
387 * delta to the middle of the error bars, just
388 * because it looks nicer.
389 *
390 * kHz = ticks / time-in-seconds / 1000;
391 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
392 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
393 */
394 delta += (long)(d2 - d1)/2;
395 delta *= PIT_TICK_RATE;
396 do_div(delta, i*256*1000);
397 printk("Fast TSC calibration using PIT\n");
398 return delta;
399}
400
401/**
402 * native_calibrate_tsc - calibrate the tsc on boot
403 */
404unsigned long native_calibrate_tsc(void)
405{
406 u64 tsc1, tsc2, delta, ref1, ref2;
407 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
408 unsigned long flags, latch, ms, fast_calibrate;
409 int hpet = is_hpet_enabled(), i, loopmin;
410
411 local_irq_save(flags);
412 fast_calibrate = quick_pit_calibrate();
413 local_irq_restore(flags);
414 if (fast_calibrate)
415 return fast_calibrate;
416
417 /*
418 * Run 5 calibration loops to get the lowest frequency value
419 * (the best estimate). We use two different calibration modes
420 * here:
421 *
422 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
423 * load a timeout of 50ms. We read the time right after we
424 * started the timer and wait until the PIT count down reaches
425 * zero. In each wait loop iteration we read the TSC and check
426 * the delta to the previous read. We keep track of the min
427 * and max values of that delta. The delta is mostly defined
428 * by the IO time of the PIT access, so we can detect when a
429 * SMI/SMM disturbance happened between the two reads. If the
430 * maximum time is significantly larger than the minimum time,
431 * then we discard the result and have another try.
432 *
433 * 2) Reference counter. If available we use the HPET or the
434 * PMTIMER as a reference to check the sanity of that value.
435 * We use separate TSC readouts and check inside of the
436 * reference read for a SMI/SMM disturbance. We dicard
437 * disturbed values here as well. We do that around the PIT
438 * calibration delay loop as we have to wait for a certain
439 * amount of time anyway.
440 */
441
442 /* Preset PIT loop values */
443 latch = CAL_LATCH;
444 ms = CAL_MS;
445 loopmin = CAL_PIT_LOOPS;
446
447 for (i = 0; i < 3; i++) {
448 unsigned long tsc_pit_khz;
449
450 /*
451 * Read the start value and the reference count of
452 * hpet/pmtimer when available. Then do the PIT
453 * calibration, which will take at least 50ms, and
454 * read the end value.
455 */
456 local_irq_save(flags);
457 tsc1 = tsc_read_refs(&ref1, hpet);
458 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
459 tsc2 = tsc_read_refs(&ref2, hpet);
460 local_irq_restore(flags);
461
462 /* Pick the lowest PIT TSC calibration so far */
463 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
464
465 /* hpet or pmtimer available ? */
466 if (ref1 == ref2)
467 continue;
468
469 /* Check, whether the sampling was disturbed by an SMI */
470 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
471 continue;
472
473 tsc2 = (tsc2 - tsc1) * 1000000LL;
474 if (hpet)
475 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
476 else
477 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
478
479 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
480
481 /* Check the reference deviation */
482 delta = ((u64) tsc_pit_min) * 100;
483 do_div(delta, tsc_ref_min);
484
485 /*
486 * If both calibration results are inside a 10% window
487 * then we can be sure, that the calibration
488 * succeeded. We break out of the loop right away. We
489 * use the reference value, as it is more precise.
490 */
491 if (delta >= 90 && delta <= 110) {
492 printk(KERN_INFO
493 "TSC: PIT calibration matches %s. %d loops\n",
494 hpet ? "HPET" : "PMTIMER", i + 1);
495 return tsc_ref_min;
496 }
497
498 /*
499 * Check whether PIT failed more than once. This
500 * happens in virtualized environments. We need to
501 * give the virtual PC a slightly longer timeframe for
502 * the HPET/PMTIMER to make the result precise.
503 */
504 if (i == 1 && tsc_pit_min == ULONG_MAX) {
505 latch = CAL2_LATCH;
506 ms = CAL2_MS;
507 loopmin = CAL2_PIT_LOOPS;
508 }
509 }
510
511 /*
512 * Now check the results.
513 */
514 if (tsc_pit_min == ULONG_MAX) {
515 /* PIT gave no useful value */
516 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n");
517
518 /* We don't have an alternative source, disable TSC */
519 if (!hpet && !ref1 && !ref2) {
520 printk("TSC: No reference (HPET/PMTIMER) available\n");
521 return 0;
522 }
523
524 /* The alternative source failed as well, disable TSC */
525 if (tsc_ref_min == ULONG_MAX) {
526 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration "
527 "failed.\n");
528 return 0;
529 }
530
531 /* Use the alternative source */
532 printk(KERN_INFO "TSC: using %s reference calibration\n",
533 hpet ? "HPET" : "PMTIMER");
534
535 return tsc_ref_min;
536 }
537
538 /* We don't have an alternative source, use the PIT calibration value */
539 if (!hpet && !ref1 && !ref2) {
540 printk(KERN_INFO "TSC: Using PIT calibration value\n");
541 return tsc_pit_min;
542 }
543
544 /* The alternative source failed, use the PIT calibration value */
545 if (tsc_ref_min == ULONG_MAX) {
546 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. "
547 "Using PIT calibration\n");
548 return tsc_pit_min;
549 }
550
551 /*
552 * The calibration values differ too much. In doubt, we use
553 * the PIT value as we know that there are PMTIMERs around
554 * running at double speed. At least we let the user know:
555 */
556 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n",
557 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
558 printk(KERN_INFO "TSC: Using PIT calibration value\n");
559 return tsc_pit_min;
560}
561
562int recalibrate_cpu_khz(void)
563{
564#ifndef CONFIG_SMP
565 unsigned long cpu_khz_old = cpu_khz;
566
567 if (cpu_has_tsc) {
568 tsc_khz = x86_platform.calibrate_tsc();
569 cpu_khz = tsc_khz;
570 cpu_data(0).loops_per_jiffy =
571 cpufreq_scale(cpu_data(0).loops_per_jiffy,
572 cpu_khz_old, cpu_khz);
573 return 0;
574 } else
575 return -ENODEV;
576#else
577 return -ENODEV;
578#endif
579}
580
581EXPORT_SYMBOL(recalibrate_cpu_khz);
582
583
584/* Accelerators for sched_clock()
585 * convert from cycles(64bits) => nanoseconds (64bits)
586 * basic equation:
587 * ns = cycles / (freq / ns_per_sec)
588 * ns = cycles * (ns_per_sec / freq)
589 * ns = cycles * (10^9 / (cpu_khz * 10^3))
590 * ns = cycles * (10^6 / cpu_khz)
591 *
592 * Then we use scaling math (suggested by george@mvista.com) to get:
593 * ns = cycles * (10^6 * SC / cpu_khz) / SC
594 * ns = cycles * cyc2ns_scale / SC
595 *
596 * And since SC is a constant power of two, we can convert the div
597 * into a shift.
598 *
599 * We can use khz divisor instead of mhz to keep a better precision, since
600 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
601 * (mathieu.desnoyers@polymtl.ca)
602 *
603 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
604 */
605
606DEFINE_PER_CPU(unsigned long, cyc2ns);
607DEFINE_PER_CPU(unsigned long long, cyc2ns_offset);
608
609static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
610{
611 unsigned long long tsc_now, ns_now, *offset;
612 unsigned long flags, *scale;
613
614 local_irq_save(flags);
615 sched_clock_idle_sleep_event();
616
617 scale = &per_cpu(cyc2ns, cpu);
618 offset = &per_cpu(cyc2ns_offset, cpu);
619
620 rdtscll(tsc_now);
621 ns_now = __cycles_2_ns(tsc_now);
622
623 if (cpu_khz) {
624 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz;
625 *offset = ns_now - (tsc_now * *scale >> CYC2NS_SCALE_FACTOR);
626 }
627
628 sched_clock_idle_wakeup_event(0);
629 local_irq_restore(flags);
630}
631
632static unsigned long long cyc2ns_suspend;
633
634void save_sched_clock_state(void)
635{
636 if (!sched_clock_stable)
637 return;
638
639 cyc2ns_suspend = sched_clock();
640}
641
642/*
643 * Even on processors with invariant TSC, TSC gets reset in some the
644 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
645 * arbitrary value (still sync'd across cpu's) during resume from such sleep
646 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
647 * that sched_clock() continues from the point where it was left off during
648 * suspend.
649 */
650void restore_sched_clock_state(void)
651{
652 unsigned long long offset;
653 unsigned long flags;
654 int cpu;
655
656 if (!sched_clock_stable)
657 return;
658
659 local_irq_save(flags);
660
661 __this_cpu_write(cyc2ns_offset, 0);
662 offset = cyc2ns_suspend - sched_clock();
663
664 for_each_possible_cpu(cpu)
665 per_cpu(cyc2ns_offset, cpu) = offset;
666
667 local_irq_restore(flags);
668}
669
670#ifdef CONFIG_CPU_FREQ
671
672/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
673 * changes.
674 *
675 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
676 * not that important because current Opteron setups do not support
677 * scaling on SMP anyroads.
678 *
679 * Should fix up last_tsc too. Currently gettimeofday in the
680 * first tick after the change will be slightly wrong.
681 */
682
683static unsigned int ref_freq;
684static unsigned long loops_per_jiffy_ref;
685static unsigned long tsc_khz_ref;
686
687static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
688 void *data)
689{
690 struct cpufreq_freqs *freq = data;
691 unsigned long *lpj;
692
693 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
694 return 0;
695
696 lpj = &boot_cpu_data.loops_per_jiffy;
697#ifdef CONFIG_SMP
698 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
699 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
700#endif
701
702 if (!ref_freq) {
703 ref_freq = freq->old;
704 loops_per_jiffy_ref = *lpj;
705 tsc_khz_ref = tsc_khz;
706 }
707 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
708 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
709 (val == CPUFREQ_RESUMECHANGE)) {
710 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
711
712 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
713 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
714 mark_tsc_unstable("cpufreq changes");
715 }
716
717 set_cyc2ns_scale(tsc_khz, freq->cpu);
718
719 return 0;
720}
721
722static struct notifier_block time_cpufreq_notifier_block = {
723 .notifier_call = time_cpufreq_notifier
724};
725
726static int __init cpufreq_tsc(void)
727{
728 if (!cpu_has_tsc)
729 return 0;
730 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
731 return 0;
732 cpufreq_register_notifier(&time_cpufreq_notifier_block,
733 CPUFREQ_TRANSITION_NOTIFIER);
734 return 0;
735}
736
737core_initcall(cpufreq_tsc);
738
739#endif /* CONFIG_CPU_FREQ */
740
741/* clocksource code */
742
743static struct clocksource clocksource_tsc;
744
745/*
746 * We compare the TSC to the cycle_last value in the clocksource
747 * structure to avoid a nasty time-warp. This can be observed in a
748 * very small window right after one CPU updated cycle_last under
749 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
750 * is smaller than the cycle_last reference value due to a TSC which
751 * is slighty behind. This delta is nowhere else observable, but in
752 * that case it results in a forward time jump in the range of hours
753 * due to the unsigned delta calculation of the time keeping core
754 * code, which is necessary to support wrapping clocksources like pm
755 * timer.
756 */
757static cycle_t read_tsc(struct clocksource *cs)
758{
759 cycle_t ret = (cycle_t)get_cycles();
760
761 return ret >= clocksource_tsc.cycle_last ?
762 ret : clocksource_tsc.cycle_last;
763}
764
765static void resume_tsc(struct clocksource *cs)
766{
767 clocksource_tsc.cycle_last = 0;
768}
769
770static struct clocksource clocksource_tsc = {
771 .name = "tsc",
772 .rating = 300,
773 .read = read_tsc,
774 .resume = resume_tsc,
775 .mask = CLOCKSOURCE_MASK(64),
776 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
777 CLOCK_SOURCE_MUST_VERIFY,
778#ifdef CONFIG_X86_64
779 .archdata = { .vclock_mode = VCLOCK_TSC },
780#endif
781};
782
783void mark_tsc_unstable(char *reason)
784{
785 if (!tsc_unstable) {
786 tsc_unstable = 1;
787 sched_clock_stable = 0;
788 disable_sched_clock_irqtime();
789 printk(KERN_INFO "Marking TSC unstable due to %s\n", reason);
790 /* Change only the rating, when not registered */
791 if (clocksource_tsc.mult)
792 clocksource_mark_unstable(&clocksource_tsc);
793 else {
794 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
795 clocksource_tsc.rating = 0;
796 }
797 }
798}
799
800EXPORT_SYMBOL_GPL(mark_tsc_unstable);
801
802static void __init check_system_tsc_reliable(void)
803{
804#ifdef CONFIG_MGEODE_LX
805 /* RTSC counts during suspend */
806#define RTSC_SUSP 0x100
807 unsigned long res_low, res_high;
808
809 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
810 /* Geode_LX - the OLPC CPU has a very reliable TSC */
811 if (res_low & RTSC_SUSP)
812 tsc_clocksource_reliable = 1;
813#endif
814 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
815 tsc_clocksource_reliable = 1;
816}
817
818/*
819 * Make an educated guess if the TSC is trustworthy and synchronized
820 * over all CPUs.
821 */
822__cpuinit int unsynchronized_tsc(void)
823{
824 if (!cpu_has_tsc || tsc_unstable)
825 return 1;
826
827#ifdef CONFIG_SMP
828 if (apic_is_clustered_box())
829 return 1;
830#endif
831
832 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
833 return 0;
834
835 if (tsc_clocksource_reliable)
836 return 0;
837 /*
838 * Intel systems are normally all synchronized.
839 * Exceptions must mark TSC as unstable:
840 */
841 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
842 /* assume multi socket systems are not synchronized: */
843 if (num_possible_cpus() > 1)
844 return 1;
845 }
846
847 return 0;
848}
849
850
851static void tsc_refine_calibration_work(struct work_struct *work);
852static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
853/**
854 * tsc_refine_calibration_work - Further refine tsc freq calibration
855 * @work - ignored.
856 *
857 * This functions uses delayed work over a period of a
858 * second to further refine the TSC freq value. Since this is
859 * timer based, instead of loop based, we don't block the boot
860 * process while this longer calibration is done.
861 *
862 * If there are any calibration anomalies (too many SMIs, etc),
863 * or the refined calibration is off by 1% of the fast early
864 * calibration, we throw out the new calibration and use the
865 * early calibration.
866 */
867static void tsc_refine_calibration_work(struct work_struct *work)
868{
869 static u64 tsc_start = -1, ref_start;
870 static int hpet;
871 u64 tsc_stop, ref_stop, delta;
872 unsigned long freq;
873
874 /* Don't bother refining TSC on unstable systems */
875 if (check_tsc_unstable())
876 goto out;
877
878 /*
879 * Since the work is started early in boot, we may be
880 * delayed the first time we expire. So set the workqueue
881 * again once we know timers are working.
882 */
883 if (tsc_start == -1) {
884 /*
885 * Only set hpet once, to avoid mixing hardware
886 * if the hpet becomes enabled later.
887 */
888 hpet = is_hpet_enabled();
889 schedule_delayed_work(&tsc_irqwork, HZ);
890 tsc_start = tsc_read_refs(&ref_start, hpet);
891 return;
892 }
893
894 tsc_stop = tsc_read_refs(&ref_stop, hpet);
895
896 /* hpet or pmtimer available ? */
897 if (ref_start == ref_stop)
898 goto out;
899
900 /* Check, whether the sampling was disturbed by an SMI */
901 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
902 goto out;
903
904 delta = tsc_stop - tsc_start;
905 delta *= 1000000LL;
906 if (hpet)
907 freq = calc_hpet_ref(delta, ref_start, ref_stop);
908 else
909 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
910
911 /* Make sure we're within 1% */
912 if (abs(tsc_khz - freq) > tsc_khz/100)
913 goto out;
914
915 tsc_khz = freq;
916 printk(KERN_INFO "Refined TSC clocksource calibration: "
917 "%lu.%03lu MHz.\n", (unsigned long)tsc_khz / 1000,
918 (unsigned long)tsc_khz % 1000);
919
920out:
921 clocksource_register_khz(&clocksource_tsc, tsc_khz);
922}
923
924
925static int __init init_tsc_clocksource(void)
926{
927 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
928 return 0;
929
930 if (tsc_clocksource_reliable)
931 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
932 /* lower the rating if we already know its unstable: */
933 if (check_tsc_unstable()) {
934 clocksource_tsc.rating = 0;
935 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
936 }
937 schedule_delayed_work(&tsc_irqwork, 0);
938 return 0;
939}
940/*
941 * We use device_initcall here, to ensure we run after the hpet
942 * is fully initialized, which may occur at fs_initcall time.
943 */
944device_initcall(init_tsc_clocksource);
945
946void __init tsc_init(void)
947{
948 u64 lpj;
949 int cpu;
950
951 x86_init.timers.tsc_pre_init();
952
953 if (!cpu_has_tsc)
954 return;
955
956 tsc_khz = x86_platform.calibrate_tsc();
957 cpu_khz = tsc_khz;
958
959 if (!tsc_khz) {
960 mark_tsc_unstable("could not calculate TSC khz");
961 return;
962 }
963
964 printk("Detected %lu.%03lu MHz processor.\n",
965 (unsigned long)cpu_khz / 1000,
966 (unsigned long)cpu_khz % 1000);
967
968 /*
969 * Secondary CPUs do not run through tsc_init(), so set up
970 * all the scale factors for all CPUs, assuming the same
971 * speed as the bootup CPU. (cpufreq notifiers will fix this
972 * up if their speed diverges)
973 */
974 for_each_possible_cpu(cpu)
975 set_cyc2ns_scale(cpu_khz, cpu);
976
977 if (tsc_disabled > 0)
978 return;
979
980 /* now allow native_sched_clock() to use rdtsc */
981 tsc_disabled = 0;
982
983 if (!no_sched_irq_time)
984 enable_sched_clock_irqtime();
985
986 lpj = ((u64)tsc_khz * 1000);
987 do_div(lpj, HZ);
988 lpj_fine = lpj;
989
990 use_tsc_delay();
991
992 if (unsynchronized_tsc())
993 mark_tsc_unstable("TSCs unsynchronized");
994
995 check_system_tsc_reliable();
996}
997
1#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
2
3#include <linux/kernel.h>
4#include <linux/sched.h>
5#include <linux/init.h>
6#include <linux/module.h>
7#include <linux/timer.h>
8#include <linux/acpi_pmtmr.h>
9#include <linux/cpufreq.h>
10#include <linux/delay.h>
11#include <linux/clocksource.h>
12#include <linux/percpu.h>
13#include <linux/timex.h>
14#include <linux/static_key.h>
15
16#include <asm/hpet.h>
17#include <asm/timer.h>
18#include <asm/vgtod.h>
19#include <asm/time.h>
20#include <asm/delay.h>
21#include <asm/hypervisor.h>
22#include <asm/nmi.h>
23#include <asm/x86_init.h>
24
25unsigned int __read_mostly cpu_khz; /* TSC clocks / usec, not used here */
26EXPORT_SYMBOL(cpu_khz);
27
28unsigned int __read_mostly tsc_khz;
29EXPORT_SYMBOL(tsc_khz);
30
31/*
32 * TSC can be unstable due to cpufreq or due to unsynced TSCs
33 */
34static int __read_mostly tsc_unstable;
35
36/* native_sched_clock() is called before tsc_init(), so
37 we must start with the TSC soft disabled to prevent
38 erroneous rdtsc usage on !cpu_has_tsc processors */
39static int __read_mostly tsc_disabled = -1;
40
41static struct static_key __use_tsc = STATIC_KEY_INIT;
42
43int tsc_clocksource_reliable;
44
45/*
46 * Use a ring-buffer like data structure, where a writer advances the head by
47 * writing a new data entry and a reader advances the tail when it observes a
48 * new entry.
49 *
50 * Writers are made to wait on readers until there's space to write a new
51 * entry.
52 *
53 * This means that we can always use an {offset, mul} pair to compute a ns
54 * value that is 'roughly' in the right direction, even if we're writing a new
55 * {offset, mul} pair during the clock read.
56 *
57 * The down-side is that we can no longer guarantee strict monotonicity anymore
58 * (assuming the TSC was that to begin with), because while we compute the
59 * intersection point of the two clock slopes and make sure the time is
60 * continuous at the point of switching; we can no longer guarantee a reader is
61 * strictly before or after the switch point.
62 *
63 * It does mean a reader no longer needs to disable IRQs in order to avoid
64 * CPU-Freq updates messing with his times, and similarly an NMI reader will
65 * no longer run the risk of hitting half-written state.
66 */
67
68struct cyc2ns {
69 struct cyc2ns_data data[2]; /* 0 + 2*24 = 48 */
70 struct cyc2ns_data *head; /* 48 + 8 = 56 */
71 struct cyc2ns_data *tail; /* 56 + 8 = 64 */
72}; /* exactly fits one cacheline */
73
74static DEFINE_PER_CPU_ALIGNED(struct cyc2ns, cyc2ns);
75
76struct cyc2ns_data *cyc2ns_read_begin(void)
77{
78 struct cyc2ns_data *head;
79
80 preempt_disable();
81
82 head = this_cpu_read(cyc2ns.head);
83 /*
84 * Ensure we observe the entry when we observe the pointer to it.
85 * matches the wmb from cyc2ns_write_end().
86 */
87 smp_read_barrier_depends();
88 head->__count++;
89 barrier();
90
91 return head;
92}
93
94void cyc2ns_read_end(struct cyc2ns_data *head)
95{
96 barrier();
97 /*
98 * If we're the outer most nested read; update the tail pointer
99 * when we're done. This notifies possible pending writers
100 * that we've observed the head pointer and that the other
101 * entry is now free.
102 */
103 if (!--head->__count) {
104 /*
105 * x86-TSO does not reorder writes with older reads;
106 * therefore once this write becomes visible to another
107 * cpu, we must be finished reading the cyc2ns_data.
108 *
109 * matches with cyc2ns_write_begin().
110 */
111 this_cpu_write(cyc2ns.tail, head);
112 }
113 preempt_enable();
114}
115
116/*
117 * Begin writing a new @data entry for @cpu.
118 *
119 * Assumes some sort of write side lock; currently 'provided' by the assumption
120 * that cpufreq will call its notifiers sequentially.
121 */
122static struct cyc2ns_data *cyc2ns_write_begin(int cpu)
123{
124 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
125 struct cyc2ns_data *data = c2n->data;
126
127 if (data == c2n->head)
128 data++;
129
130 /* XXX send an IPI to @cpu in order to guarantee a read? */
131
132 /*
133 * When we observe the tail write from cyc2ns_read_end(),
134 * the cpu must be done with that entry and its safe
135 * to start writing to it.
136 */
137 while (c2n->tail == data)
138 cpu_relax();
139
140 return data;
141}
142
143static void cyc2ns_write_end(int cpu, struct cyc2ns_data *data)
144{
145 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
146
147 /*
148 * Ensure the @data writes are visible before we publish the
149 * entry. Matches the data-depencency in cyc2ns_read_begin().
150 */
151 smp_wmb();
152
153 ACCESS_ONCE(c2n->head) = data;
154}
155
156/*
157 * Accelerators for sched_clock()
158 * convert from cycles(64bits) => nanoseconds (64bits)
159 * basic equation:
160 * ns = cycles / (freq / ns_per_sec)
161 * ns = cycles * (ns_per_sec / freq)
162 * ns = cycles * (10^9 / (cpu_khz * 10^3))
163 * ns = cycles * (10^6 / cpu_khz)
164 *
165 * Then we use scaling math (suggested by george@mvista.com) to get:
166 * ns = cycles * (10^6 * SC / cpu_khz) / SC
167 * ns = cycles * cyc2ns_scale / SC
168 *
169 * And since SC is a constant power of two, we can convert the div
170 * into a shift.
171 *
172 * We can use khz divisor instead of mhz to keep a better precision, since
173 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits.
174 * (mathieu.desnoyers@polymtl.ca)
175 *
176 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
177 */
178
179#define CYC2NS_SCALE_FACTOR 10 /* 2^10, carefully chosen */
180
181static void cyc2ns_data_init(struct cyc2ns_data *data)
182{
183 data->cyc2ns_mul = 0;
184 data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
185 data->cyc2ns_offset = 0;
186 data->__count = 0;
187}
188
189static void cyc2ns_init(int cpu)
190{
191 struct cyc2ns *c2n = &per_cpu(cyc2ns, cpu);
192
193 cyc2ns_data_init(&c2n->data[0]);
194 cyc2ns_data_init(&c2n->data[1]);
195
196 c2n->head = c2n->data;
197 c2n->tail = c2n->data;
198}
199
200static inline unsigned long long cycles_2_ns(unsigned long long cyc)
201{
202 struct cyc2ns_data *data, *tail;
203 unsigned long long ns;
204
205 /*
206 * See cyc2ns_read_*() for details; replicated in order to avoid
207 * an extra few instructions that came with the abstraction.
208 * Notable, it allows us to only do the __count and tail update
209 * dance when its actually needed.
210 */
211
212 preempt_disable_notrace();
213 data = this_cpu_read(cyc2ns.head);
214 tail = this_cpu_read(cyc2ns.tail);
215
216 if (likely(data == tail)) {
217 ns = data->cyc2ns_offset;
218 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
219 } else {
220 data->__count++;
221
222 barrier();
223
224 ns = data->cyc2ns_offset;
225 ns += mul_u64_u32_shr(cyc, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
226
227 barrier();
228
229 if (!--data->__count)
230 this_cpu_write(cyc2ns.tail, data);
231 }
232 preempt_enable_notrace();
233
234 return ns;
235}
236
237/* XXX surely we already have this someplace in the kernel?! */
238#define DIV_ROUND(n, d) (((n) + ((d) / 2)) / (d))
239
240static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu)
241{
242 unsigned long long tsc_now, ns_now;
243 struct cyc2ns_data *data;
244 unsigned long flags;
245
246 local_irq_save(flags);
247 sched_clock_idle_sleep_event();
248
249 if (!cpu_khz)
250 goto done;
251
252 data = cyc2ns_write_begin(cpu);
253
254 rdtscll(tsc_now);
255 ns_now = cycles_2_ns(tsc_now);
256
257 /*
258 * Compute a new multiplier as per the above comment and ensure our
259 * time function is continuous; see the comment near struct
260 * cyc2ns_data.
261 */
262 data->cyc2ns_mul = DIV_ROUND(NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR, cpu_khz);
263 data->cyc2ns_shift = CYC2NS_SCALE_FACTOR;
264 data->cyc2ns_offset = ns_now -
265 mul_u64_u32_shr(tsc_now, data->cyc2ns_mul, CYC2NS_SCALE_FACTOR);
266
267 cyc2ns_write_end(cpu, data);
268
269done:
270 sched_clock_idle_wakeup_event(0);
271 local_irq_restore(flags);
272}
273/*
274 * Scheduler clock - returns current time in nanosec units.
275 */
276u64 native_sched_clock(void)
277{
278 u64 tsc_now;
279
280 /*
281 * Fall back to jiffies if there's no TSC available:
282 * ( But note that we still use it if the TSC is marked
283 * unstable. We do this because unlike Time Of Day,
284 * the scheduler clock tolerates small errors and it's
285 * very important for it to be as fast as the platform
286 * can achieve it. )
287 */
288 if (!static_key_false(&__use_tsc)) {
289 /* No locking but a rare wrong value is not a big deal: */
290 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ);
291 }
292
293 /* read the Time Stamp Counter: */
294 rdtscll(tsc_now);
295
296 /* return the value in ns */
297 return cycles_2_ns(tsc_now);
298}
299
300/* We need to define a real function for sched_clock, to override the
301 weak default version */
302#ifdef CONFIG_PARAVIRT
303unsigned long long sched_clock(void)
304{
305 return paravirt_sched_clock();
306}
307#else
308unsigned long long
309sched_clock(void) __attribute__((alias("native_sched_clock")));
310#endif
311
312unsigned long long native_read_tsc(void)
313{
314 return __native_read_tsc();
315}
316EXPORT_SYMBOL(native_read_tsc);
317
318int check_tsc_unstable(void)
319{
320 return tsc_unstable;
321}
322EXPORT_SYMBOL_GPL(check_tsc_unstable);
323
324int check_tsc_disabled(void)
325{
326 return tsc_disabled;
327}
328EXPORT_SYMBOL_GPL(check_tsc_disabled);
329
330#ifdef CONFIG_X86_TSC
331int __init notsc_setup(char *str)
332{
333 pr_warn("Kernel compiled with CONFIG_X86_TSC, cannot disable TSC completely\n");
334 tsc_disabled = 1;
335 return 1;
336}
337#else
338/*
339 * disable flag for tsc. Takes effect by clearing the TSC cpu flag
340 * in cpu/common.c
341 */
342int __init notsc_setup(char *str)
343{
344 setup_clear_cpu_cap(X86_FEATURE_TSC);
345 return 1;
346}
347#endif
348
349__setup("notsc", notsc_setup);
350
351static int no_sched_irq_time;
352
353static int __init tsc_setup(char *str)
354{
355 if (!strcmp(str, "reliable"))
356 tsc_clocksource_reliable = 1;
357 if (!strncmp(str, "noirqtime", 9))
358 no_sched_irq_time = 1;
359 return 1;
360}
361
362__setup("tsc=", tsc_setup);
363
364#define MAX_RETRIES 5
365#define SMI_TRESHOLD 50000
366
367/*
368 * Read TSC and the reference counters. Take care of SMI disturbance
369 */
370static u64 tsc_read_refs(u64 *p, int hpet)
371{
372 u64 t1, t2;
373 int i;
374
375 for (i = 0; i < MAX_RETRIES; i++) {
376 t1 = get_cycles();
377 if (hpet)
378 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF;
379 else
380 *p = acpi_pm_read_early();
381 t2 = get_cycles();
382 if ((t2 - t1) < SMI_TRESHOLD)
383 return t2;
384 }
385 return ULLONG_MAX;
386}
387
388/*
389 * Calculate the TSC frequency from HPET reference
390 */
391static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2)
392{
393 u64 tmp;
394
395 if (hpet2 < hpet1)
396 hpet2 += 0x100000000ULL;
397 hpet2 -= hpet1;
398 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD));
399 do_div(tmp, 1000000);
400 do_div(deltatsc, tmp);
401
402 return (unsigned long) deltatsc;
403}
404
405/*
406 * Calculate the TSC frequency from PMTimer reference
407 */
408static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2)
409{
410 u64 tmp;
411
412 if (!pm1 && !pm2)
413 return ULONG_MAX;
414
415 if (pm2 < pm1)
416 pm2 += (u64)ACPI_PM_OVRRUN;
417 pm2 -= pm1;
418 tmp = pm2 * 1000000000LL;
419 do_div(tmp, PMTMR_TICKS_PER_SEC);
420 do_div(deltatsc, tmp);
421
422 return (unsigned long) deltatsc;
423}
424
425#define CAL_MS 10
426#define CAL_LATCH (PIT_TICK_RATE / (1000 / CAL_MS))
427#define CAL_PIT_LOOPS 1000
428
429#define CAL2_MS 50
430#define CAL2_LATCH (PIT_TICK_RATE / (1000 / CAL2_MS))
431#define CAL2_PIT_LOOPS 5000
432
433
434/*
435 * Try to calibrate the TSC against the Programmable
436 * Interrupt Timer and return the frequency of the TSC
437 * in kHz.
438 *
439 * Return ULONG_MAX on failure to calibrate.
440 */
441static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin)
442{
443 u64 tsc, t1, t2, delta;
444 unsigned long tscmin, tscmax;
445 int pitcnt;
446
447 /* Set the Gate high, disable speaker */
448 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
449
450 /*
451 * Setup CTC channel 2* for mode 0, (interrupt on terminal
452 * count mode), binary count. Set the latch register to 50ms
453 * (LSB then MSB) to begin countdown.
454 */
455 outb(0xb0, 0x43);
456 outb(latch & 0xff, 0x42);
457 outb(latch >> 8, 0x42);
458
459 tsc = t1 = t2 = get_cycles();
460
461 pitcnt = 0;
462 tscmax = 0;
463 tscmin = ULONG_MAX;
464 while ((inb(0x61) & 0x20) == 0) {
465 t2 = get_cycles();
466 delta = t2 - tsc;
467 tsc = t2;
468 if ((unsigned long) delta < tscmin)
469 tscmin = (unsigned int) delta;
470 if ((unsigned long) delta > tscmax)
471 tscmax = (unsigned int) delta;
472 pitcnt++;
473 }
474
475 /*
476 * Sanity checks:
477 *
478 * If we were not able to read the PIT more than loopmin
479 * times, then we have been hit by a massive SMI
480 *
481 * If the maximum is 10 times larger than the minimum,
482 * then we got hit by an SMI as well.
483 */
484 if (pitcnt < loopmin || tscmax > 10 * tscmin)
485 return ULONG_MAX;
486
487 /* Calculate the PIT value */
488 delta = t2 - t1;
489 do_div(delta, ms);
490 return delta;
491}
492
493/*
494 * This reads the current MSB of the PIT counter, and
495 * checks if we are running on sufficiently fast and
496 * non-virtualized hardware.
497 *
498 * Our expectations are:
499 *
500 * - the PIT is running at roughly 1.19MHz
501 *
502 * - each IO is going to take about 1us on real hardware,
503 * but we allow it to be much faster (by a factor of 10) or
504 * _slightly_ slower (ie we allow up to a 2us read+counter
505 * update - anything else implies a unacceptably slow CPU
506 * or PIT for the fast calibration to work.
507 *
508 * - with 256 PIT ticks to read the value, we have 214us to
509 * see the same MSB (and overhead like doing a single TSC
510 * read per MSB value etc).
511 *
512 * - We're doing 2 reads per loop (LSB, MSB), and we expect
513 * them each to take about a microsecond on real hardware.
514 * So we expect a count value of around 100. But we'll be
515 * generous, and accept anything over 50.
516 *
517 * - if the PIT is stuck, and we see *many* more reads, we
518 * return early (and the next caller of pit_expect_msb()
519 * then consider it a failure when they don't see the
520 * next expected value).
521 *
522 * These expectations mean that we know that we have seen the
523 * transition from one expected value to another with a fairly
524 * high accuracy, and we didn't miss any events. We can thus
525 * use the TSC value at the transitions to calculate a pretty
526 * good value for the TSC frequencty.
527 */
528static inline int pit_verify_msb(unsigned char val)
529{
530 /* Ignore LSB */
531 inb(0x42);
532 return inb(0x42) == val;
533}
534
535static inline int pit_expect_msb(unsigned char val, u64 *tscp, unsigned long *deltap)
536{
537 int count;
538 u64 tsc = 0, prev_tsc = 0;
539
540 for (count = 0; count < 50000; count++) {
541 if (!pit_verify_msb(val))
542 break;
543 prev_tsc = tsc;
544 tsc = get_cycles();
545 }
546 *deltap = get_cycles() - prev_tsc;
547 *tscp = tsc;
548
549 /*
550 * We require _some_ success, but the quality control
551 * will be based on the error terms on the TSC values.
552 */
553 return count > 5;
554}
555
556/*
557 * How many MSB values do we want to see? We aim for
558 * a maximum error rate of 500ppm (in practice the
559 * real error is much smaller), but refuse to spend
560 * more than 50ms on it.
561 */
562#define MAX_QUICK_PIT_MS 50
563#define MAX_QUICK_PIT_ITERATIONS (MAX_QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256)
564
565static unsigned long quick_pit_calibrate(void)
566{
567 int i;
568 u64 tsc, delta;
569 unsigned long d1, d2;
570
571 /* Set the Gate high, disable speaker */
572 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
573
574 /*
575 * Counter 2, mode 0 (one-shot), binary count
576 *
577 * NOTE! Mode 2 decrements by two (and then the
578 * output is flipped each time, giving the same
579 * final output frequency as a decrement-by-one),
580 * so mode 0 is much better when looking at the
581 * individual counts.
582 */
583 outb(0xb0, 0x43);
584
585 /* Start at 0xffff */
586 outb(0xff, 0x42);
587 outb(0xff, 0x42);
588
589 /*
590 * The PIT starts counting at the next edge, so we
591 * need to delay for a microsecond. The easiest way
592 * to do that is to just read back the 16-bit counter
593 * once from the PIT.
594 */
595 pit_verify_msb(0);
596
597 if (pit_expect_msb(0xff, &tsc, &d1)) {
598 for (i = 1; i <= MAX_QUICK_PIT_ITERATIONS; i++) {
599 if (!pit_expect_msb(0xff-i, &delta, &d2))
600 break;
601
602 /*
603 * Iterate until the error is less than 500 ppm
604 */
605 delta -= tsc;
606 if (d1+d2 >= delta >> 11)
607 continue;
608
609 /*
610 * Check the PIT one more time to verify that
611 * all TSC reads were stable wrt the PIT.
612 *
613 * This also guarantees serialization of the
614 * last cycle read ('d2') in pit_expect_msb.
615 */
616 if (!pit_verify_msb(0xfe - i))
617 break;
618 goto success;
619 }
620 }
621 pr_err("Fast TSC calibration failed\n");
622 return 0;
623
624success:
625 /*
626 * Ok, if we get here, then we've seen the
627 * MSB of the PIT decrement 'i' times, and the
628 * error has shrunk to less than 500 ppm.
629 *
630 * As a result, we can depend on there not being
631 * any odd delays anywhere, and the TSC reads are
632 * reliable (within the error).
633 *
634 * kHz = ticks / time-in-seconds / 1000;
635 * kHz = (t2 - t1) / (I * 256 / PIT_TICK_RATE) / 1000
636 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (I * 256 * 1000)
637 */
638 delta *= PIT_TICK_RATE;
639 do_div(delta, i*256*1000);
640 pr_info("Fast TSC calibration using PIT\n");
641 return delta;
642}
643
644/**
645 * native_calibrate_tsc - calibrate the tsc on boot
646 */
647unsigned long native_calibrate_tsc(void)
648{
649 u64 tsc1, tsc2, delta, ref1, ref2;
650 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX;
651 unsigned long flags, latch, ms, fast_calibrate;
652 int hpet = is_hpet_enabled(), i, loopmin;
653
654 /* Calibrate TSC using MSR for Intel Atom SoCs */
655 local_irq_save(flags);
656 fast_calibrate = try_msr_calibrate_tsc();
657 local_irq_restore(flags);
658 if (fast_calibrate)
659 return fast_calibrate;
660
661 local_irq_save(flags);
662 fast_calibrate = quick_pit_calibrate();
663 local_irq_restore(flags);
664 if (fast_calibrate)
665 return fast_calibrate;
666
667 /*
668 * Run 5 calibration loops to get the lowest frequency value
669 * (the best estimate). We use two different calibration modes
670 * here:
671 *
672 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and
673 * load a timeout of 50ms. We read the time right after we
674 * started the timer and wait until the PIT count down reaches
675 * zero. In each wait loop iteration we read the TSC and check
676 * the delta to the previous read. We keep track of the min
677 * and max values of that delta. The delta is mostly defined
678 * by the IO time of the PIT access, so we can detect when a
679 * SMI/SMM disturbance happened between the two reads. If the
680 * maximum time is significantly larger than the minimum time,
681 * then we discard the result and have another try.
682 *
683 * 2) Reference counter. If available we use the HPET or the
684 * PMTIMER as a reference to check the sanity of that value.
685 * We use separate TSC readouts and check inside of the
686 * reference read for a SMI/SMM disturbance. We dicard
687 * disturbed values here as well. We do that around the PIT
688 * calibration delay loop as we have to wait for a certain
689 * amount of time anyway.
690 */
691
692 /* Preset PIT loop values */
693 latch = CAL_LATCH;
694 ms = CAL_MS;
695 loopmin = CAL_PIT_LOOPS;
696
697 for (i = 0; i < 3; i++) {
698 unsigned long tsc_pit_khz;
699
700 /*
701 * Read the start value and the reference count of
702 * hpet/pmtimer when available. Then do the PIT
703 * calibration, which will take at least 50ms, and
704 * read the end value.
705 */
706 local_irq_save(flags);
707 tsc1 = tsc_read_refs(&ref1, hpet);
708 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin);
709 tsc2 = tsc_read_refs(&ref2, hpet);
710 local_irq_restore(flags);
711
712 /* Pick the lowest PIT TSC calibration so far */
713 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz);
714
715 /* hpet or pmtimer available ? */
716 if (ref1 == ref2)
717 continue;
718
719 /* Check, whether the sampling was disturbed by an SMI */
720 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX)
721 continue;
722
723 tsc2 = (tsc2 - tsc1) * 1000000LL;
724 if (hpet)
725 tsc2 = calc_hpet_ref(tsc2, ref1, ref2);
726 else
727 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2);
728
729 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2);
730
731 /* Check the reference deviation */
732 delta = ((u64) tsc_pit_min) * 100;
733 do_div(delta, tsc_ref_min);
734
735 /*
736 * If both calibration results are inside a 10% window
737 * then we can be sure, that the calibration
738 * succeeded. We break out of the loop right away. We
739 * use the reference value, as it is more precise.
740 */
741 if (delta >= 90 && delta <= 110) {
742 pr_info("PIT calibration matches %s. %d loops\n",
743 hpet ? "HPET" : "PMTIMER", i + 1);
744 return tsc_ref_min;
745 }
746
747 /*
748 * Check whether PIT failed more than once. This
749 * happens in virtualized environments. We need to
750 * give the virtual PC a slightly longer timeframe for
751 * the HPET/PMTIMER to make the result precise.
752 */
753 if (i == 1 && tsc_pit_min == ULONG_MAX) {
754 latch = CAL2_LATCH;
755 ms = CAL2_MS;
756 loopmin = CAL2_PIT_LOOPS;
757 }
758 }
759
760 /*
761 * Now check the results.
762 */
763 if (tsc_pit_min == ULONG_MAX) {
764 /* PIT gave no useful value */
765 pr_warn("Unable to calibrate against PIT\n");
766
767 /* We don't have an alternative source, disable TSC */
768 if (!hpet && !ref1 && !ref2) {
769 pr_notice("No reference (HPET/PMTIMER) available\n");
770 return 0;
771 }
772
773 /* The alternative source failed as well, disable TSC */
774 if (tsc_ref_min == ULONG_MAX) {
775 pr_warn("HPET/PMTIMER calibration failed\n");
776 return 0;
777 }
778
779 /* Use the alternative source */
780 pr_info("using %s reference calibration\n",
781 hpet ? "HPET" : "PMTIMER");
782
783 return tsc_ref_min;
784 }
785
786 /* We don't have an alternative source, use the PIT calibration value */
787 if (!hpet && !ref1 && !ref2) {
788 pr_info("Using PIT calibration value\n");
789 return tsc_pit_min;
790 }
791
792 /* The alternative source failed, use the PIT calibration value */
793 if (tsc_ref_min == ULONG_MAX) {
794 pr_warn("HPET/PMTIMER calibration failed. Using PIT calibration.\n");
795 return tsc_pit_min;
796 }
797
798 /*
799 * The calibration values differ too much. In doubt, we use
800 * the PIT value as we know that there are PMTIMERs around
801 * running at double speed. At least we let the user know:
802 */
803 pr_warn("PIT calibration deviates from %s: %lu %lu\n",
804 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min);
805 pr_info("Using PIT calibration value\n");
806 return tsc_pit_min;
807}
808
809int recalibrate_cpu_khz(void)
810{
811#ifndef CONFIG_SMP
812 unsigned long cpu_khz_old = cpu_khz;
813
814 if (cpu_has_tsc) {
815 tsc_khz = x86_platform.calibrate_tsc();
816 cpu_khz = tsc_khz;
817 cpu_data(0).loops_per_jiffy =
818 cpufreq_scale(cpu_data(0).loops_per_jiffy,
819 cpu_khz_old, cpu_khz);
820 return 0;
821 } else
822 return -ENODEV;
823#else
824 return -ENODEV;
825#endif
826}
827
828EXPORT_SYMBOL(recalibrate_cpu_khz);
829
830
831static unsigned long long cyc2ns_suspend;
832
833void tsc_save_sched_clock_state(void)
834{
835 if (!sched_clock_stable())
836 return;
837
838 cyc2ns_suspend = sched_clock();
839}
840
841/*
842 * Even on processors with invariant TSC, TSC gets reset in some the
843 * ACPI system sleep states. And in some systems BIOS seem to reinit TSC to
844 * arbitrary value (still sync'd across cpu's) during resume from such sleep
845 * states. To cope up with this, recompute the cyc2ns_offset for each cpu so
846 * that sched_clock() continues from the point where it was left off during
847 * suspend.
848 */
849void tsc_restore_sched_clock_state(void)
850{
851 unsigned long long offset;
852 unsigned long flags;
853 int cpu;
854
855 if (!sched_clock_stable())
856 return;
857
858 local_irq_save(flags);
859
860 /*
861 * We're comming out of suspend, there's no concurrency yet; don't
862 * bother being nice about the RCU stuff, just write to both
863 * data fields.
864 */
865
866 this_cpu_write(cyc2ns.data[0].cyc2ns_offset, 0);
867 this_cpu_write(cyc2ns.data[1].cyc2ns_offset, 0);
868
869 offset = cyc2ns_suspend - sched_clock();
870
871 for_each_possible_cpu(cpu) {
872 per_cpu(cyc2ns.data[0].cyc2ns_offset, cpu) = offset;
873 per_cpu(cyc2ns.data[1].cyc2ns_offset, cpu) = offset;
874 }
875
876 local_irq_restore(flags);
877}
878
879#ifdef CONFIG_CPU_FREQ
880
881/* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
882 * changes.
883 *
884 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
885 * not that important because current Opteron setups do not support
886 * scaling on SMP anyroads.
887 *
888 * Should fix up last_tsc too. Currently gettimeofday in the
889 * first tick after the change will be slightly wrong.
890 */
891
892static unsigned int ref_freq;
893static unsigned long loops_per_jiffy_ref;
894static unsigned long tsc_khz_ref;
895
896static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
897 void *data)
898{
899 struct cpufreq_freqs *freq = data;
900 unsigned long *lpj;
901
902 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC))
903 return 0;
904
905 lpj = &boot_cpu_data.loops_per_jiffy;
906#ifdef CONFIG_SMP
907 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
908 lpj = &cpu_data(freq->cpu).loops_per_jiffy;
909#endif
910
911 if (!ref_freq) {
912 ref_freq = freq->old;
913 loops_per_jiffy_ref = *lpj;
914 tsc_khz_ref = tsc_khz;
915 }
916 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
917 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new)) {
918 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new);
919
920 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
921 if (!(freq->flags & CPUFREQ_CONST_LOOPS))
922 mark_tsc_unstable("cpufreq changes");
923 }
924
925 set_cyc2ns_scale(tsc_khz, freq->cpu);
926
927 return 0;
928}
929
930static struct notifier_block time_cpufreq_notifier_block = {
931 .notifier_call = time_cpufreq_notifier
932};
933
934static int __init cpufreq_tsc(void)
935{
936 if (!cpu_has_tsc)
937 return 0;
938 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
939 return 0;
940 cpufreq_register_notifier(&time_cpufreq_notifier_block,
941 CPUFREQ_TRANSITION_NOTIFIER);
942 return 0;
943}
944
945core_initcall(cpufreq_tsc);
946
947#endif /* CONFIG_CPU_FREQ */
948
949/* clocksource code */
950
951static struct clocksource clocksource_tsc;
952
953/*
954 * We compare the TSC to the cycle_last value in the clocksource
955 * structure to avoid a nasty time-warp. This can be observed in a
956 * very small window right after one CPU updated cycle_last under
957 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which
958 * is smaller than the cycle_last reference value due to a TSC which
959 * is slighty behind. This delta is nowhere else observable, but in
960 * that case it results in a forward time jump in the range of hours
961 * due to the unsigned delta calculation of the time keeping core
962 * code, which is necessary to support wrapping clocksources like pm
963 * timer.
964 */
965static cycle_t read_tsc(struct clocksource *cs)
966{
967 cycle_t ret = (cycle_t)get_cycles();
968
969 return ret >= clocksource_tsc.cycle_last ?
970 ret : clocksource_tsc.cycle_last;
971}
972
973static void resume_tsc(struct clocksource *cs)
974{
975 if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
976 clocksource_tsc.cycle_last = 0;
977}
978
979static struct clocksource clocksource_tsc = {
980 .name = "tsc",
981 .rating = 300,
982 .read = read_tsc,
983 .resume = resume_tsc,
984 .mask = CLOCKSOURCE_MASK(64),
985 .flags = CLOCK_SOURCE_IS_CONTINUOUS |
986 CLOCK_SOURCE_MUST_VERIFY,
987 .archdata = { .vclock_mode = VCLOCK_TSC },
988};
989
990void mark_tsc_unstable(char *reason)
991{
992 if (!tsc_unstable) {
993 tsc_unstable = 1;
994 clear_sched_clock_stable();
995 disable_sched_clock_irqtime();
996 pr_info("Marking TSC unstable due to %s\n", reason);
997 /* Change only the rating, when not registered */
998 if (clocksource_tsc.mult)
999 clocksource_mark_unstable(&clocksource_tsc);
1000 else {
1001 clocksource_tsc.flags |= CLOCK_SOURCE_UNSTABLE;
1002 clocksource_tsc.rating = 0;
1003 }
1004 }
1005}
1006
1007EXPORT_SYMBOL_GPL(mark_tsc_unstable);
1008
1009static void __init check_system_tsc_reliable(void)
1010{
1011#ifdef CONFIG_MGEODE_LX
1012 /* RTSC counts during suspend */
1013#define RTSC_SUSP 0x100
1014 unsigned long res_low, res_high;
1015
1016 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high);
1017 /* Geode_LX - the OLPC CPU has a very reliable TSC */
1018 if (res_low & RTSC_SUSP)
1019 tsc_clocksource_reliable = 1;
1020#endif
1021 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE))
1022 tsc_clocksource_reliable = 1;
1023}
1024
1025/*
1026 * Make an educated guess if the TSC is trustworthy and synchronized
1027 * over all CPUs.
1028 */
1029int unsynchronized_tsc(void)
1030{
1031 if (!cpu_has_tsc || tsc_unstable)
1032 return 1;
1033
1034#ifdef CONFIG_SMP
1035 if (apic_is_clustered_box())
1036 return 1;
1037#endif
1038
1039 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
1040 return 0;
1041
1042 if (tsc_clocksource_reliable)
1043 return 0;
1044 /*
1045 * Intel systems are normally all synchronized.
1046 * Exceptions must mark TSC as unstable:
1047 */
1048 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) {
1049 /* assume multi socket systems are not synchronized: */
1050 if (num_possible_cpus() > 1)
1051 return 1;
1052 }
1053
1054 return 0;
1055}
1056
1057
1058static void tsc_refine_calibration_work(struct work_struct *work);
1059static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work);
1060/**
1061 * tsc_refine_calibration_work - Further refine tsc freq calibration
1062 * @work - ignored.
1063 *
1064 * This functions uses delayed work over a period of a
1065 * second to further refine the TSC freq value. Since this is
1066 * timer based, instead of loop based, we don't block the boot
1067 * process while this longer calibration is done.
1068 *
1069 * If there are any calibration anomalies (too many SMIs, etc),
1070 * or the refined calibration is off by 1% of the fast early
1071 * calibration, we throw out the new calibration and use the
1072 * early calibration.
1073 */
1074static void tsc_refine_calibration_work(struct work_struct *work)
1075{
1076 static u64 tsc_start = -1, ref_start;
1077 static int hpet;
1078 u64 tsc_stop, ref_stop, delta;
1079 unsigned long freq;
1080
1081 /* Don't bother refining TSC on unstable systems */
1082 if (check_tsc_unstable())
1083 goto out;
1084
1085 /*
1086 * Since the work is started early in boot, we may be
1087 * delayed the first time we expire. So set the workqueue
1088 * again once we know timers are working.
1089 */
1090 if (tsc_start == -1) {
1091 /*
1092 * Only set hpet once, to avoid mixing hardware
1093 * if the hpet becomes enabled later.
1094 */
1095 hpet = is_hpet_enabled();
1096 schedule_delayed_work(&tsc_irqwork, HZ);
1097 tsc_start = tsc_read_refs(&ref_start, hpet);
1098 return;
1099 }
1100
1101 tsc_stop = tsc_read_refs(&ref_stop, hpet);
1102
1103 /* hpet or pmtimer available ? */
1104 if (ref_start == ref_stop)
1105 goto out;
1106
1107 /* Check, whether the sampling was disturbed by an SMI */
1108 if (tsc_start == ULLONG_MAX || tsc_stop == ULLONG_MAX)
1109 goto out;
1110
1111 delta = tsc_stop - tsc_start;
1112 delta *= 1000000LL;
1113 if (hpet)
1114 freq = calc_hpet_ref(delta, ref_start, ref_stop);
1115 else
1116 freq = calc_pmtimer_ref(delta, ref_start, ref_stop);
1117
1118 /* Make sure we're within 1% */
1119 if (abs(tsc_khz - freq) > tsc_khz/100)
1120 goto out;
1121
1122 tsc_khz = freq;
1123 pr_info("Refined TSC clocksource calibration: %lu.%03lu MHz\n",
1124 (unsigned long)tsc_khz / 1000,
1125 (unsigned long)tsc_khz % 1000);
1126
1127out:
1128 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1129}
1130
1131
1132static int __init init_tsc_clocksource(void)
1133{
1134 if (!cpu_has_tsc || tsc_disabled > 0 || !tsc_khz)
1135 return 0;
1136
1137 if (tsc_clocksource_reliable)
1138 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY;
1139 /* lower the rating if we already know its unstable: */
1140 if (check_tsc_unstable()) {
1141 clocksource_tsc.rating = 0;
1142 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS;
1143 }
1144
1145 if (boot_cpu_has(X86_FEATURE_NONSTOP_TSC_S3))
1146 clocksource_tsc.flags |= CLOCK_SOURCE_SUSPEND_NONSTOP;
1147
1148 /*
1149 * Trust the results of the earlier calibration on systems
1150 * exporting a reliable TSC.
1151 */
1152 if (boot_cpu_has(X86_FEATURE_TSC_RELIABLE)) {
1153 clocksource_register_khz(&clocksource_tsc, tsc_khz);
1154 return 0;
1155 }
1156
1157 schedule_delayed_work(&tsc_irqwork, 0);
1158 return 0;
1159}
1160/*
1161 * We use device_initcall here, to ensure we run after the hpet
1162 * is fully initialized, which may occur at fs_initcall time.
1163 */
1164device_initcall(init_tsc_clocksource);
1165
1166void __init tsc_init(void)
1167{
1168 u64 lpj;
1169 int cpu;
1170
1171 x86_init.timers.tsc_pre_init();
1172
1173 if (!cpu_has_tsc)
1174 return;
1175
1176 tsc_khz = x86_platform.calibrate_tsc();
1177 cpu_khz = tsc_khz;
1178
1179 if (!tsc_khz) {
1180 mark_tsc_unstable("could not calculate TSC khz");
1181 return;
1182 }
1183
1184 pr_info("Detected %lu.%03lu MHz processor\n",
1185 (unsigned long)cpu_khz / 1000,
1186 (unsigned long)cpu_khz % 1000);
1187
1188 /*
1189 * Secondary CPUs do not run through tsc_init(), so set up
1190 * all the scale factors for all CPUs, assuming the same
1191 * speed as the bootup CPU. (cpufreq notifiers will fix this
1192 * up if their speed diverges)
1193 */
1194 for_each_possible_cpu(cpu) {
1195 cyc2ns_init(cpu);
1196 set_cyc2ns_scale(cpu_khz, cpu);
1197 }
1198
1199 if (tsc_disabled > 0)
1200 return;
1201
1202 /* now allow native_sched_clock() to use rdtsc */
1203
1204 tsc_disabled = 0;
1205 static_key_slow_inc(&__use_tsc);
1206
1207 if (!no_sched_irq_time)
1208 enable_sched_clock_irqtime();
1209
1210 lpj = ((u64)tsc_khz * 1000);
1211 do_div(lpj, HZ);
1212 lpj_fine = lpj;
1213
1214 use_tsc_delay();
1215
1216 if (unsynchronized_tsc())
1217 mark_tsc_unstable("TSCs unsynchronized");
1218
1219 check_system_tsc_reliable();
1220}
1221
1222#ifdef CONFIG_SMP
1223/*
1224 * If we have a constant TSC and are using the TSC for the delay loop,
1225 * we can skip clock calibration if another cpu in the same socket has already
1226 * been calibrated. This assumes that CONSTANT_TSC applies to all
1227 * cpus in the socket - this should be a safe assumption.
1228 */
1229unsigned long calibrate_delay_is_known(void)
1230{
1231 int i, cpu = smp_processor_id();
1232
1233 if (!tsc_disabled && !cpu_has(&cpu_data(cpu), X86_FEATURE_CONSTANT_TSC))
1234 return 0;
1235
1236 for_each_online_cpu(i)
1237 if (cpu_data(i).phys_proc_id == cpu_data(cpu).phys_proc_id)
1238 return cpu_data(i).loops_per_jiffy;
1239 return 0;
1240}
1241#endif