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1/*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#include <linux/init.h>
43#include <linux/smp.h>
44#include <linux/module.h>
45#include <linux/sched.h>
46#include <linux/percpu.h>
47#include <linux/bootmem.h>
48#include <linux/err.h>
49#include <linux/nmi.h>
50#include <linux/tboot.h>
51#include <linux/stackprotector.h>
52#include <linux/gfp.h>
53
54#include <asm/acpi.h>
55#include <asm/desc.h>
56#include <asm/nmi.h>
57#include <asm/irq.h>
58#include <asm/idle.h>
59#include <asm/trampoline.h>
60#include <asm/cpu.h>
61#include <asm/numa.h>
62#include <asm/pgtable.h>
63#include <asm/tlbflush.h>
64#include <asm/mtrr.h>
65#include <asm/mwait.h>
66#include <asm/apic.h>
67#include <asm/io_apic.h>
68#include <asm/setup.h>
69#include <asm/uv/uv.h>
70#include <linux/mc146818rtc.h>
71
72#include <asm/smpboot_hooks.h>
73#include <asm/i8259.h>
74
75/* State of each CPU */
76DEFINE_PER_CPU(int, cpu_state) = { 0 };
77
78/* Store all idle threads, this can be reused instead of creating
79* a new thread. Also avoids complicated thread destroy functionality
80* for idle threads.
81*/
82#ifdef CONFIG_HOTPLUG_CPU
83/*
84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is
85 * removed after init for !CONFIG_HOTPLUG_CPU.
86 */
87static DEFINE_PER_CPU(struct task_struct *, idle_thread_array);
88#define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x))
89#define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p))
90
91/*
92 * We need this for trampoline_base protection from concurrent accesses when
93 * off- and onlining cores wildly.
94 */
95static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex);
96
97void cpu_hotplug_driver_lock(void)
98{
99 mutex_lock(&x86_cpu_hotplug_driver_mutex);
100}
101
102void cpu_hotplug_driver_unlock(void)
103{
104 mutex_unlock(&x86_cpu_hotplug_driver_mutex);
105}
106
107ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; }
108ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; }
109#else
110static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ;
111#define get_idle_for_cpu(x) (idle_thread_array[(x)])
112#define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p))
113#endif
114
115/* Number of siblings per CPU package */
116int smp_num_siblings = 1;
117EXPORT_SYMBOL(smp_num_siblings);
118
119/* Last level cache ID of each logical CPU */
120DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID;
121
122/* representing HT siblings of each logical CPU */
123DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
124EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
125
126/* representing HT and core siblings of each logical CPU */
127DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
128EXPORT_PER_CPU_SYMBOL(cpu_core_map);
129
130DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map);
131
132/* Per CPU bogomips and other parameters */
133DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
134EXPORT_PER_CPU_SYMBOL(cpu_info);
135
136atomic_t init_deasserted;
137
138/*
139 * Report back to the Boot Processor.
140 * Running on AP.
141 */
142static void __cpuinit smp_callin(void)
143{
144 int cpuid, phys_id;
145 unsigned long timeout;
146
147 /*
148 * If waken up by an INIT in an 82489DX configuration
149 * we may get here before an INIT-deassert IPI reaches
150 * our local APIC. We have to wait for the IPI or we'll
151 * lock up on an APIC access.
152 */
153 if (apic->wait_for_init_deassert)
154 apic->wait_for_init_deassert(&init_deasserted);
155
156 /*
157 * (This works even if the APIC is not enabled.)
158 */
159 phys_id = read_apic_id();
160 cpuid = smp_processor_id();
161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
163 phys_id, cpuid);
164 }
165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
166
167 /*
168 * STARTUP IPIs are fragile beasts as they might sometimes
169 * trigger some glue motherboard logic. Complete APIC bus
170 * silence for 1 second, this overestimates the time the
171 * boot CPU is spending to send the up to 2 STARTUP IPIs
172 * by a factor of two. This should be enough.
173 */
174
175 /*
176 * Waiting 2s total for startup (udelay is not yet working)
177 */
178 timeout = jiffies + 2*HZ;
179 while (time_before(jiffies, timeout)) {
180 /*
181 * Has the boot CPU finished it's STARTUP sequence?
182 */
183 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
184 break;
185 cpu_relax();
186 }
187
188 if (!time_before(jiffies, timeout)) {
189 panic("%s: CPU%d started up but did not get a callout!\n",
190 __func__, cpuid);
191 }
192
193 /*
194 * the boot CPU has finished the init stage and is spinning
195 * on callin_map until we finish. We are free to set up this
196 * CPU, first the APIC. (this is probably redundant on most
197 * boards)
198 */
199
200 pr_debug("CALLIN, before setup_local_APIC().\n");
201 if (apic->smp_callin_clear_local_apic)
202 apic->smp_callin_clear_local_apic();
203 setup_local_APIC();
204 end_local_APIC_setup();
205
206 /*
207 * Need to setup vector mappings before we enable interrupts.
208 */
209 setup_vector_irq(smp_processor_id());
210 /*
211 * Get our bogomips.
212 *
213 * Need to enable IRQs because it can take longer and then
214 * the NMI watchdog might kill us.
215 */
216 local_irq_enable();
217 calibrate_delay();
218 local_irq_disable();
219 pr_debug("Stack at about %p\n", &cpuid);
220
221 /*
222 * Save our processor parameters
223 */
224 smp_store_cpu_info(cpuid);
225
226 /*
227 * This must be done before setting cpu_online_mask
228 * or calling notify_cpu_starting.
229 */
230 set_cpu_sibling_map(raw_smp_processor_id());
231 wmb();
232
233 notify_cpu_starting(cpuid);
234
235 /*
236 * Allow the master to continue.
237 */
238 cpumask_set_cpu(cpuid, cpu_callin_mask);
239}
240
241/*
242 * Activate a secondary processor.
243 */
244notrace static void __cpuinit start_secondary(void *unused)
245{
246 /*
247 * Don't put *anything* before cpu_init(), SMP booting is too
248 * fragile that we want to limit the things done here to the
249 * most necessary things.
250 */
251 cpu_init();
252 preempt_disable();
253 smp_callin();
254
255#ifdef CONFIG_X86_32
256 /* switch away from the initial page table */
257 load_cr3(swapper_pg_dir);
258 __flush_tlb_all();
259#endif
260
261 /* otherwise gcc will move up smp_processor_id before the cpu_init */
262 barrier();
263 /*
264 * Check TSC synchronization with the BP:
265 */
266 check_tsc_sync_target();
267
268 /*
269 * We need to hold call_lock, so there is no inconsistency
270 * between the time smp_call_function() determines number of
271 * IPI recipients, and the time when the determination is made
272 * for which cpus receive the IPI. Holding this
273 * lock helps us to not include this cpu in a currently in progress
274 * smp_call_function().
275 *
276 * We need to hold vector_lock so there the set of online cpus
277 * does not change while we are assigning vectors to cpus. Holding
278 * this lock ensures we don't half assign or remove an irq from a cpu.
279 */
280 ipi_call_lock();
281 lock_vector_lock();
282 set_cpu_online(smp_processor_id(), true);
283 unlock_vector_lock();
284 ipi_call_unlock();
285 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
286 x86_platform.nmi_init();
287
288 /*
289 * Wait until the cpu which brought this one up marked it
290 * online before enabling interrupts. If we don't do that then
291 * we can end up waking up the softirq thread before this cpu
292 * reached the active state, which makes the scheduler unhappy
293 * and schedule the softirq thread on the wrong cpu. This is
294 * only observable with forced threaded interrupts, but in
295 * theory it could also happen w/o them. It's just way harder
296 * to achieve.
297 */
298 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask))
299 cpu_relax();
300
301 /* enable local interrupts */
302 local_irq_enable();
303
304 /* to prevent fake stack check failure in clock setup */
305 boot_init_stack_canary();
306
307 x86_cpuinit.setup_percpu_clockev();
308
309 wmb();
310 cpu_idle();
311}
312
313/*
314 * The bootstrap kernel entry code has set these up. Save them for
315 * a given CPU
316 */
317
318void __cpuinit smp_store_cpu_info(int id)
319{
320 struct cpuinfo_x86 *c = &cpu_data(id);
321
322 *c = boot_cpu_data;
323 c->cpu_index = id;
324 if (id != 0)
325 identify_secondary_cpu(c);
326}
327
328static void __cpuinit link_thread_siblings(int cpu1, int cpu2)
329{
330 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2));
331 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1));
332 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2));
333 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1));
334 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2));
335 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1));
336}
337
338
339void __cpuinit set_cpu_sibling_map(int cpu)
340{
341 int i;
342 struct cpuinfo_x86 *c = &cpu_data(cpu);
343
344 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
345
346 if (smp_num_siblings > 1) {
347 for_each_cpu(i, cpu_sibling_setup_mask) {
348 struct cpuinfo_x86 *o = &cpu_data(i);
349
350 if (cpu_has(c, X86_FEATURE_TOPOEXT)) {
351 if (c->phys_proc_id == o->phys_proc_id &&
352 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) &&
353 c->compute_unit_id == o->compute_unit_id)
354 link_thread_siblings(cpu, i);
355 } else if (c->phys_proc_id == o->phys_proc_id &&
356 c->cpu_core_id == o->cpu_core_id) {
357 link_thread_siblings(cpu, i);
358 }
359 }
360 } else {
361 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
362 }
363
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365
366 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) {
367 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu));
368 c->booted_cores = 1;
369 return;
370 }
371
372 for_each_cpu(i, cpu_sibling_setup_mask) {
373 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID &&
374 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) {
375 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu));
376 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i));
377 }
378 if (c->phys_proc_id == cpu_data(i).phys_proc_id) {
379 cpumask_set_cpu(i, cpu_core_mask(cpu));
380 cpumask_set_cpu(cpu, cpu_core_mask(i));
381 /*
382 * Does this new cpu bringup a new core?
383 */
384 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
385 /*
386 * for each core in package, increment
387 * the booted_cores for this new cpu
388 */
389 if (cpumask_first(cpu_sibling_mask(i)) == i)
390 c->booted_cores++;
391 /*
392 * increment the core count for all
393 * the other cpus in this package
394 */
395 if (i != cpu)
396 cpu_data(i).booted_cores++;
397 } else if (i != cpu && !c->booted_cores)
398 c->booted_cores = cpu_data(i).booted_cores;
399 }
400 }
401}
402
403/* maps the cpu to the sched domain representing multi-core */
404const struct cpumask *cpu_coregroup_mask(int cpu)
405{
406 struct cpuinfo_x86 *c = &cpu_data(cpu);
407 /*
408 * For perf, we return last level cache shared map.
409 * And for power savings, we return cpu_core_map
410 */
411 if ((sched_mc_power_savings || sched_smt_power_savings) &&
412 !(cpu_has(c, X86_FEATURE_AMD_DCM)))
413 return cpu_core_mask(cpu);
414 else
415 return cpu_llc_shared_mask(cpu);
416}
417
418static void impress_friends(void)
419{
420 int cpu;
421 unsigned long bogosum = 0;
422 /*
423 * Allow the user to impress friends.
424 */
425 pr_debug("Before bogomips.\n");
426 for_each_possible_cpu(cpu)
427 if (cpumask_test_cpu(cpu, cpu_callout_mask))
428 bogosum += cpu_data(cpu).loops_per_jiffy;
429 printk(KERN_INFO
430 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1.\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 printk(KERN_CONT
456 "a previous APIC delivery may have failed\n");
457
458 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
459
460 timeout = 0;
461 do {
462 udelay(100);
463 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
464 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
465
466 switch (status) {
467 case APIC_ICR_RR_VALID:
468 status = apic_read(APIC_RRR);
469 printk(KERN_CONT "%08x\n", status);
470 break;
471 default:
472 printk(KERN_CONT "failed\n");
473 }
474 }
475}
476
477/*
478 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
479 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
480 * won't ... remember to clear down the APIC, etc later.
481 */
482int __cpuinit
483wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip)
484{
485 unsigned long send_status, accept_status = 0;
486 int maxlvt;
487
488 /* Target chip */
489 /* Boot on the stack */
490 /* Kick the second */
491 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid);
492
493 pr_debug("Waiting for send to finish...\n");
494 send_status = safe_apic_wait_icr_idle();
495
496 /*
497 * Give the other CPU some time to accept the IPI.
498 */
499 udelay(200);
500 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
501 maxlvt = lapic_get_maxlvt();
502 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
503 apic_write(APIC_ESR, 0);
504 accept_status = (apic_read(APIC_ESR) & 0xEF);
505 }
506 pr_debug("NMI sent.\n");
507
508 if (send_status)
509 printk(KERN_ERR "APIC never delivered???\n");
510 if (accept_status)
511 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
512
513 return (send_status | accept_status);
514}
515
516static int __cpuinit
517wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
518{
519 unsigned long send_status, accept_status = 0;
520 int maxlvt, num_starts, j;
521
522 maxlvt = lapic_get_maxlvt();
523
524 /*
525 * Be paranoid about clearing APIC errors.
526 */
527 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
528 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
529 apic_write(APIC_ESR, 0);
530 apic_read(APIC_ESR);
531 }
532
533 pr_debug("Asserting INIT.\n");
534
535 /*
536 * Turn INIT on target chip
537 */
538 /*
539 * Send IPI
540 */
541 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
542 phys_apicid);
543
544 pr_debug("Waiting for send to finish...\n");
545 send_status = safe_apic_wait_icr_idle();
546
547 mdelay(10);
548
549 pr_debug("Deasserting INIT.\n");
550
551 /* Target chip */
552 /* Send IPI */
553 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
554
555 pr_debug("Waiting for send to finish...\n");
556 send_status = safe_apic_wait_icr_idle();
557
558 mb();
559 atomic_set(&init_deasserted, 1);
560
561 /*
562 * Should we send STARTUP IPIs ?
563 *
564 * Determine this based on the APIC version.
565 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
566 */
567 if (APIC_INTEGRATED(apic_version[phys_apicid]))
568 num_starts = 2;
569 else
570 num_starts = 0;
571
572 /*
573 * Paravirt / VMI wants a startup IPI hook here to set up the
574 * target processor state.
575 */
576 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
577 stack_start);
578
579 /*
580 * Run STARTUP IPI loop.
581 */
582 pr_debug("#startup loops: %d.\n", num_starts);
583
584 for (j = 1; j <= num_starts; j++) {
585 pr_debug("Sending STARTUP #%d.\n", j);
586 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
587 apic_write(APIC_ESR, 0);
588 apic_read(APIC_ESR);
589 pr_debug("After apic_write.\n");
590
591 /*
592 * STARTUP IPI
593 */
594
595 /* Target chip */
596 /* Boot on the stack */
597 /* Kick the second */
598 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
599 phys_apicid);
600
601 /*
602 * Give the other CPU some time to accept the IPI.
603 */
604 udelay(300);
605
606 pr_debug("Startup point 1.\n");
607
608 pr_debug("Waiting for send to finish...\n");
609 send_status = safe_apic_wait_icr_idle();
610
611 /*
612 * Give the other CPU some time to accept the IPI.
613 */
614 udelay(200);
615 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
616 apic_write(APIC_ESR, 0);
617 accept_status = (apic_read(APIC_ESR) & 0xEF);
618 if (send_status || accept_status)
619 break;
620 }
621 pr_debug("After Startup.\n");
622
623 if (send_status)
624 printk(KERN_ERR "APIC never delivered???\n");
625 if (accept_status)
626 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
627
628 return (send_status | accept_status);
629}
630
631struct create_idle {
632 struct work_struct work;
633 struct task_struct *idle;
634 struct completion done;
635 int cpu;
636};
637
638static void __cpuinit do_fork_idle(struct work_struct *work)
639{
640 struct create_idle *c_idle =
641 container_of(work, struct create_idle, work);
642
643 c_idle->idle = fork_idle(c_idle->cpu);
644 complete(&c_idle->done);
645}
646
647/* reduce the number of lines printed when booting a large cpu count system */
648static void __cpuinit announce_cpu(int cpu, int apicid)
649{
650 static int current_node = -1;
651 int node = early_cpu_to_node(cpu);
652
653 if (system_state == SYSTEM_BOOTING) {
654 if (node != current_node) {
655 if (current_node > (-1))
656 pr_cont(" Ok.\n");
657 current_node = node;
658 pr_info("Booting Node %3d, Processors ", node);
659 }
660 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : "");
661 return;
662 } else
663 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
664 node, cpu, apicid);
665}
666
667/*
668 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
669 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
670 * Returns zero if CPU booted OK, else error code from
671 * ->wakeup_secondary_cpu.
672 */
673static int __cpuinit do_boot_cpu(int apicid, int cpu)
674{
675 unsigned long boot_error = 0;
676 unsigned long start_ip;
677 int timeout;
678 struct create_idle c_idle = {
679 .cpu = cpu,
680 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done),
681 };
682
683 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle);
684
685 alternatives_smp_switch(1);
686
687 c_idle.idle = get_idle_for_cpu(cpu);
688
689 /*
690 * We can't use kernel_thread since we must avoid to
691 * reschedule the child.
692 */
693 if (c_idle.idle) {
694 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *)
695 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1);
696 init_idle(c_idle.idle, cpu);
697 goto do_rest;
698 }
699
700 schedule_work(&c_idle.work);
701 wait_for_completion(&c_idle.done);
702
703 if (IS_ERR(c_idle.idle)) {
704 printk("failed fork for CPU %d\n", cpu);
705 destroy_work_on_stack(&c_idle.work);
706 return PTR_ERR(c_idle.idle);
707 }
708
709 set_idle_for_cpu(cpu, c_idle.idle);
710do_rest:
711 per_cpu(current_task, cpu) = c_idle.idle;
712#ifdef CONFIG_X86_32
713 /* Stack for startup_32 can be just as for start_secondary onwards */
714 irq_ctx_init(cpu);
715#else
716 clear_tsk_thread_flag(c_idle.idle, TIF_FORK);
717 initial_gs = per_cpu_offset(cpu);
718 per_cpu(kernel_stack, cpu) =
719 (unsigned long)task_stack_page(c_idle.idle) -
720 KERNEL_STACK_OFFSET + THREAD_SIZE;
721#endif
722 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
723 initial_code = (unsigned long)start_secondary;
724 stack_start = c_idle.idle->thread.sp;
725
726 /* start_ip had better be page-aligned! */
727 start_ip = trampoline_address();
728
729 /* So we see what's up */
730 announce_cpu(cpu, apicid);
731
732 /*
733 * This grunge runs the startup process for
734 * the targeted processor.
735 */
736
737 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip);
738
739 atomic_set(&init_deasserted, 0);
740
741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
742
743 pr_debug("Setting warm reset code and vector.\n");
744
745 smpboot_setup_warm_reset_vector(start_ip);
746 /*
747 * Be paranoid about clearing APIC errors.
748 */
749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
750 apic_write(APIC_ESR, 0);
751 apic_read(APIC_ESR);
752 }
753 }
754
755 /*
756 * Kick the secondary CPU. Use the method in the APIC driver
757 * if it's defined - or use an INIT boot APIC message otherwise:
758 */
759 if (apic->wakeup_secondary_cpu)
760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
761 else
762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
763
764 if (!boot_error) {
765 /*
766 * allow APs to start initializing.
767 */
768 pr_debug("Before Callout %d.\n", cpu);
769 cpumask_set_cpu(cpu, cpu_callout_mask);
770 pr_debug("After Callout %d.\n", cpu);
771
772 /*
773 * Wait 5s total for a response
774 */
775 for (timeout = 0; timeout < 50000; timeout++) {
776 if (cpumask_test_cpu(cpu, cpu_callin_mask))
777 break; /* It has booted */
778 udelay(100);
779 /*
780 * Allow other tasks to run while we wait for the
781 * AP to come online. This also gives a chance
782 * for the MTRR work(triggered by the AP coming online)
783 * to be completed in the stop machine context.
784 */
785 schedule();
786 }
787
788 if (cpumask_test_cpu(cpu, cpu_callin_mask))
789 pr_debug("CPU%d: has booted.\n", cpu);
790 else {
791 boot_error = 1;
792 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status)
793 == 0xA5A5A5A5)
794 /* trampoline started but...? */
795 pr_err("CPU%d: Stuck ??\n", cpu);
796 else
797 /* trampoline code not run */
798 pr_err("CPU%d: Not responding.\n", cpu);
799 if (apic->inquire_remote_apic)
800 apic->inquire_remote_apic(apicid);
801 }
802 }
803
804 if (boot_error) {
805 /* Try to put things back the way they were before ... */
806 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
807
808 /* was set by do_boot_cpu() */
809 cpumask_clear_cpu(cpu, cpu_callout_mask);
810
811 /* was set by cpu_init() */
812 cpumask_clear_cpu(cpu, cpu_initialized_mask);
813
814 set_cpu_present(cpu, false);
815 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID;
816 }
817
818 /* mark "stuck" area as not stuck */
819 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0;
820
821 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
822 /*
823 * Cleanup possible dangling ends...
824 */
825 smpboot_restore_warm_reset_vector();
826 }
827
828 destroy_work_on_stack(&c_idle.work);
829 return boot_error;
830}
831
832int __cpuinit native_cpu_up(unsigned int cpu)
833{
834 int apicid = apic->cpu_present_to_apicid(cpu);
835 unsigned long flags;
836 int err;
837
838 WARN_ON(irqs_disabled());
839
840 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
841
842 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid ||
843 !physid_isset(apicid, phys_cpu_present_map)) {
844 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu);
845 return -EINVAL;
846 }
847
848 /*
849 * Already booted CPU?
850 */
851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
852 pr_debug("do_boot_cpu %d Already started\n", cpu);
853 return -ENOSYS;
854 }
855
856 /*
857 * Save current MTRR state in case it was changed since early boot
858 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
859 */
860 mtrr_save_state();
861
862 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
863
864 err = do_boot_cpu(apicid, cpu);
865 if (err) {
866 pr_debug("do_boot_cpu failed %d\n", err);
867 return -EIO;
868 }
869
870 /*
871 * Check TSC synchronization with the AP (keep irqs disabled
872 * while doing so):
873 */
874 local_irq_save(flags);
875 check_tsc_sync_source(cpu);
876 local_irq_restore(flags);
877
878 while (!cpu_online(cpu)) {
879 cpu_relax();
880 touch_nmi_watchdog();
881 }
882
883 return 0;
884}
885
886/**
887 * arch_disable_smp_support() - disables SMP support for x86 at runtime
888 */
889void arch_disable_smp_support(void)
890{
891 disable_ioapic_support();
892}
893
894/*
895 * Fall back to non SMP mode after errors.
896 *
897 * RED-PEN audit/test this more. I bet there is more state messed up here.
898 */
899static __init void disable_smp(void)
900{
901 init_cpu_present(cpumask_of(0));
902 init_cpu_possible(cpumask_of(0));
903 smpboot_clear_io_apic_irqs();
904
905 if (smp_found_config)
906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
907 else
908 physid_set_mask_of_physid(0, &phys_cpu_present_map);
909 cpumask_set_cpu(0, cpu_sibling_mask(0));
910 cpumask_set_cpu(0, cpu_core_mask(0));
911}
912
913/*
914 * Various sanity checks.
915 */
916static int __init smp_sanity_check(unsigned max_cpus)
917{
918 preempt_disable();
919
920#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
921 if (def_to_bigsmp && nr_cpu_ids > 8) {
922 unsigned int cpu;
923 unsigned nr;
924
925 printk(KERN_WARNING
926 "More than 8 CPUs detected - skipping them.\n"
927 "Use CONFIG_X86_BIGSMP.\n");
928
929 nr = 0;
930 for_each_present_cpu(cpu) {
931 if (nr >= 8)
932 set_cpu_present(cpu, false);
933 nr++;
934 }
935
936 nr = 0;
937 for_each_possible_cpu(cpu) {
938 if (nr >= 8)
939 set_cpu_possible(cpu, false);
940 nr++;
941 }
942
943 nr_cpu_ids = 8;
944 }
945#endif
946
947 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
948 printk(KERN_WARNING
949 "weird, boot CPU (#%d) not listed by the BIOS.\n",
950 hard_smp_processor_id());
951
952 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
953 }
954
955 /*
956 * If we couldn't find an SMP configuration at boot time,
957 * get out of here now!
958 */
959 if (!smp_found_config && !acpi_lapic) {
960 preempt_enable();
961 printk(KERN_NOTICE "SMP motherboard not detected.\n");
962 disable_smp();
963 if (APIC_init_uniprocessor())
964 printk(KERN_NOTICE "Local APIC not detected."
965 " Using dummy APIC emulation.\n");
966 return -1;
967 }
968
969 /*
970 * Should not be necessary because the MP table should list the boot
971 * CPU too, but we do it for the sake of robustness anyway.
972 */
973 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
974 printk(KERN_NOTICE
975 "weird, boot CPU (#%d) not listed by the BIOS.\n",
976 boot_cpu_physical_apicid);
977 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
978 }
979 preempt_enable();
980
981 /*
982 * If we couldn't find a local APIC, then get out of here now!
983 */
984 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
985 !cpu_has_apic) {
986 if (!disable_apic) {
987 pr_err("BIOS bug, local APIC #%d not detected!...\n",
988 boot_cpu_physical_apicid);
989 pr_err("... forcing use of dummy APIC emulation."
990 "(tell your hw vendor)\n");
991 }
992 smpboot_clear_io_apic();
993 disable_ioapic_support();
994 return -1;
995 }
996
997 verify_local_APIC();
998
999 /*
1000 * If SMP should be disabled, then really disable it!
1001 */
1002 if (!max_cpus) {
1003 printk(KERN_INFO "SMP mode deactivated.\n");
1004 smpboot_clear_io_apic();
1005
1006 connect_bsp_APIC();
1007 setup_local_APIC();
1008 bsp_end_local_APIC_setup();
1009 return -1;
1010 }
1011
1012 return 0;
1013}
1014
1015static void __init smp_cpu_index_default(void)
1016{
1017 int i;
1018 struct cpuinfo_x86 *c;
1019
1020 for_each_possible_cpu(i) {
1021 c = &cpu_data(i);
1022 /* mark all to hotplug */
1023 c->cpu_index = nr_cpu_ids;
1024 }
1025}
1026
1027/*
1028 * Prepare for SMP bootup. The MP table or ACPI has been read
1029 * earlier. Just do some sanity checking here and enable APIC mode.
1030 */
1031void __init native_smp_prepare_cpus(unsigned int max_cpus)
1032{
1033 unsigned int i;
1034
1035 preempt_disable();
1036 smp_cpu_index_default();
1037
1038 /*
1039 * Setup boot CPU information
1040 */
1041 smp_store_cpu_info(0); /* Final full version of the data */
1042 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1043 mb();
1044
1045 current_thread_info()->cpu = 0; /* needed? */
1046 for_each_possible_cpu(i) {
1047 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1048 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1049 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1050 }
1051 set_cpu_sibling_map(0);
1052
1053
1054 if (smp_sanity_check(max_cpus) < 0) {
1055 printk(KERN_INFO "SMP disabled\n");
1056 disable_smp();
1057 goto out;
1058 }
1059
1060 default_setup_apic_routing();
1061
1062 preempt_disable();
1063 if (read_apic_id() != boot_cpu_physical_apicid) {
1064 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1065 read_apic_id(), boot_cpu_physical_apicid);
1066 /* Or can we switch back to PIC here? */
1067 }
1068 preempt_enable();
1069
1070 connect_bsp_APIC();
1071
1072 /*
1073 * Switch from PIC to APIC mode.
1074 */
1075 setup_local_APIC();
1076
1077 /*
1078 * Enable IO APIC before setting up error vector
1079 */
1080 if (!skip_ioapic_setup && nr_ioapics)
1081 enable_IO_APIC();
1082
1083 bsp_end_local_APIC_setup();
1084
1085 if (apic->setup_portio_remap)
1086 apic->setup_portio_remap();
1087
1088 smpboot_setup_io_apic();
1089 /*
1090 * Set up local APIC timer on boot CPU.
1091 */
1092
1093 printk(KERN_INFO "CPU%d: ", 0);
1094 print_cpu_info(&cpu_data(0));
1095 x86_init.timers.setup_percpu_clockev();
1096
1097 if (is_uv_system())
1098 uv_system_init();
1099
1100 set_mtrr_aps_delayed_init();
1101out:
1102 preempt_enable();
1103}
1104
1105void arch_disable_nonboot_cpus_begin(void)
1106{
1107 /*
1108 * Avoid the smp alternatives switch during the disable_nonboot_cpus().
1109 * In the suspend path, we will be back in the SMP mode shortly anyways.
1110 */
1111 skip_smp_alternatives = true;
1112}
1113
1114void arch_disable_nonboot_cpus_end(void)
1115{
1116 skip_smp_alternatives = false;
1117}
1118
1119void arch_enable_nonboot_cpus_begin(void)
1120{
1121 set_mtrr_aps_delayed_init();
1122}
1123
1124void arch_enable_nonboot_cpus_end(void)
1125{
1126 mtrr_aps_init();
1127}
1128
1129/*
1130 * Early setup to make printk work.
1131 */
1132void __init native_smp_prepare_boot_cpu(void)
1133{
1134 int me = smp_processor_id();
1135 switch_to_new_gdt(me);
1136 /* already set me in cpu_online_mask in boot_cpu_init() */
1137 cpumask_set_cpu(me, cpu_callout_mask);
1138 per_cpu(cpu_state, me) = CPU_ONLINE;
1139}
1140
1141void __init native_smp_cpus_done(unsigned int max_cpus)
1142{
1143 pr_debug("Boot done.\n");
1144
1145 impress_friends();
1146#ifdef CONFIG_X86_IO_APIC
1147 setup_ioapic_dest();
1148#endif
1149 mtrr_aps_init();
1150}
1151
1152static int __initdata setup_possible_cpus = -1;
1153static int __init _setup_possible_cpus(char *str)
1154{
1155 get_option(&str, &setup_possible_cpus);
1156 return 0;
1157}
1158early_param("possible_cpus", _setup_possible_cpus);
1159
1160
1161/*
1162 * cpu_possible_mask should be static, it cannot change as cpu's
1163 * are onlined, or offlined. The reason is per-cpu data-structures
1164 * are allocated by some modules at init time, and dont expect to
1165 * do this dynamically on cpu arrival/departure.
1166 * cpu_present_mask on the other hand can change dynamically.
1167 * In case when cpu_hotplug is not compiled, then we resort to current
1168 * behaviour, which is cpu_possible == cpu_present.
1169 * - Ashok Raj
1170 *
1171 * Three ways to find out the number of additional hotplug CPUs:
1172 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1173 * - The user can overwrite it with possible_cpus=NUM
1174 * - Otherwise don't reserve additional CPUs.
1175 * We do this because additional CPUs waste a lot of memory.
1176 * -AK
1177 */
1178__init void prefill_possible_map(void)
1179{
1180 int i, possible;
1181
1182 /* no processor from mptable or madt */
1183 if (!num_processors)
1184 num_processors = 1;
1185
1186 i = setup_max_cpus ?: 1;
1187 if (setup_possible_cpus == -1) {
1188 possible = num_processors;
1189#ifdef CONFIG_HOTPLUG_CPU
1190 if (setup_max_cpus)
1191 possible += disabled_cpus;
1192#else
1193 if (possible > i)
1194 possible = i;
1195#endif
1196 } else
1197 possible = setup_possible_cpus;
1198
1199 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1200
1201 /* nr_cpu_ids could be reduced via nr_cpus= */
1202 if (possible > nr_cpu_ids) {
1203 printk(KERN_WARNING
1204 "%d Processors exceeds NR_CPUS limit of %d\n",
1205 possible, nr_cpu_ids);
1206 possible = nr_cpu_ids;
1207 }
1208
1209#ifdef CONFIG_HOTPLUG_CPU
1210 if (!setup_max_cpus)
1211#endif
1212 if (possible > i) {
1213 printk(KERN_WARNING
1214 "%d Processors exceeds max_cpus limit of %u\n",
1215 possible, setup_max_cpus);
1216 possible = i;
1217 }
1218
1219 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n",
1220 possible, max_t(int, possible - num_processors, 0));
1221
1222 for (i = 0; i < possible; i++)
1223 set_cpu_possible(i, true);
1224 for (; i < NR_CPUS; i++)
1225 set_cpu_possible(i, false);
1226
1227 nr_cpu_ids = possible;
1228}
1229
1230#ifdef CONFIG_HOTPLUG_CPU
1231
1232static void remove_siblinginfo(int cpu)
1233{
1234 int sibling;
1235 struct cpuinfo_x86 *c = &cpu_data(cpu);
1236
1237 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1238 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1239 /*/
1240 * last thread sibling in this cpu core going down
1241 */
1242 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1243 cpu_data(sibling).booted_cores--;
1244 }
1245
1246 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1247 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1248 cpumask_clear(cpu_sibling_mask(cpu));
1249 cpumask_clear(cpu_core_mask(cpu));
1250 c->phys_proc_id = 0;
1251 c->cpu_core_id = 0;
1252 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1253}
1254
1255static void __ref remove_cpu_from_maps(int cpu)
1256{
1257 set_cpu_online(cpu, false);
1258 cpumask_clear_cpu(cpu, cpu_callout_mask);
1259 cpumask_clear_cpu(cpu, cpu_callin_mask);
1260 /* was set by cpu_init() */
1261 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1262 numa_remove_cpu(cpu);
1263}
1264
1265void cpu_disable_common(void)
1266{
1267 int cpu = smp_processor_id();
1268
1269 remove_siblinginfo(cpu);
1270
1271 /* It's now safe to remove this processor from the online map */
1272 lock_vector_lock();
1273 remove_cpu_from_maps(cpu);
1274 unlock_vector_lock();
1275 fixup_irqs();
1276}
1277
1278int native_cpu_disable(void)
1279{
1280 int cpu = smp_processor_id();
1281
1282 /*
1283 * Perhaps use cpufreq to drop frequency, but that could go
1284 * into generic code.
1285 *
1286 * We won't take down the boot processor on i386 due to some
1287 * interrupts only being able to be serviced by the BSP.
1288 * Especially so if we're not using an IOAPIC -zwane
1289 */
1290 if (cpu == 0)
1291 return -EBUSY;
1292
1293 clear_local_APIC();
1294
1295 cpu_disable_common();
1296 return 0;
1297}
1298
1299void native_cpu_die(unsigned int cpu)
1300{
1301 /* We don't do anything here: idle task is faking death itself. */
1302 unsigned int i;
1303
1304 for (i = 0; i < 10; i++) {
1305 /* They ack this in play_dead by setting CPU_DEAD */
1306 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1307 if (system_state == SYSTEM_RUNNING)
1308 pr_info("CPU %u is now offline\n", cpu);
1309
1310 if (1 == num_online_cpus())
1311 alternatives_smp_switch(0);
1312 return;
1313 }
1314 msleep(100);
1315 }
1316 pr_err("CPU %u didn't die...\n", cpu);
1317}
1318
1319void play_dead_common(void)
1320{
1321 idle_task_exit();
1322 reset_lazy_tlbstate();
1323 amd_e400_remove_cpu(raw_smp_processor_id());
1324
1325 mb();
1326 /* Ack it */
1327 __this_cpu_write(cpu_state, CPU_DEAD);
1328
1329 /*
1330 * With physical CPU hotplug, we should halt the cpu
1331 */
1332 local_irq_disable();
1333}
1334
1335/*
1336 * We need to flush the caches before going to sleep, lest we have
1337 * dirty data in our caches when we come back up.
1338 */
1339static inline void mwait_play_dead(void)
1340{
1341 unsigned int eax, ebx, ecx, edx;
1342 unsigned int highest_cstate = 0;
1343 unsigned int highest_subcstate = 0;
1344 int i;
1345 void *mwait_ptr;
1346 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info);
1347
1348 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c)))
1349 return;
1350 if (!this_cpu_has(X86_FEATURE_CLFLSH))
1351 return;
1352 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1353 return;
1354
1355 eax = CPUID_MWAIT_LEAF;
1356 ecx = 0;
1357 native_cpuid(&eax, &ebx, &ecx, &edx);
1358
1359 /*
1360 * eax will be 0 if EDX enumeration is not valid.
1361 * Initialized below to cstate, sub_cstate value when EDX is valid.
1362 */
1363 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1364 eax = 0;
1365 } else {
1366 edx >>= MWAIT_SUBSTATE_SIZE;
1367 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1368 if (edx & MWAIT_SUBSTATE_MASK) {
1369 highest_cstate = i;
1370 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1371 }
1372 }
1373 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1374 (highest_subcstate - 1);
1375 }
1376
1377 /*
1378 * This should be a memory location in a cache line which is
1379 * unlikely to be touched by other processors. The actual
1380 * content is immaterial as it is not actually modified in any way.
1381 */
1382 mwait_ptr = ¤t_thread_info()->flags;
1383
1384 wbinvd();
1385
1386 while (1) {
1387 /*
1388 * The CLFLUSH is a workaround for erratum AAI65 for
1389 * the Xeon 7400 series. It's not clear it is actually
1390 * needed, but it should be harmless in either case.
1391 * The WBINVD is insufficient due to the spurious-wakeup
1392 * case where we return around the loop.
1393 */
1394 clflush(mwait_ptr);
1395 __monitor(mwait_ptr, 0, 0);
1396 mb();
1397 __mwait(eax, 0);
1398 }
1399}
1400
1401static inline void hlt_play_dead(void)
1402{
1403 if (__this_cpu_read(cpu_info.x86) >= 4)
1404 wbinvd();
1405
1406 while (1) {
1407 native_halt();
1408 }
1409}
1410
1411void native_play_dead(void)
1412{
1413 play_dead_common();
1414 tboot_shutdown(TB_SHUTDOWN_WFS);
1415
1416 mwait_play_dead(); /* Only returns on failure */
1417 hlt_play_dead();
1418}
1419
1420#else /* ... !CONFIG_HOTPLUG_CPU */
1421int native_cpu_disable(void)
1422{
1423 return -ENOSYS;
1424}
1425
1426void native_cpu_die(unsigned int cpu)
1427{
1428 /* We said "no" in __cpu_disable */
1429 BUG();
1430}
1431
1432void native_play_dead(void)
1433{
1434 BUG();
1435}
1436
1437#endif
1 /*
2 * x86 SMP booting functions
3 *
4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
7 *
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
10 *
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
14 *
15 * This code is released under the GNU General Public License version 2 or
16 * later.
17 *
18 * Fixes
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
29 * from Jose Renau
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Martin J. Bligh : Added support for multi-quad systems
35 * Dave Jones : Report invalid combinations of Athlon CPUs.
36 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 * Andi Kleen : Converted to new state machine.
38 * Ashok Raj : CPU hotplug support
39 * Glauber Costa : i386 and x86_64 integration
40 */
41
42#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43
44#include <linux/init.h>
45#include <linux/smp.h>
46#include <linux/module.h>
47#include <linux/sched.h>
48#include <linux/percpu.h>
49#include <linux/bootmem.h>
50#include <linux/err.h>
51#include <linux/nmi.h>
52#include <linux/tboot.h>
53#include <linux/stackprotector.h>
54#include <linux/gfp.h>
55#include <linux/cpuidle.h>
56
57#include <asm/acpi.h>
58#include <asm/desc.h>
59#include <asm/nmi.h>
60#include <asm/irq.h>
61#include <asm/idle.h>
62#include <asm/realmode.h>
63#include <asm/cpu.h>
64#include <asm/numa.h>
65#include <asm/pgtable.h>
66#include <asm/tlbflush.h>
67#include <asm/mtrr.h>
68#include <asm/mwait.h>
69#include <asm/apic.h>
70#include <asm/io_apic.h>
71#include <asm/i387.h>
72#include <asm/fpu-internal.h>
73#include <asm/setup.h>
74#include <asm/uv/uv.h>
75#include <linux/mc146818rtc.h>
76#include <asm/smpboot_hooks.h>
77#include <asm/i8259.h>
78#include <asm/realmode.h>
79#include <asm/misc.h>
80
81/* State of each CPU */
82DEFINE_PER_CPU(int, cpu_state) = { 0 };
83
84/* Number of siblings per CPU package */
85int smp_num_siblings = 1;
86EXPORT_SYMBOL(smp_num_siblings);
87
88/* Last level cache ID of each logical CPU */
89DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID;
90
91/* representing HT siblings of each logical CPU */
92DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94
95/* representing HT and core siblings of each logical CPU */
96DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98
99DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
100
101/* Per CPU bogomips and other parameters */
102DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info);
103EXPORT_PER_CPU_SYMBOL(cpu_info);
104
105atomic_t init_deasserted;
106
107/*
108 * Report back to the Boot Processor during boot time or to the caller processor
109 * during CPU online.
110 */
111static void smp_callin(void)
112{
113 int cpuid, phys_id;
114 unsigned long timeout;
115
116 /*
117 * If waken up by an INIT in an 82489DX configuration
118 * we may get here before an INIT-deassert IPI reaches
119 * our local APIC. We have to wait for the IPI or we'll
120 * lock up on an APIC access.
121 *
122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI.
123 */
124 cpuid = smp_processor_id();
125 if (apic->wait_for_init_deassert && cpuid)
126 while (!atomic_read(&init_deasserted))
127 cpu_relax();
128
129 /*
130 * (This works even if the APIC is not enabled.)
131 */
132 phys_id = read_apic_id();
133 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) {
134 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__,
135 phys_id, cpuid);
136 }
137 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
138
139 /*
140 * STARTUP IPIs are fragile beasts as they might sometimes
141 * trigger some glue motherboard logic. Complete APIC bus
142 * silence for 1 second, this overestimates the time the
143 * boot CPU is spending to send the up to 2 STARTUP IPIs
144 * by a factor of two. This should be enough.
145 */
146
147 /*
148 * Waiting 2s total for startup (udelay is not yet working)
149 */
150 timeout = jiffies + 2*HZ;
151 while (time_before(jiffies, timeout)) {
152 /*
153 * Has the boot CPU finished it's STARTUP sequence?
154 */
155 if (cpumask_test_cpu(cpuid, cpu_callout_mask))
156 break;
157 cpu_relax();
158 }
159
160 if (!time_before(jiffies, timeout)) {
161 panic("%s: CPU%d started up but did not get a callout!\n",
162 __func__, cpuid);
163 }
164
165 /*
166 * the boot CPU has finished the init stage and is spinning
167 * on callin_map until we finish. We are free to set up this
168 * CPU, first the APIC. (this is probably redundant on most
169 * boards)
170 */
171
172 pr_debug("CALLIN, before setup_local_APIC()\n");
173 if (apic->smp_callin_clear_local_apic)
174 apic->smp_callin_clear_local_apic();
175 setup_local_APIC();
176 end_local_APIC_setup();
177
178 /*
179 * Need to setup vector mappings before we enable interrupts.
180 */
181 setup_vector_irq(smp_processor_id());
182
183 /*
184 * Save our processor parameters. Note: this information
185 * is needed for clock calibration.
186 */
187 smp_store_cpu_info(cpuid);
188
189 /*
190 * Get our bogomips.
191 * Update loops_per_jiffy in cpu_data. Previous call to
192 * smp_store_cpu_info() stored a value that is close but not as
193 * accurate as the value just calculated.
194 */
195 calibrate_delay();
196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
197 pr_debug("Stack at about %p\n", &cpuid);
198
199 /*
200 * This must be done before setting cpu_online_mask
201 * or calling notify_cpu_starting.
202 */
203 set_cpu_sibling_map(raw_smp_processor_id());
204 wmb();
205
206 notify_cpu_starting(cpuid);
207
208 /*
209 * Allow the master to continue.
210 */
211 cpumask_set_cpu(cpuid, cpu_callin_mask);
212}
213
214static int cpu0_logical_apicid;
215static int enable_start_cpu0;
216/*
217 * Activate a secondary processor.
218 */
219static void notrace start_secondary(void *unused)
220{
221 /*
222 * Don't put *anything* before cpu_init(), SMP booting is too
223 * fragile that we want to limit the things done here to the
224 * most necessary things.
225 */
226 cpu_init();
227 x86_cpuinit.early_percpu_clock_init();
228 preempt_disable();
229 smp_callin();
230
231 enable_start_cpu0 = 0;
232
233#ifdef CONFIG_X86_32
234 /* switch away from the initial page table */
235 load_cr3(swapper_pg_dir);
236 __flush_tlb_all();
237#endif
238
239 /* otherwise gcc will move up smp_processor_id before the cpu_init */
240 barrier();
241 /*
242 * Check TSC synchronization with the BP:
243 */
244 check_tsc_sync_target();
245
246 /*
247 * We need to hold vector_lock so there the set of online cpus
248 * does not change while we are assigning vectors to cpus. Holding
249 * this lock ensures we don't half assign or remove an irq from a cpu.
250 */
251 lock_vector_lock();
252 set_cpu_online(smp_processor_id(), true);
253 unlock_vector_lock();
254 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
255 x86_platform.nmi_init();
256
257 /* enable local interrupts */
258 local_irq_enable();
259
260 /* to prevent fake stack check failure in clock setup */
261 boot_init_stack_canary();
262
263 x86_cpuinit.setup_percpu_clockev();
264
265 wmb();
266 cpu_startup_entry(CPUHP_ONLINE);
267}
268
269void __init smp_store_boot_cpu_info(void)
270{
271 int id = 0; /* CPU 0 */
272 struct cpuinfo_x86 *c = &cpu_data(id);
273
274 *c = boot_cpu_data;
275 c->cpu_index = id;
276}
277
278/*
279 * The bootstrap kernel entry code has set these up. Save them for
280 * a given CPU
281 */
282void smp_store_cpu_info(int id)
283{
284 struct cpuinfo_x86 *c = &cpu_data(id);
285
286 *c = boot_cpu_data;
287 c->cpu_index = id;
288 /*
289 * During boot time, CPU0 has this setup already. Save the info when
290 * bringing up AP or offlined CPU0.
291 */
292 identify_secondary_cpu(c);
293}
294
295static bool
296topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
297{
298 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
299
300 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2),
301 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
302 "[node: %d != %d]. Ignoring dependency.\n",
303 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
304}
305
306#define link_mask(_m, c1, c2) \
307do { \
308 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \
309 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \
310} while (0)
311
312static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
313{
314 if (cpu_has_topoext) {
315 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
316
317 if (c->phys_proc_id == o->phys_proc_id &&
318 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) &&
319 c->compute_unit_id == o->compute_unit_id)
320 return topology_sane(c, o, "smt");
321
322 } else if (c->phys_proc_id == o->phys_proc_id &&
323 c->cpu_core_id == o->cpu_core_id) {
324 return topology_sane(c, o, "smt");
325 }
326
327 return false;
328}
329
330static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
331{
332 int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
333
334 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID &&
335 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2))
336 return topology_sane(c, o, "llc");
337
338 return false;
339}
340
341static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
342{
343 if (c->phys_proc_id == o->phys_proc_id) {
344 if (cpu_has(c, X86_FEATURE_AMD_DCM))
345 return true;
346
347 return topology_sane(c, o, "mc");
348 }
349 return false;
350}
351
352void set_cpu_sibling_map(int cpu)
353{
354 bool has_smt = smp_num_siblings > 1;
355 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
356 struct cpuinfo_x86 *c = &cpu_data(cpu);
357 struct cpuinfo_x86 *o;
358 int i;
359
360 cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
361
362 if (!has_mp) {
363 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
365 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
366 c->booted_cores = 1;
367 return;
368 }
369
370 for_each_cpu(i, cpu_sibling_setup_mask) {
371 o = &cpu_data(i);
372
373 if ((i == cpu) || (has_smt && match_smt(c, o)))
374 link_mask(sibling, cpu, i);
375
376 if ((i == cpu) || (has_mp && match_llc(c, o)))
377 link_mask(llc_shared, cpu, i);
378
379 }
380
381 /*
382 * This needs a separate iteration over the cpus because we rely on all
383 * cpu_sibling_mask links to be set-up.
384 */
385 for_each_cpu(i, cpu_sibling_setup_mask) {
386 o = &cpu_data(i);
387
388 if ((i == cpu) || (has_mp && match_mc(c, o))) {
389 link_mask(core, cpu, i);
390
391 /*
392 * Does this new cpu bringup a new core?
393 */
394 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) {
395 /*
396 * for each core in package, increment
397 * the booted_cores for this new cpu
398 */
399 if (cpumask_first(cpu_sibling_mask(i)) == i)
400 c->booted_cores++;
401 /*
402 * increment the core count for all
403 * the other cpus in this package
404 */
405 if (i != cpu)
406 cpu_data(i).booted_cores++;
407 } else if (i != cpu && !c->booted_cores)
408 c->booted_cores = cpu_data(i).booted_cores;
409 }
410 }
411}
412
413/* maps the cpu to the sched domain representing multi-core */
414const struct cpumask *cpu_coregroup_mask(int cpu)
415{
416 return cpu_llc_shared_mask(cpu);
417}
418
419static void impress_friends(void)
420{
421 int cpu;
422 unsigned long bogosum = 0;
423 /*
424 * Allow the user to impress friends.
425 */
426 pr_debug("Before bogomips\n");
427 for_each_possible_cpu(cpu)
428 if (cpumask_test_cpu(cpu, cpu_callout_mask))
429 bogosum += cpu_data(cpu).loops_per_jiffy;
430 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
431 num_online_cpus(),
432 bogosum/(500000/HZ),
433 (bogosum/(5000/HZ))%100);
434
435 pr_debug("Before bogocount - setting activated=1\n");
436}
437
438void __inquire_remote_apic(int apicid)
439{
440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
441 const char * const names[] = { "ID", "VERSION", "SPIV" };
442 int timeout;
443 u32 status;
444
445 pr_info("Inquiring remote APIC 0x%x...\n", apicid);
446
447 for (i = 0; i < ARRAY_SIZE(regs); i++) {
448 pr_info("... APIC 0x%x %s: ", apicid, names[i]);
449
450 /*
451 * Wait for idle.
452 */
453 status = safe_apic_wait_icr_idle();
454 if (status)
455 pr_cont("a previous APIC delivery may have failed\n");
456
457 apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
458
459 timeout = 0;
460 do {
461 udelay(100);
462 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
463 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
464
465 switch (status) {
466 case APIC_ICR_RR_VALID:
467 status = apic_read(APIC_RRR);
468 pr_cont("%08x\n", status);
469 break;
470 default:
471 pr_cont("failed\n");
472 }
473 }
474}
475
476/*
477 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
478 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
479 * won't ... remember to clear down the APIC, etc later.
480 */
481int
482wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
483{
484 unsigned long send_status, accept_status = 0;
485 int maxlvt;
486
487 /* Target chip */
488 /* Boot on the stack */
489 /* Kick the second */
490 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
491
492 pr_debug("Waiting for send to finish...\n");
493 send_status = safe_apic_wait_icr_idle();
494
495 /*
496 * Give the other CPU some time to accept the IPI.
497 */
498 udelay(200);
499 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
500 maxlvt = lapic_get_maxlvt();
501 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
502 apic_write(APIC_ESR, 0);
503 accept_status = (apic_read(APIC_ESR) & 0xEF);
504 }
505 pr_debug("NMI sent\n");
506
507 if (send_status)
508 pr_err("APIC never delivered???\n");
509 if (accept_status)
510 pr_err("APIC delivery error (%lx)\n", accept_status);
511
512 return (send_status | accept_status);
513}
514
515static int
516wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
517{
518 unsigned long send_status, accept_status = 0;
519 int maxlvt, num_starts, j;
520
521 maxlvt = lapic_get_maxlvt();
522
523 /*
524 * Be paranoid about clearing APIC errors.
525 */
526 if (APIC_INTEGRATED(apic_version[phys_apicid])) {
527 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
528 apic_write(APIC_ESR, 0);
529 apic_read(APIC_ESR);
530 }
531
532 pr_debug("Asserting INIT\n");
533
534 /*
535 * Turn INIT on target chip
536 */
537 /*
538 * Send IPI
539 */
540 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
541 phys_apicid);
542
543 pr_debug("Waiting for send to finish...\n");
544 send_status = safe_apic_wait_icr_idle();
545
546 mdelay(10);
547
548 pr_debug("Deasserting INIT\n");
549
550 /* Target chip */
551 /* Send IPI */
552 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
553
554 pr_debug("Waiting for send to finish...\n");
555 send_status = safe_apic_wait_icr_idle();
556
557 mb();
558 atomic_set(&init_deasserted, 1);
559
560 /*
561 * Should we send STARTUP IPIs ?
562 *
563 * Determine this based on the APIC version.
564 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
565 */
566 if (APIC_INTEGRATED(apic_version[phys_apicid]))
567 num_starts = 2;
568 else
569 num_starts = 0;
570
571 /*
572 * Paravirt / VMI wants a startup IPI hook here to set up the
573 * target processor state.
574 */
575 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary,
576 stack_start);
577
578 /*
579 * Run STARTUP IPI loop.
580 */
581 pr_debug("#startup loops: %d\n", num_starts);
582
583 for (j = 1; j <= num_starts; j++) {
584 pr_debug("Sending STARTUP #%d\n", j);
585 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
586 apic_write(APIC_ESR, 0);
587 apic_read(APIC_ESR);
588 pr_debug("After apic_write\n");
589
590 /*
591 * STARTUP IPI
592 */
593
594 /* Target chip */
595 /* Boot on the stack */
596 /* Kick the second */
597 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
598 phys_apicid);
599
600 /*
601 * Give the other CPU some time to accept the IPI.
602 */
603 udelay(300);
604
605 pr_debug("Startup point 1\n");
606
607 pr_debug("Waiting for send to finish...\n");
608 send_status = safe_apic_wait_icr_idle();
609
610 /*
611 * Give the other CPU some time to accept the IPI.
612 */
613 udelay(200);
614 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
615 apic_write(APIC_ESR, 0);
616 accept_status = (apic_read(APIC_ESR) & 0xEF);
617 if (send_status || accept_status)
618 break;
619 }
620 pr_debug("After Startup\n");
621
622 if (send_status)
623 pr_err("APIC never delivered???\n");
624 if (accept_status)
625 pr_err("APIC delivery error (%lx)\n", accept_status);
626
627 return (send_status | accept_status);
628}
629
630void smp_announce(void)
631{
632 int num_nodes = num_online_nodes();
633
634 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n",
635 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus());
636}
637
638/* reduce the number of lines printed when booting a large cpu count system */
639static void announce_cpu(int cpu, int apicid)
640{
641 static int current_node = -1;
642 int node = early_cpu_to_node(cpu);
643 static int width, node_width;
644
645 if (!width)
646 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
647
648 if (!node_width)
649 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
650
651 if (cpu == 1)
652 printk(KERN_INFO "x86: Booting SMP configuration:\n");
653
654 if (system_state == SYSTEM_BOOTING) {
655 if (node != current_node) {
656 if (current_node > (-1))
657 pr_cont("\n");
658 current_node = node;
659
660 printk(KERN_INFO ".... node %*s#%d, CPUs: ",
661 node_width - num_digits(node), " ", node);
662 }
663
664 /* Add padding for the BSP */
665 if (cpu == 1)
666 pr_cont("%*s", width + 1, " ");
667
668 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
669
670 } else
671 pr_info("Booting Node %d Processor %d APIC 0x%x\n",
672 node, cpu, apicid);
673}
674
675static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
676{
677 int cpu;
678
679 cpu = smp_processor_id();
680 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
681 return NMI_HANDLED;
682
683 return NMI_DONE;
684}
685
686/*
687 * Wake up AP by INIT, INIT, STARTUP sequence.
688 *
689 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
690 * boot-strap code which is not a desired behavior for waking up BSP. To
691 * void the boot-strap code, wake up CPU0 by NMI instead.
692 *
693 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
694 * (i.e. physically hot removed and then hot added), NMI won't wake it up.
695 * We'll change this code in the future to wake up hard offlined CPU0 if
696 * real platform and request are available.
697 */
698static int
699wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
700 int *cpu0_nmi_registered)
701{
702 int id;
703 int boot_error;
704
705 preempt_disable();
706
707 /*
708 * Wake up AP by INIT, INIT, STARTUP sequence.
709 */
710 if (cpu) {
711 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
712 goto out;
713 }
714
715 /*
716 * Wake up BSP by nmi.
717 *
718 * Register a NMI handler to help wake up CPU0.
719 */
720 boot_error = register_nmi_handler(NMI_LOCAL,
721 wakeup_cpu0_nmi, 0, "wake_cpu0");
722
723 if (!boot_error) {
724 enable_start_cpu0 = 1;
725 *cpu0_nmi_registered = 1;
726 if (apic->dest_logical == APIC_DEST_LOGICAL)
727 id = cpu0_logical_apicid;
728 else
729 id = apicid;
730 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
731 }
732
733out:
734 preempt_enable();
735
736 return boot_error;
737}
738
739/*
740 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
741 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
742 * Returns zero if CPU booted OK, else error code from
743 * ->wakeup_secondary_cpu.
744 */
745static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
746{
747 volatile u32 *trampoline_status =
748 (volatile u32 *) __va(real_mode_header->trampoline_status);
749 /* start_ip had better be page-aligned! */
750 unsigned long start_ip = real_mode_header->trampoline_start;
751
752 unsigned long boot_error = 0;
753 int timeout;
754 int cpu0_nmi_registered = 0;
755
756 /* Just in case we booted with a single CPU. */
757 alternatives_enable_smp();
758
759 idle->thread.sp = (unsigned long) (((struct pt_regs *)
760 (THREAD_SIZE + task_stack_page(idle))) - 1);
761 per_cpu(current_task, cpu) = idle;
762
763#ifdef CONFIG_X86_32
764 /* Stack for startup_32 can be just as for start_secondary onwards */
765 irq_ctx_init(cpu);
766#else
767 clear_tsk_thread_flag(idle, TIF_FORK);
768 initial_gs = per_cpu_offset(cpu);
769#endif
770 per_cpu(kernel_stack, cpu) =
771 (unsigned long)task_stack_page(idle) -
772 KERNEL_STACK_OFFSET + THREAD_SIZE;
773 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu);
774 initial_code = (unsigned long)start_secondary;
775 stack_start = idle->thread.sp;
776
777 /* So we see what's up */
778 announce_cpu(cpu, apicid);
779
780 /*
781 * This grunge runs the startup process for
782 * the targeted processor.
783 */
784
785 atomic_set(&init_deasserted, 0);
786
787 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
788
789 pr_debug("Setting warm reset code and vector.\n");
790
791 smpboot_setup_warm_reset_vector(start_ip);
792 /*
793 * Be paranoid about clearing APIC errors.
794 */
795 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) {
796 apic_write(APIC_ESR, 0);
797 apic_read(APIC_ESR);
798 }
799 }
800
801 /*
802 * Wake up a CPU in difference cases:
803 * - Use the method in the APIC driver if it's defined
804 * Otherwise,
805 * - Use an INIT boot APIC message for APs or NMI for BSP.
806 */
807 if (apic->wakeup_secondary_cpu)
808 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
809 else
810 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
811 &cpu0_nmi_registered);
812
813 if (!boot_error) {
814 /*
815 * allow APs to start initializing.
816 */
817 pr_debug("Before Callout %d\n", cpu);
818 cpumask_set_cpu(cpu, cpu_callout_mask);
819 pr_debug("After Callout %d\n", cpu);
820
821 /*
822 * Wait 5s total for a response
823 */
824 for (timeout = 0; timeout < 50000; timeout++) {
825 if (cpumask_test_cpu(cpu, cpu_callin_mask))
826 break; /* It has booted */
827 udelay(100);
828 /*
829 * Allow other tasks to run while we wait for the
830 * AP to come online. This also gives a chance
831 * for the MTRR work(triggered by the AP coming online)
832 * to be completed in the stop machine context.
833 */
834 schedule();
835 }
836
837 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
838 print_cpu_msr(&cpu_data(cpu));
839 pr_debug("CPU%d: has booted.\n", cpu);
840 } else {
841 boot_error = 1;
842 if (*trampoline_status == 0xA5A5A5A5)
843 /* trampoline started but...? */
844 pr_err("CPU%d: Stuck ??\n", cpu);
845 else
846 /* trampoline code not run */
847 pr_err("CPU%d: Not responding\n", cpu);
848 if (apic->inquire_remote_apic)
849 apic->inquire_remote_apic(apicid);
850 }
851 }
852
853 if (boot_error) {
854 /* Try to put things back the way they were before ... */
855 numa_remove_cpu(cpu); /* was set by numa_add_cpu */
856
857 /* was set by do_boot_cpu() */
858 cpumask_clear_cpu(cpu, cpu_callout_mask);
859
860 /* was set by cpu_init() */
861 cpumask_clear_cpu(cpu, cpu_initialized_mask);
862 }
863
864 /* mark "stuck" area as not stuck */
865 *trampoline_status = 0;
866
867 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) {
868 /*
869 * Cleanup possible dangling ends...
870 */
871 smpboot_restore_warm_reset_vector();
872 }
873 /*
874 * Clean up the nmi handler. Do this after the callin and callout sync
875 * to avoid impact of possible long unregister time.
876 */
877 if (cpu0_nmi_registered)
878 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
879
880 return boot_error;
881}
882
883int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
884{
885 int apicid = apic->cpu_present_to_apicid(cpu);
886 unsigned long flags;
887 int err;
888
889 WARN_ON(irqs_disabled());
890
891 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu);
892
893 if (apicid == BAD_APICID ||
894 !physid_isset(apicid, phys_cpu_present_map) ||
895 !apic->apic_id_valid(apicid)) {
896 pr_err("%s: bad cpu %d\n", __func__, cpu);
897 return -EINVAL;
898 }
899
900 /*
901 * Already booted CPU?
902 */
903 if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
904 pr_debug("do_boot_cpu %d Already started\n", cpu);
905 return -ENOSYS;
906 }
907
908 /*
909 * Save current MTRR state in case it was changed since early boot
910 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
911 */
912 mtrr_save_state();
913
914 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
915
916 /* the FPU context is blank, nobody can own it */
917 __cpu_disable_lazy_restore(cpu);
918
919 err = do_boot_cpu(apicid, cpu, tidle);
920 if (err) {
921 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
922 return -EIO;
923 }
924
925 /*
926 * Check TSC synchronization with the AP (keep irqs disabled
927 * while doing so):
928 */
929 local_irq_save(flags);
930 check_tsc_sync_source(cpu);
931 local_irq_restore(flags);
932
933 while (!cpu_online(cpu)) {
934 cpu_relax();
935 touch_nmi_watchdog();
936 }
937
938 return 0;
939}
940
941/**
942 * arch_disable_smp_support() - disables SMP support for x86 at runtime
943 */
944void arch_disable_smp_support(void)
945{
946 disable_ioapic_support();
947}
948
949/*
950 * Fall back to non SMP mode after errors.
951 *
952 * RED-PEN audit/test this more. I bet there is more state messed up here.
953 */
954static __init void disable_smp(void)
955{
956 init_cpu_present(cpumask_of(0));
957 init_cpu_possible(cpumask_of(0));
958 smpboot_clear_io_apic_irqs();
959
960 if (smp_found_config)
961 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
962 else
963 physid_set_mask_of_physid(0, &phys_cpu_present_map);
964 cpumask_set_cpu(0, cpu_sibling_mask(0));
965 cpumask_set_cpu(0, cpu_core_mask(0));
966}
967
968/*
969 * Various sanity checks.
970 */
971static int __init smp_sanity_check(unsigned max_cpus)
972{
973 preempt_disable();
974
975#if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
976 if (def_to_bigsmp && nr_cpu_ids > 8) {
977 unsigned int cpu;
978 unsigned nr;
979
980 pr_warn("More than 8 CPUs detected - skipping them\n"
981 "Use CONFIG_X86_BIGSMP\n");
982
983 nr = 0;
984 for_each_present_cpu(cpu) {
985 if (nr >= 8)
986 set_cpu_present(cpu, false);
987 nr++;
988 }
989
990 nr = 0;
991 for_each_possible_cpu(cpu) {
992 if (nr >= 8)
993 set_cpu_possible(cpu, false);
994 nr++;
995 }
996
997 nr_cpu_ids = 8;
998 }
999#endif
1000
1001 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1002 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1003 hard_smp_processor_id());
1004
1005 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1006 }
1007
1008 /*
1009 * If we couldn't find an SMP configuration at boot time,
1010 * get out of here now!
1011 */
1012 if (!smp_found_config && !acpi_lapic) {
1013 preempt_enable();
1014 pr_notice("SMP motherboard not detected\n");
1015 disable_smp();
1016 if (APIC_init_uniprocessor())
1017 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n");
1018 return -1;
1019 }
1020
1021 /*
1022 * Should not be necessary because the MP table should list the boot
1023 * CPU too, but we do it for the sake of robustness anyway.
1024 */
1025 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1026 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1027 boot_cpu_physical_apicid);
1028 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1029 }
1030 preempt_enable();
1031
1032 /*
1033 * If we couldn't find a local APIC, then get out of here now!
1034 */
1035 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) &&
1036 !cpu_has_apic) {
1037 if (!disable_apic) {
1038 pr_err("BIOS bug, local APIC #%d not detected!...\n",
1039 boot_cpu_physical_apicid);
1040 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
1041 }
1042 smpboot_clear_io_apic();
1043 disable_ioapic_support();
1044 return -1;
1045 }
1046
1047 verify_local_APIC();
1048
1049 /*
1050 * If SMP should be disabled, then really disable it!
1051 */
1052 if (!max_cpus) {
1053 pr_info("SMP mode deactivated\n");
1054 smpboot_clear_io_apic();
1055
1056 connect_bsp_APIC();
1057 setup_local_APIC();
1058 bsp_end_local_APIC_setup();
1059 return -1;
1060 }
1061
1062 return 0;
1063}
1064
1065static void __init smp_cpu_index_default(void)
1066{
1067 int i;
1068 struct cpuinfo_x86 *c;
1069
1070 for_each_possible_cpu(i) {
1071 c = &cpu_data(i);
1072 /* mark all to hotplug */
1073 c->cpu_index = nr_cpu_ids;
1074 }
1075}
1076
1077/*
1078 * Prepare for SMP bootup. The MP table or ACPI has been read
1079 * earlier. Just do some sanity checking here and enable APIC mode.
1080 */
1081void __init native_smp_prepare_cpus(unsigned int max_cpus)
1082{
1083 unsigned int i;
1084
1085 preempt_disable();
1086 smp_cpu_index_default();
1087
1088 /*
1089 * Setup boot CPU information
1090 */
1091 smp_store_boot_cpu_info(); /* Final full version of the data */
1092 cpumask_copy(cpu_callin_mask, cpumask_of(0));
1093 mb();
1094
1095 current_thread_info()->cpu = 0; /* needed? */
1096 for_each_possible_cpu(i) {
1097 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1098 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1099 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1100 }
1101 set_cpu_sibling_map(0);
1102
1103
1104 if (smp_sanity_check(max_cpus) < 0) {
1105 pr_info("SMP disabled\n");
1106 disable_smp();
1107 goto out;
1108 }
1109
1110 default_setup_apic_routing();
1111
1112 preempt_disable();
1113 if (read_apic_id() != boot_cpu_physical_apicid) {
1114 panic("Boot APIC ID in local APIC unexpected (%d vs %d)",
1115 read_apic_id(), boot_cpu_physical_apicid);
1116 /* Or can we switch back to PIC here? */
1117 }
1118 preempt_enable();
1119
1120 connect_bsp_APIC();
1121
1122 /*
1123 * Switch from PIC to APIC mode.
1124 */
1125 setup_local_APIC();
1126
1127 if (x2apic_mode)
1128 cpu0_logical_apicid = apic_read(APIC_LDR);
1129 else
1130 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1131
1132 /*
1133 * Enable IO APIC before setting up error vector
1134 */
1135 if (!skip_ioapic_setup && nr_ioapics)
1136 enable_IO_APIC();
1137
1138 bsp_end_local_APIC_setup();
1139
1140 if (apic->setup_portio_remap)
1141 apic->setup_portio_remap();
1142
1143 smpboot_setup_io_apic();
1144 /*
1145 * Set up local APIC timer on boot CPU.
1146 */
1147
1148 pr_info("CPU%d: ", 0);
1149 print_cpu_info(&cpu_data(0));
1150 x86_init.timers.setup_percpu_clockev();
1151
1152 if (is_uv_system())
1153 uv_system_init();
1154
1155 set_mtrr_aps_delayed_init();
1156out:
1157 preempt_enable();
1158}
1159
1160void arch_enable_nonboot_cpus_begin(void)
1161{
1162 set_mtrr_aps_delayed_init();
1163}
1164
1165void arch_enable_nonboot_cpus_end(void)
1166{
1167 mtrr_aps_init();
1168}
1169
1170/*
1171 * Early setup to make printk work.
1172 */
1173void __init native_smp_prepare_boot_cpu(void)
1174{
1175 int me = smp_processor_id();
1176 switch_to_new_gdt(me);
1177 /* already set me in cpu_online_mask in boot_cpu_init() */
1178 cpumask_set_cpu(me, cpu_callout_mask);
1179 per_cpu(cpu_state, me) = CPU_ONLINE;
1180}
1181
1182void __init native_smp_cpus_done(unsigned int max_cpus)
1183{
1184 pr_debug("Boot done\n");
1185
1186 nmi_selftest();
1187 impress_friends();
1188#ifdef CONFIG_X86_IO_APIC
1189 setup_ioapic_dest();
1190#endif
1191 mtrr_aps_init();
1192}
1193
1194static int __initdata setup_possible_cpus = -1;
1195static int __init _setup_possible_cpus(char *str)
1196{
1197 get_option(&str, &setup_possible_cpus);
1198 return 0;
1199}
1200early_param("possible_cpus", _setup_possible_cpus);
1201
1202
1203/*
1204 * cpu_possible_mask should be static, it cannot change as cpu's
1205 * are onlined, or offlined. The reason is per-cpu data-structures
1206 * are allocated by some modules at init time, and dont expect to
1207 * do this dynamically on cpu arrival/departure.
1208 * cpu_present_mask on the other hand can change dynamically.
1209 * In case when cpu_hotplug is not compiled, then we resort to current
1210 * behaviour, which is cpu_possible == cpu_present.
1211 * - Ashok Raj
1212 *
1213 * Three ways to find out the number of additional hotplug CPUs:
1214 * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1215 * - The user can overwrite it with possible_cpus=NUM
1216 * - Otherwise don't reserve additional CPUs.
1217 * We do this because additional CPUs waste a lot of memory.
1218 * -AK
1219 */
1220__init void prefill_possible_map(void)
1221{
1222 int i, possible;
1223
1224 /* no processor from mptable or madt */
1225 if (!num_processors)
1226 num_processors = 1;
1227
1228 i = setup_max_cpus ?: 1;
1229 if (setup_possible_cpus == -1) {
1230 possible = num_processors;
1231#ifdef CONFIG_HOTPLUG_CPU
1232 if (setup_max_cpus)
1233 possible += disabled_cpus;
1234#else
1235 if (possible > i)
1236 possible = i;
1237#endif
1238 } else
1239 possible = setup_possible_cpus;
1240
1241 total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1242
1243 /* nr_cpu_ids could be reduced via nr_cpus= */
1244 if (possible > nr_cpu_ids) {
1245 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n",
1246 possible, nr_cpu_ids);
1247 possible = nr_cpu_ids;
1248 }
1249
1250#ifdef CONFIG_HOTPLUG_CPU
1251 if (!setup_max_cpus)
1252#endif
1253 if (possible > i) {
1254 pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1255 possible, setup_max_cpus);
1256 possible = i;
1257 }
1258
1259 pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1260 possible, max_t(int, possible - num_processors, 0));
1261
1262 for (i = 0; i < possible; i++)
1263 set_cpu_possible(i, true);
1264 for (; i < NR_CPUS; i++)
1265 set_cpu_possible(i, false);
1266
1267 nr_cpu_ids = possible;
1268}
1269
1270#ifdef CONFIG_HOTPLUG_CPU
1271
1272static void remove_siblinginfo(int cpu)
1273{
1274 int sibling;
1275 struct cpuinfo_x86 *c = &cpu_data(cpu);
1276
1277 for_each_cpu(sibling, cpu_core_mask(cpu)) {
1278 cpumask_clear_cpu(cpu, cpu_core_mask(sibling));
1279 /*/
1280 * last thread sibling in this cpu core going down
1281 */
1282 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1)
1283 cpu_data(sibling).booted_cores--;
1284 }
1285
1286 for_each_cpu(sibling, cpu_sibling_mask(cpu))
1287 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling));
1288 cpumask_clear(cpu_sibling_mask(cpu));
1289 cpumask_clear(cpu_core_mask(cpu));
1290 c->phys_proc_id = 0;
1291 c->cpu_core_id = 0;
1292 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1293}
1294
1295static void __ref remove_cpu_from_maps(int cpu)
1296{
1297 set_cpu_online(cpu, false);
1298 cpumask_clear_cpu(cpu, cpu_callout_mask);
1299 cpumask_clear_cpu(cpu, cpu_callin_mask);
1300 /* was set by cpu_init() */
1301 cpumask_clear_cpu(cpu, cpu_initialized_mask);
1302 numa_remove_cpu(cpu);
1303}
1304
1305void cpu_disable_common(void)
1306{
1307 int cpu = smp_processor_id();
1308
1309 remove_siblinginfo(cpu);
1310
1311 /* It's now safe to remove this processor from the online map */
1312 lock_vector_lock();
1313 remove_cpu_from_maps(cpu);
1314 unlock_vector_lock();
1315 fixup_irqs();
1316}
1317
1318int native_cpu_disable(void)
1319{
1320 int ret;
1321
1322 ret = check_irq_vectors_for_cpu_disable();
1323 if (ret)
1324 return ret;
1325
1326 clear_local_APIC();
1327
1328 cpu_disable_common();
1329 return 0;
1330}
1331
1332void native_cpu_die(unsigned int cpu)
1333{
1334 /* We don't do anything here: idle task is faking death itself. */
1335 unsigned int i;
1336
1337 for (i = 0; i < 10; i++) {
1338 /* They ack this in play_dead by setting CPU_DEAD */
1339 if (per_cpu(cpu_state, cpu) == CPU_DEAD) {
1340 if (system_state == SYSTEM_RUNNING)
1341 pr_info("CPU %u is now offline\n", cpu);
1342 return;
1343 }
1344 msleep(100);
1345 }
1346 pr_err("CPU %u didn't die...\n", cpu);
1347}
1348
1349void play_dead_common(void)
1350{
1351 idle_task_exit();
1352 reset_lazy_tlbstate();
1353 amd_e400_remove_cpu(raw_smp_processor_id());
1354
1355 mb();
1356 /* Ack it */
1357 __this_cpu_write(cpu_state, CPU_DEAD);
1358
1359 /*
1360 * With physical CPU hotplug, we should halt the cpu
1361 */
1362 local_irq_disable();
1363}
1364
1365static bool wakeup_cpu0(void)
1366{
1367 if (smp_processor_id() == 0 && enable_start_cpu0)
1368 return true;
1369
1370 return false;
1371}
1372
1373/*
1374 * We need to flush the caches before going to sleep, lest we have
1375 * dirty data in our caches when we come back up.
1376 */
1377static inline void mwait_play_dead(void)
1378{
1379 unsigned int eax, ebx, ecx, edx;
1380 unsigned int highest_cstate = 0;
1381 unsigned int highest_subcstate = 0;
1382 void *mwait_ptr;
1383 int i;
1384
1385 if (!this_cpu_has(X86_FEATURE_MWAIT))
1386 return;
1387 if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1388 return;
1389 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1390 return;
1391
1392 eax = CPUID_MWAIT_LEAF;
1393 ecx = 0;
1394 native_cpuid(&eax, &ebx, &ecx, &edx);
1395
1396 /*
1397 * eax will be 0 if EDX enumeration is not valid.
1398 * Initialized below to cstate, sub_cstate value when EDX is valid.
1399 */
1400 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1401 eax = 0;
1402 } else {
1403 edx >>= MWAIT_SUBSTATE_SIZE;
1404 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1405 if (edx & MWAIT_SUBSTATE_MASK) {
1406 highest_cstate = i;
1407 highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1408 }
1409 }
1410 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1411 (highest_subcstate - 1);
1412 }
1413
1414 /*
1415 * This should be a memory location in a cache line which is
1416 * unlikely to be touched by other processors. The actual
1417 * content is immaterial as it is not actually modified in any way.
1418 */
1419 mwait_ptr = ¤t_thread_info()->flags;
1420
1421 wbinvd();
1422
1423 while (1) {
1424 /*
1425 * The CLFLUSH is a workaround for erratum AAI65 for
1426 * the Xeon 7400 series. It's not clear it is actually
1427 * needed, but it should be harmless in either case.
1428 * The WBINVD is insufficient due to the spurious-wakeup
1429 * case where we return around the loop.
1430 */
1431 mb();
1432 clflush(mwait_ptr);
1433 mb();
1434 __monitor(mwait_ptr, 0, 0);
1435 mb();
1436 __mwait(eax, 0);
1437 /*
1438 * If NMI wants to wake up CPU0, start CPU0.
1439 */
1440 if (wakeup_cpu0())
1441 start_cpu0();
1442 }
1443}
1444
1445static inline void hlt_play_dead(void)
1446{
1447 if (__this_cpu_read(cpu_info.x86) >= 4)
1448 wbinvd();
1449
1450 while (1) {
1451 native_halt();
1452 /*
1453 * If NMI wants to wake up CPU0, start CPU0.
1454 */
1455 if (wakeup_cpu0())
1456 start_cpu0();
1457 }
1458}
1459
1460void native_play_dead(void)
1461{
1462 play_dead_common();
1463 tboot_shutdown(TB_SHUTDOWN_WFS);
1464
1465 mwait_play_dead(); /* Only returns on failure */
1466 if (cpuidle_play_dead())
1467 hlt_play_dead();
1468}
1469
1470#else /* ... !CONFIG_HOTPLUG_CPU */
1471int native_cpu_disable(void)
1472{
1473 return -ENOSYS;
1474}
1475
1476void native_cpu_die(unsigned int cpu)
1477{
1478 /* We said "no" in __cpu_disable */
1479 BUG();
1480}
1481
1482void native_play_dead(void)
1483{
1484 BUG();
1485}
1486
1487#endif