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1/* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/module.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/pagemap.h>
11#include <linux/threads.h>
12#include <linux/smp.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/spinlock.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/cache.h>
21#include <linux/jiffies.h>
22#include <linux/profile.h>
23#include <linux/bootmem.h>
24#include <linux/vmalloc.h>
25#include <linux/ftrace.h>
26#include <linux/cpu.h>
27#include <linux/slab.h>
28
29#include <asm/head.h>
30#include <asm/ptrace.h>
31#include <linux/atomic.h>
32#include <asm/tlbflush.h>
33#include <asm/mmu_context.h>
34#include <asm/cpudata.h>
35#include <asm/hvtramp.h>
36#include <asm/io.h>
37#include <asm/timer.h>
38
39#include <asm/irq.h>
40#include <asm/irq_regs.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/oplib.h>
44#include <asm/uaccess.h>
45#include <asm/starfire.h>
46#include <asm/tlb.h>
47#include <asm/sections.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/ldc.h>
51#include <asm/hypervisor.h>
52#include <asm/pcr.h>
53
54#include "cpumap.h"
55
56int sparc64_multi_core __read_mostly;
57
58DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
59cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
60 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
61
62EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
63EXPORT_SYMBOL(cpu_core_map);
64
65static cpumask_t smp_commenced_mask;
66
67void smp_info(struct seq_file *m)
68{
69 int i;
70
71 seq_printf(m, "State:\n");
72 for_each_online_cpu(i)
73 seq_printf(m, "CPU%d:\t\tonline\n", i);
74}
75
76void smp_bogo(struct seq_file *m)
77{
78 int i;
79
80 for_each_online_cpu(i)
81 seq_printf(m,
82 "Cpu%dClkTck\t: %016lx\n",
83 i, cpu_data(i).clock_tick);
84}
85
86extern void setup_sparc64_timer(void);
87
88static volatile unsigned long callin_flag = 0;
89
90void __cpuinit smp_callin(void)
91{
92 int cpuid = hard_smp_processor_id();
93
94 __local_per_cpu_offset = __per_cpu_offset(cpuid);
95
96 if (tlb_type == hypervisor)
97 sun4v_ktsb_register();
98
99 __flush_tlb_all();
100
101 setup_sparc64_timer();
102
103 if (cheetah_pcache_forced_on)
104 cheetah_enable_pcache();
105
106 local_irq_enable();
107
108 callin_flag = 1;
109 __asm__ __volatile__("membar #Sync\n\t"
110 "flush %%g6" : : : "memory");
111
112 /* Clear this or we will die instantly when we
113 * schedule back to this idler...
114 */
115 current_thread_info()->new_child = 0;
116
117 /* Attach to the address space of init_task. */
118 atomic_inc(&init_mm.mm_count);
119 current->active_mm = &init_mm;
120
121 /* inform the notifiers about the new cpu */
122 notify_cpu_starting(cpuid);
123
124 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
125 rmb();
126
127 ipi_call_lock_irq();
128 set_cpu_online(cpuid, true);
129 ipi_call_unlock_irq();
130
131 /* idle thread is expected to have preempt disabled */
132 preempt_disable();
133}
134
135void cpu_panic(void)
136{
137 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
138 panic("SMP bolixed\n");
139}
140
141/* This tick register synchronization scheme is taken entirely from
142 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
143 *
144 * The only change I've made is to rework it so that the master
145 * initiates the synchonization instead of the slave. -DaveM
146 */
147
148#define MASTER 0
149#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
150
151#define NUM_ROUNDS 64 /* magic value */
152#define NUM_ITERS 5 /* likewise */
153
154static DEFINE_SPINLOCK(itc_sync_lock);
155static unsigned long go[SLAVE + 1];
156
157#define DEBUG_TICK_SYNC 0
158
159static inline long get_delta (long *rt, long *master)
160{
161 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
162 unsigned long tcenter, t0, t1, tm;
163 unsigned long i;
164
165 for (i = 0; i < NUM_ITERS; i++) {
166 t0 = tick_ops->get_tick();
167 go[MASTER] = 1;
168 membar_safe("#StoreLoad");
169 while (!(tm = go[SLAVE]))
170 rmb();
171 go[SLAVE] = 0;
172 wmb();
173 t1 = tick_ops->get_tick();
174
175 if (t1 - t0 < best_t1 - best_t0)
176 best_t0 = t0, best_t1 = t1, best_tm = tm;
177 }
178
179 *rt = best_t1 - best_t0;
180 *master = best_tm - best_t0;
181
182 /* average best_t0 and best_t1 without overflow: */
183 tcenter = (best_t0/2 + best_t1/2);
184 if (best_t0 % 2 + best_t1 % 2 == 2)
185 tcenter++;
186 return tcenter - best_tm;
187}
188
189void smp_synchronize_tick_client(void)
190{
191 long i, delta, adj, adjust_latency = 0, done = 0;
192 unsigned long flags, rt, master_time_stamp;
193#if DEBUG_TICK_SYNC
194 struct {
195 long rt; /* roundtrip time */
196 long master; /* master's timestamp */
197 long diff; /* difference between midpoint and master's timestamp */
198 long lat; /* estimate of itc adjustment latency */
199 } t[NUM_ROUNDS];
200#endif
201
202 go[MASTER] = 1;
203
204 while (go[MASTER])
205 rmb();
206
207 local_irq_save(flags);
208 {
209 for (i = 0; i < NUM_ROUNDS; i++) {
210 delta = get_delta(&rt, &master_time_stamp);
211 if (delta == 0)
212 done = 1; /* let's lock on to this... */
213
214 if (!done) {
215 if (i > 0) {
216 adjust_latency += -delta;
217 adj = -delta + adjust_latency/4;
218 } else
219 adj = -delta;
220
221 tick_ops->add_tick(adj);
222 }
223#if DEBUG_TICK_SYNC
224 t[i].rt = rt;
225 t[i].master = master_time_stamp;
226 t[i].diff = delta;
227 t[i].lat = adjust_latency/4;
228#endif
229 }
230 }
231 local_irq_restore(flags);
232
233#if DEBUG_TICK_SYNC
234 for (i = 0; i < NUM_ROUNDS; i++)
235 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
236 t[i].rt, t[i].master, t[i].diff, t[i].lat);
237#endif
238
239 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
240 "(last diff %ld cycles, maxerr %lu cycles)\n",
241 smp_processor_id(), delta, rt);
242}
243
244static void smp_start_sync_tick_client(int cpu);
245
246static void smp_synchronize_one_tick(int cpu)
247{
248 unsigned long flags, i;
249
250 go[MASTER] = 0;
251
252 smp_start_sync_tick_client(cpu);
253
254 /* wait for client to be ready */
255 while (!go[MASTER])
256 rmb();
257
258 /* now let the client proceed into his loop */
259 go[MASTER] = 0;
260 membar_safe("#StoreLoad");
261
262 spin_lock_irqsave(&itc_sync_lock, flags);
263 {
264 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
265 while (!go[MASTER])
266 rmb();
267 go[MASTER] = 0;
268 wmb();
269 go[SLAVE] = tick_ops->get_tick();
270 membar_safe("#StoreLoad");
271 }
272 }
273 spin_unlock_irqrestore(&itc_sync_lock, flags);
274}
275
276#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
277/* XXX Put this in some common place. XXX */
278static unsigned long kimage_addr_to_ra(void *p)
279{
280 unsigned long val = (unsigned long) p;
281
282 return kern_base + (val - KERNBASE);
283}
284
285static void __cpuinit ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg, void **descrp)
286{
287 extern unsigned long sparc64_ttable_tl0;
288 extern unsigned long kern_locked_tte_data;
289 struct hvtramp_descr *hdesc;
290 unsigned long trampoline_ra;
291 struct trap_per_cpu *tb;
292 u64 tte_vaddr, tte_data;
293 unsigned long hv_err;
294 int i;
295
296 hdesc = kzalloc(sizeof(*hdesc) +
297 (sizeof(struct hvtramp_mapping) *
298 num_kernel_image_mappings - 1),
299 GFP_KERNEL);
300 if (!hdesc) {
301 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
302 "hvtramp_descr.\n");
303 return;
304 }
305 *descrp = hdesc;
306
307 hdesc->cpu = cpu;
308 hdesc->num_mappings = num_kernel_image_mappings;
309
310 tb = &trap_block[cpu];
311
312 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
313 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
314
315 hdesc->thread_reg = thread_reg;
316
317 tte_vaddr = (unsigned long) KERNBASE;
318 tte_data = kern_locked_tte_data;
319
320 for (i = 0; i < hdesc->num_mappings; i++) {
321 hdesc->maps[i].vaddr = tte_vaddr;
322 hdesc->maps[i].tte = tte_data;
323 tte_vaddr += 0x400000;
324 tte_data += 0x400000;
325 }
326
327 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
328
329 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
330 kimage_addr_to_ra(&sparc64_ttable_tl0),
331 __pa(hdesc));
332 if (hv_err)
333 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
334 "gives error %lu\n", hv_err);
335}
336#endif
337
338extern unsigned long sparc64_cpu_startup;
339
340/* The OBP cpu startup callback truncates the 3rd arg cookie to
341 * 32-bits (I think) so to be safe we have it read the pointer
342 * contained here so we work on >4GB machines. -DaveM
343 */
344static struct thread_info *cpu_new_thread = NULL;
345
346static int __cpuinit smp_boot_one_cpu(unsigned int cpu)
347{
348 unsigned long entry =
349 (unsigned long)(&sparc64_cpu_startup);
350 unsigned long cookie =
351 (unsigned long)(&cpu_new_thread);
352 struct task_struct *p;
353 void *descr = NULL;
354 int timeout, ret;
355
356 p = fork_idle(cpu);
357 if (IS_ERR(p))
358 return PTR_ERR(p);
359 callin_flag = 0;
360 cpu_new_thread = task_thread_info(p);
361
362 if (tlb_type == hypervisor) {
363#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
364 if (ldom_domaining_enabled)
365 ldom_startcpu_cpuid(cpu,
366 (unsigned long) cpu_new_thread,
367 &descr);
368 else
369#endif
370 prom_startcpu_cpuid(cpu, entry, cookie);
371 } else {
372 struct device_node *dp = of_find_node_by_cpuid(cpu);
373
374 prom_startcpu(dp->phandle, entry, cookie);
375 }
376
377 for (timeout = 0; timeout < 50000; timeout++) {
378 if (callin_flag)
379 break;
380 udelay(100);
381 }
382
383 if (callin_flag) {
384 ret = 0;
385 } else {
386 printk("Processor %d is stuck.\n", cpu);
387 ret = -ENODEV;
388 }
389 cpu_new_thread = NULL;
390
391 kfree(descr);
392
393 return ret;
394}
395
396static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
397{
398 u64 result, target;
399 int stuck, tmp;
400
401 if (this_is_starfire) {
402 /* map to real upaid */
403 cpu = (((cpu & 0x3c) << 1) |
404 ((cpu & 0x40) >> 4) |
405 (cpu & 0x3));
406 }
407
408 target = (cpu << 14) | 0x70;
409again:
410 /* Ok, this is the real Spitfire Errata #54.
411 * One must read back from a UDB internal register
412 * after writes to the UDB interrupt dispatch, but
413 * before the membar Sync for that write.
414 * So we use the high UDB control register (ASI 0x7f,
415 * ADDR 0x20) for the dummy read. -DaveM
416 */
417 tmp = 0x40;
418 __asm__ __volatile__(
419 "wrpr %1, %2, %%pstate\n\t"
420 "stxa %4, [%0] %3\n\t"
421 "stxa %5, [%0+%8] %3\n\t"
422 "add %0, %8, %0\n\t"
423 "stxa %6, [%0+%8] %3\n\t"
424 "membar #Sync\n\t"
425 "stxa %%g0, [%7] %3\n\t"
426 "membar #Sync\n\t"
427 "mov 0x20, %%g1\n\t"
428 "ldxa [%%g1] 0x7f, %%g0\n\t"
429 "membar #Sync"
430 : "=r" (tmp)
431 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
432 "r" (data0), "r" (data1), "r" (data2), "r" (target),
433 "r" (0x10), "0" (tmp)
434 : "g1");
435
436 /* NOTE: PSTATE_IE is still clear. */
437 stuck = 100000;
438 do {
439 __asm__ __volatile__("ldxa [%%g0] %1, %0"
440 : "=r" (result)
441 : "i" (ASI_INTR_DISPATCH_STAT));
442 if (result == 0) {
443 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
444 : : "r" (pstate));
445 return;
446 }
447 stuck -= 1;
448 if (stuck == 0)
449 break;
450 } while (result & 0x1);
451 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
452 : : "r" (pstate));
453 if (stuck == 0) {
454 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
455 smp_processor_id(), result);
456 } else {
457 udelay(2);
458 goto again;
459 }
460}
461
462static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
463{
464 u64 *mondo, data0, data1, data2;
465 u16 *cpu_list;
466 u64 pstate;
467 int i;
468
469 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
470 cpu_list = __va(tb->cpu_list_pa);
471 mondo = __va(tb->cpu_mondo_block_pa);
472 data0 = mondo[0];
473 data1 = mondo[1];
474 data2 = mondo[2];
475 for (i = 0; i < cnt; i++)
476 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
477}
478
479/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
480 * packet, but we have no use for that. However we do take advantage of
481 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
482 */
483static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
484{
485 int nack_busy_id, is_jbus, need_more;
486 u64 *mondo, pstate, ver, busy_mask;
487 u16 *cpu_list;
488
489 cpu_list = __va(tb->cpu_list_pa);
490 mondo = __va(tb->cpu_mondo_block_pa);
491
492 /* Unfortunately, someone at Sun had the brilliant idea to make the
493 * busy/nack fields hard-coded by ITID number for this Ultra-III
494 * derivative processor.
495 */
496 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
497 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
498 (ver >> 32) == __SERRANO_ID);
499
500 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
501
502retry:
503 need_more = 0;
504 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
505 : : "r" (pstate), "i" (PSTATE_IE));
506
507 /* Setup the dispatch data registers. */
508 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
509 "stxa %1, [%4] %6\n\t"
510 "stxa %2, [%5] %6\n\t"
511 "membar #Sync\n\t"
512 : /* no outputs */
513 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
514 "r" (0x40), "r" (0x50), "r" (0x60),
515 "i" (ASI_INTR_W));
516
517 nack_busy_id = 0;
518 busy_mask = 0;
519 {
520 int i;
521
522 for (i = 0; i < cnt; i++) {
523 u64 target, nr;
524
525 nr = cpu_list[i];
526 if (nr == 0xffff)
527 continue;
528
529 target = (nr << 14) | 0x70;
530 if (is_jbus) {
531 busy_mask |= (0x1UL << (nr * 2));
532 } else {
533 target |= (nack_busy_id << 24);
534 busy_mask |= (0x1UL <<
535 (nack_busy_id * 2));
536 }
537 __asm__ __volatile__(
538 "stxa %%g0, [%0] %1\n\t"
539 "membar #Sync\n\t"
540 : /* no outputs */
541 : "r" (target), "i" (ASI_INTR_W));
542 nack_busy_id++;
543 if (nack_busy_id == 32) {
544 need_more = 1;
545 break;
546 }
547 }
548 }
549
550 /* Now, poll for completion. */
551 {
552 u64 dispatch_stat, nack_mask;
553 long stuck;
554
555 stuck = 100000 * nack_busy_id;
556 nack_mask = busy_mask << 1;
557 do {
558 __asm__ __volatile__("ldxa [%%g0] %1, %0"
559 : "=r" (dispatch_stat)
560 : "i" (ASI_INTR_DISPATCH_STAT));
561 if (!(dispatch_stat & (busy_mask | nack_mask))) {
562 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
563 : : "r" (pstate));
564 if (unlikely(need_more)) {
565 int i, this_cnt = 0;
566 for (i = 0; i < cnt; i++) {
567 if (cpu_list[i] == 0xffff)
568 continue;
569 cpu_list[i] = 0xffff;
570 this_cnt++;
571 if (this_cnt == 32)
572 break;
573 }
574 goto retry;
575 }
576 return;
577 }
578 if (!--stuck)
579 break;
580 } while (dispatch_stat & busy_mask);
581
582 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
583 : : "r" (pstate));
584
585 if (dispatch_stat & busy_mask) {
586 /* Busy bits will not clear, continue instead
587 * of freezing up on this cpu.
588 */
589 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
590 smp_processor_id(), dispatch_stat);
591 } else {
592 int i, this_busy_nack = 0;
593
594 /* Delay some random time with interrupts enabled
595 * to prevent deadlock.
596 */
597 udelay(2 * nack_busy_id);
598
599 /* Clear out the mask bits for cpus which did not
600 * NACK us.
601 */
602 for (i = 0; i < cnt; i++) {
603 u64 check_mask, nr;
604
605 nr = cpu_list[i];
606 if (nr == 0xffff)
607 continue;
608
609 if (is_jbus)
610 check_mask = (0x2UL << (2*nr));
611 else
612 check_mask = (0x2UL <<
613 this_busy_nack);
614 if ((dispatch_stat & check_mask) == 0)
615 cpu_list[i] = 0xffff;
616 this_busy_nack += 2;
617 if (this_busy_nack == 64)
618 break;
619 }
620
621 goto retry;
622 }
623 }
624}
625
626/* Multi-cpu list version. */
627static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
628{
629 int retries, this_cpu, prev_sent, i, saw_cpu_error;
630 unsigned long status;
631 u16 *cpu_list;
632
633 this_cpu = smp_processor_id();
634
635 cpu_list = __va(tb->cpu_list_pa);
636
637 saw_cpu_error = 0;
638 retries = 0;
639 prev_sent = 0;
640 do {
641 int forward_progress, n_sent;
642
643 status = sun4v_cpu_mondo_send(cnt,
644 tb->cpu_list_pa,
645 tb->cpu_mondo_block_pa);
646
647 /* HV_EOK means all cpus received the xcall, we're done. */
648 if (likely(status == HV_EOK))
649 break;
650
651 /* First, see if we made any forward progress.
652 *
653 * The hypervisor indicates successful sends by setting
654 * cpu list entries to the value 0xffff.
655 */
656 n_sent = 0;
657 for (i = 0; i < cnt; i++) {
658 if (likely(cpu_list[i] == 0xffff))
659 n_sent++;
660 }
661
662 forward_progress = 0;
663 if (n_sent > prev_sent)
664 forward_progress = 1;
665
666 prev_sent = n_sent;
667
668 /* If we get a HV_ECPUERROR, then one or more of the cpus
669 * in the list are in error state. Use the cpu_state()
670 * hypervisor call to find out which cpus are in error state.
671 */
672 if (unlikely(status == HV_ECPUERROR)) {
673 for (i = 0; i < cnt; i++) {
674 long err;
675 u16 cpu;
676
677 cpu = cpu_list[i];
678 if (cpu == 0xffff)
679 continue;
680
681 err = sun4v_cpu_state(cpu);
682 if (err == HV_CPU_STATE_ERROR) {
683 saw_cpu_error = (cpu + 1);
684 cpu_list[i] = 0xffff;
685 }
686 }
687 } else if (unlikely(status != HV_EWOULDBLOCK))
688 goto fatal_mondo_error;
689
690 /* Don't bother rewriting the CPU list, just leave the
691 * 0xffff and non-0xffff entries in there and the
692 * hypervisor will do the right thing.
693 *
694 * Only advance timeout state if we didn't make any
695 * forward progress.
696 */
697 if (unlikely(!forward_progress)) {
698 if (unlikely(++retries > 10000))
699 goto fatal_mondo_timeout;
700
701 /* Delay a little bit to let other cpus catch up
702 * on their cpu mondo queue work.
703 */
704 udelay(2 * cnt);
705 }
706 } while (1);
707
708 if (unlikely(saw_cpu_error))
709 goto fatal_mondo_cpu_error;
710
711 return;
712
713fatal_mondo_cpu_error:
714 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
715 "(including %d) were in error state\n",
716 this_cpu, saw_cpu_error - 1);
717 return;
718
719fatal_mondo_timeout:
720 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
721 " progress after %d retries.\n",
722 this_cpu, retries);
723 goto dump_cpu_list_and_out;
724
725fatal_mondo_error:
726 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
727 this_cpu, status);
728 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
729 "mondo_block_pa(%lx)\n",
730 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
731
732dump_cpu_list_and_out:
733 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
734 for (i = 0; i < cnt; i++)
735 printk("%u ", cpu_list[i]);
736 printk("]\n");
737}
738
739static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
740
741static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
742{
743 struct trap_per_cpu *tb;
744 int this_cpu, i, cnt;
745 unsigned long flags;
746 u16 *cpu_list;
747 u64 *mondo;
748
749 /* We have to do this whole thing with interrupts fully disabled.
750 * Otherwise if we send an xcall from interrupt context it will
751 * corrupt both our mondo block and cpu list state.
752 *
753 * One consequence of this is that we cannot use timeout mechanisms
754 * that depend upon interrupts being delivered locally. So, for
755 * example, we cannot sample jiffies and expect it to advance.
756 *
757 * Fortunately, udelay() uses %stick/%tick so we can use that.
758 */
759 local_irq_save(flags);
760
761 this_cpu = smp_processor_id();
762 tb = &trap_block[this_cpu];
763
764 mondo = __va(tb->cpu_mondo_block_pa);
765 mondo[0] = data0;
766 mondo[1] = data1;
767 mondo[2] = data2;
768 wmb();
769
770 cpu_list = __va(tb->cpu_list_pa);
771
772 /* Setup the initial cpu list. */
773 cnt = 0;
774 for_each_cpu(i, mask) {
775 if (i == this_cpu || !cpu_online(i))
776 continue;
777 cpu_list[cnt++] = i;
778 }
779
780 if (cnt)
781 xcall_deliver_impl(tb, cnt);
782
783 local_irq_restore(flags);
784}
785
786/* Send cross call to all processors mentioned in MASK_P
787 * except self. Really, there are only two cases currently,
788 * "cpu_online_mask" and "mm_cpumask(mm)".
789 */
790static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
791{
792 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
793
794 xcall_deliver(data0, data1, data2, mask);
795}
796
797/* Send cross call to all processors except self. */
798static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
799{
800 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
801}
802
803extern unsigned long xcall_sync_tick;
804
805static void smp_start_sync_tick_client(int cpu)
806{
807 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
808 cpumask_of(cpu));
809}
810
811extern unsigned long xcall_call_function;
812
813void arch_send_call_function_ipi_mask(const struct cpumask *mask)
814{
815 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
816}
817
818extern unsigned long xcall_call_function_single;
819
820void arch_send_call_function_single_ipi(int cpu)
821{
822 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
823 cpumask_of(cpu));
824}
825
826void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
827{
828 clear_softint(1 << irq);
829 generic_smp_call_function_interrupt();
830}
831
832void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
833{
834 clear_softint(1 << irq);
835 generic_smp_call_function_single_interrupt();
836}
837
838static void tsb_sync(void *info)
839{
840 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
841 struct mm_struct *mm = info;
842
843 /* It is not valid to test "currrent->active_mm == mm" here.
844 *
845 * The value of "current" is not changed atomically with
846 * switch_mm(). But that's OK, we just need to check the
847 * current cpu's trap block PGD physical address.
848 */
849 if (tp->pgd_paddr == __pa(mm->pgd))
850 tsb_context_switch(mm);
851}
852
853void smp_tsb_sync(struct mm_struct *mm)
854{
855 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
856}
857
858extern unsigned long xcall_flush_tlb_mm;
859extern unsigned long xcall_flush_tlb_pending;
860extern unsigned long xcall_flush_tlb_kernel_range;
861extern unsigned long xcall_fetch_glob_regs;
862extern unsigned long xcall_receive_signal;
863extern unsigned long xcall_new_mmu_context_version;
864#ifdef CONFIG_KGDB
865extern unsigned long xcall_kgdb_capture;
866#endif
867
868#ifdef DCACHE_ALIASING_POSSIBLE
869extern unsigned long xcall_flush_dcache_page_cheetah;
870#endif
871extern unsigned long xcall_flush_dcache_page_spitfire;
872
873#ifdef CONFIG_DEBUG_DCFLUSH
874extern atomic_t dcpage_flushes;
875extern atomic_t dcpage_flushes_xcall;
876#endif
877
878static inline void __local_flush_dcache_page(struct page *page)
879{
880#ifdef DCACHE_ALIASING_POSSIBLE
881 __flush_dcache_page(page_address(page),
882 ((tlb_type == spitfire) &&
883 page_mapping(page) != NULL));
884#else
885 if (page_mapping(page) != NULL &&
886 tlb_type == spitfire)
887 __flush_icache_page(__pa(page_address(page)));
888#endif
889}
890
891void smp_flush_dcache_page_impl(struct page *page, int cpu)
892{
893 int this_cpu;
894
895 if (tlb_type == hypervisor)
896 return;
897
898#ifdef CONFIG_DEBUG_DCFLUSH
899 atomic_inc(&dcpage_flushes);
900#endif
901
902 this_cpu = get_cpu();
903
904 if (cpu == this_cpu) {
905 __local_flush_dcache_page(page);
906 } else if (cpu_online(cpu)) {
907 void *pg_addr = page_address(page);
908 u64 data0 = 0;
909
910 if (tlb_type == spitfire) {
911 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
912 if (page_mapping(page) != NULL)
913 data0 |= ((u64)1 << 32);
914 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
915#ifdef DCACHE_ALIASING_POSSIBLE
916 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
917#endif
918 }
919 if (data0) {
920 xcall_deliver(data0, __pa(pg_addr),
921 (u64) pg_addr, cpumask_of(cpu));
922#ifdef CONFIG_DEBUG_DCFLUSH
923 atomic_inc(&dcpage_flushes_xcall);
924#endif
925 }
926 }
927
928 put_cpu();
929}
930
931void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
932{
933 void *pg_addr;
934 u64 data0;
935
936 if (tlb_type == hypervisor)
937 return;
938
939 preempt_disable();
940
941#ifdef CONFIG_DEBUG_DCFLUSH
942 atomic_inc(&dcpage_flushes);
943#endif
944 data0 = 0;
945 pg_addr = page_address(page);
946 if (tlb_type == spitfire) {
947 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
948 if (page_mapping(page) != NULL)
949 data0 |= ((u64)1 << 32);
950 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
951#ifdef DCACHE_ALIASING_POSSIBLE
952 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
953#endif
954 }
955 if (data0) {
956 xcall_deliver(data0, __pa(pg_addr),
957 (u64) pg_addr, cpu_online_mask);
958#ifdef CONFIG_DEBUG_DCFLUSH
959 atomic_inc(&dcpage_flushes_xcall);
960#endif
961 }
962 __local_flush_dcache_page(page);
963
964 preempt_enable();
965}
966
967void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
968{
969 struct mm_struct *mm;
970 unsigned long flags;
971
972 clear_softint(1 << irq);
973
974 /* See if we need to allocate a new TLB context because
975 * the version of the one we are using is now out of date.
976 */
977 mm = current->active_mm;
978 if (unlikely(!mm || (mm == &init_mm)))
979 return;
980
981 spin_lock_irqsave(&mm->context.lock, flags);
982
983 if (unlikely(!CTX_VALID(mm->context)))
984 get_new_mmu_context(mm);
985
986 spin_unlock_irqrestore(&mm->context.lock, flags);
987
988 load_secondary_context(mm);
989 __flush_tlb_mm(CTX_HWBITS(mm->context),
990 SECONDARY_CONTEXT);
991}
992
993void smp_new_mmu_context_version(void)
994{
995 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
996}
997
998#ifdef CONFIG_KGDB
999void kgdb_roundup_cpus(unsigned long flags)
1000{
1001 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
1002}
1003#endif
1004
1005void smp_fetch_global_regs(void)
1006{
1007 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1008}
1009
1010/* We know that the window frames of the user have been flushed
1011 * to the stack before we get here because all callers of us
1012 * are flush_tlb_*() routines, and these run after flush_cache_*()
1013 * which performs the flushw.
1014 *
1015 * The SMP TLB coherency scheme we use works as follows:
1016 *
1017 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1018 * space has (potentially) executed on, this is the heuristic
1019 * we use to avoid doing cross calls.
1020 *
1021 * Also, for flushing from kswapd and also for clones, we
1022 * use cpu_vm_mask as the list of cpus to make run the TLB.
1023 *
1024 * 2) TLB context numbers are shared globally across all processors
1025 * in the system, this allows us to play several games to avoid
1026 * cross calls.
1027 *
1028 * One invariant is that when a cpu switches to a process, and
1029 * that processes tsk->active_mm->cpu_vm_mask does not have the
1030 * current cpu's bit set, that tlb context is flushed locally.
1031 *
1032 * If the address space is non-shared (ie. mm->count == 1) we avoid
1033 * cross calls when we want to flush the currently running process's
1034 * tlb state. This is done by clearing all cpu bits except the current
1035 * processor's in current->mm->cpu_vm_mask and performing the
1036 * flush locally only. This will force any subsequent cpus which run
1037 * this task to flush the context from the local tlb if the process
1038 * migrates to another cpu (again).
1039 *
1040 * 3) For shared address spaces (threads) and swapping we bite the
1041 * bullet for most cases and perform the cross call (but only to
1042 * the cpus listed in cpu_vm_mask).
1043 *
1044 * The performance gain from "optimizing" away the cross call for threads is
1045 * questionable (in theory the big win for threads is the massive sharing of
1046 * address space state across processors).
1047 */
1048
1049/* This currently is only used by the hugetlb arch pre-fault
1050 * hook on UltraSPARC-III+ and later when changing the pagesize
1051 * bits of the context register for an address space.
1052 */
1053void smp_flush_tlb_mm(struct mm_struct *mm)
1054{
1055 u32 ctx = CTX_HWBITS(mm->context);
1056 int cpu = get_cpu();
1057
1058 if (atomic_read(&mm->mm_users) == 1) {
1059 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1060 goto local_flush_and_out;
1061 }
1062
1063 smp_cross_call_masked(&xcall_flush_tlb_mm,
1064 ctx, 0, 0,
1065 mm_cpumask(mm));
1066
1067local_flush_and_out:
1068 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1069
1070 put_cpu();
1071}
1072
1073void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1074{
1075 u32 ctx = CTX_HWBITS(mm->context);
1076 int cpu = get_cpu();
1077
1078 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1079 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1080 else
1081 smp_cross_call_masked(&xcall_flush_tlb_pending,
1082 ctx, nr, (unsigned long) vaddrs,
1083 mm_cpumask(mm));
1084
1085 __flush_tlb_pending(ctx, nr, vaddrs);
1086
1087 put_cpu();
1088}
1089
1090void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1091{
1092 start &= PAGE_MASK;
1093 end = PAGE_ALIGN(end);
1094 if (start != end) {
1095 smp_cross_call(&xcall_flush_tlb_kernel_range,
1096 0, start, end);
1097
1098 __flush_tlb_kernel_range(start, end);
1099 }
1100}
1101
1102/* CPU capture. */
1103/* #define CAPTURE_DEBUG */
1104extern unsigned long xcall_capture;
1105
1106static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1107static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1108static unsigned long penguins_are_doing_time;
1109
1110void smp_capture(void)
1111{
1112 int result = atomic_add_ret(1, &smp_capture_depth);
1113
1114 if (result == 1) {
1115 int ncpus = num_online_cpus();
1116
1117#ifdef CAPTURE_DEBUG
1118 printk("CPU[%d]: Sending penguins to jail...",
1119 smp_processor_id());
1120#endif
1121 penguins_are_doing_time = 1;
1122 atomic_inc(&smp_capture_registry);
1123 smp_cross_call(&xcall_capture, 0, 0, 0);
1124 while (atomic_read(&smp_capture_registry) != ncpus)
1125 rmb();
1126#ifdef CAPTURE_DEBUG
1127 printk("done\n");
1128#endif
1129 }
1130}
1131
1132void smp_release(void)
1133{
1134 if (atomic_dec_and_test(&smp_capture_depth)) {
1135#ifdef CAPTURE_DEBUG
1136 printk("CPU[%d]: Giving pardon to "
1137 "imprisoned penguins\n",
1138 smp_processor_id());
1139#endif
1140 penguins_are_doing_time = 0;
1141 membar_safe("#StoreLoad");
1142 atomic_dec(&smp_capture_registry);
1143 }
1144}
1145
1146/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1147 * set, so they can service tlb flush xcalls...
1148 */
1149extern void prom_world(int);
1150
1151void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1152{
1153 clear_softint(1 << irq);
1154
1155 preempt_disable();
1156
1157 __asm__ __volatile__("flushw");
1158 prom_world(1);
1159 atomic_inc(&smp_capture_registry);
1160 membar_safe("#StoreLoad");
1161 while (penguins_are_doing_time)
1162 rmb();
1163 atomic_dec(&smp_capture_registry);
1164 prom_world(0);
1165
1166 preempt_enable();
1167}
1168
1169/* /proc/profile writes can call this, don't __init it please. */
1170int setup_profiling_timer(unsigned int multiplier)
1171{
1172 return -EINVAL;
1173}
1174
1175void __init smp_prepare_cpus(unsigned int max_cpus)
1176{
1177}
1178
1179void __devinit smp_prepare_boot_cpu(void)
1180{
1181}
1182
1183void __init smp_setup_processor_id(void)
1184{
1185 if (tlb_type == spitfire)
1186 xcall_deliver_impl = spitfire_xcall_deliver;
1187 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1188 xcall_deliver_impl = cheetah_xcall_deliver;
1189 else
1190 xcall_deliver_impl = hypervisor_xcall_deliver;
1191}
1192
1193void __devinit smp_fill_in_sib_core_maps(void)
1194{
1195 unsigned int i;
1196
1197 for_each_present_cpu(i) {
1198 unsigned int j;
1199
1200 cpumask_clear(&cpu_core_map[i]);
1201 if (cpu_data(i).core_id == 0) {
1202 cpumask_set_cpu(i, &cpu_core_map[i]);
1203 continue;
1204 }
1205
1206 for_each_present_cpu(j) {
1207 if (cpu_data(i).core_id ==
1208 cpu_data(j).core_id)
1209 cpumask_set_cpu(j, &cpu_core_map[i]);
1210 }
1211 }
1212
1213 for_each_present_cpu(i) {
1214 unsigned int j;
1215
1216 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1217 if (cpu_data(i).proc_id == -1) {
1218 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1219 continue;
1220 }
1221
1222 for_each_present_cpu(j) {
1223 if (cpu_data(i).proc_id ==
1224 cpu_data(j).proc_id)
1225 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1226 }
1227 }
1228}
1229
1230int __cpuinit __cpu_up(unsigned int cpu)
1231{
1232 int ret = smp_boot_one_cpu(cpu);
1233
1234 if (!ret) {
1235 cpumask_set_cpu(cpu, &smp_commenced_mask);
1236 while (!cpu_online(cpu))
1237 mb();
1238 if (!cpu_online(cpu)) {
1239 ret = -ENODEV;
1240 } else {
1241 /* On SUN4V, writes to %tick and %stick are
1242 * not allowed.
1243 */
1244 if (tlb_type != hypervisor)
1245 smp_synchronize_one_tick(cpu);
1246 }
1247 }
1248 return ret;
1249}
1250
1251#ifdef CONFIG_HOTPLUG_CPU
1252void cpu_play_dead(void)
1253{
1254 int cpu = smp_processor_id();
1255 unsigned long pstate;
1256
1257 idle_task_exit();
1258
1259 if (tlb_type == hypervisor) {
1260 struct trap_per_cpu *tb = &trap_block[cpu];
1261
1262 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1263 tb->cpu_mondo_pa, 0);
1264 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1265 tb->dev_mondo_pa, 0);
1266 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1267 tb->resum_mondo_pa, 0);
1268 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1269 tb->nonresum_mondo_pa, 0);
1270 }
1271
1272 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1273 membar_safe("#Sync");
1274
1275 local_irq_disable();
1276
1277 __asm__ __volatile__(
1278 "rdpr %%pstate, %0\n\t"
1279 "wrpr %0, %1, %%pstate"
1280 : "=r" (pstate)
1281 : "i" (PSTATE_IE));
1282
1283 while (1)
1284 barrier();
1285}
1286
1287int __cpu_disable(void)
1288{
1289 int cpu = smp_processor_id();
1290 cpuinfo_sparc *c;
1291 int i;
1292
1293 for_each_cpu(i, &cpu_core_map[cpu])
1294 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1295 cpumask_clear(&cpu_core_map[cpu]);
1296
1297 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1298 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1299 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1300
1301 c = &cpu_data(cpu);
1302
1303 c->core_id = 0;
1304 c->proc_id = -1;
1305
1306 smp_wmb();
1307
1308 /* Make sure no interrupts point to this cpu. */
1309 fixup_irqs();
1310
1311 local_irq_enable();
1312 mdelay(1);
1313 local_irq_disable();
1314
1315 ipi_call_lock();
1316 set_cpu_online(cpu, false);
1317 ipi_call_unlock();
1318
1319 cpu_map_rebuild();
1320
1321 return 0;
1322}
1323
1324void __cpu_die(unsigned int cpu)
1325{
1326 int i;
1327
1328 for (i = 0; i < 100; i++) {
1329 smp_rmb();
1330 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1331 break;
1332 msleep(100);
1333 }
1334 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1335 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1336 } else {
1337#if defined(CONFIG_SUN_LDOMS)
1338 unsigned long hv_err;
1339 int limit = 100;
1340
1341 do {
1342 hv_err = sun4v_cpu_stop(cpu);
1343 if (hv_err == HV_EOK) {
1344 set_cpu_present(cpu, false);
1345 break;
1346 }
1347 } while (--limit > 0);
1348 if (limit <= 0) {
1349 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1350 hv_err);
1351 }
1352#endif
1353 }
1354}
1355#endif
1356
1357void __init smp_cpus_done(unsigned int max_cpus)
1358{
1359 pcr_arch_init();
1360}
1361
1362void smp_send_reschedule(int cpu)
1363{
1364 xcall_deliver((u64) &xcall_receive_signal, 0, 0,
1365 cpumask_of(cpu));
1366}
1367
1368void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1369{
1370 clear_softint(1 << irq);
1371 scheduler_ipi();
1372}
1373
1374/* This is a nop because we capture all other cpus
1375 * anyways when making the PROM active.
1376 */
1377void smp_send_stop(void)
1378{
1379}
1380
1381/**
1382 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1383 * @cpu: cpu to allocate for
1384 * @size: size allocation in bytes
1385 * @align: alignment
1386 *
1387 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1388 * does the right thing for NUMA regardless of the current
1389 * configuration.
1390 *
1391 * RETURNS:
1392 * Pointer to the allocated area on success, NULL on failure.
1393 */
1394static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1395 size_t align)
1396{
1397 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1398#ifdef CONFIG_NEED_MULTIPLE_NODES
1399 int node = cpu_to_node(cpu);
1400 void *ptr;
1401
1402 if (!node_online(node) || !NODE_DATA(node)) {
1403 ptr = __alloc_bootmem(size, align, goal);
1404 pr_info("cpu %d has no node %d or node-local memory\n",
1405 cpu, node);
1406 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1407 cpu, size, __pa(ptr));
1408 } else {
1409 ptr = __alloc_bootmem_node(NODE_DATA(node),
1410 size, align, goal);
1411 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1412 "%016lx\n", cpu, size, node, __pa(ptr));
1413 }
1414 return ptr;
1415#else
1416 return __alloc_bootmem(size, align, goal);
1417#endif
1418}
1419
1420static void __init pcpu_free_bootmem(void *ptr, size_t size)
1421{
1422 free_bootmem(__pa(ptr), size);
1423}
1424
1425static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1426{
1427 if (cpu_to_node(from) == cpu_to_node(to))
1428 return LOCAL_DISTANCE;
1429 else
1430 return REMOTE_DISTANCE;
1431}
1432
1433static void __init pcpu_populate_pte(unsigned long addr)
1434{
1435 pgd_t *pgd = pgd_offset_k(addr);
1436 pud_t *pud;
1437 pmd_t *pmd;
1438
1439 pud = pud_offset(pgd, addr);
1440 if (pud_none(*pud)) {
1441 pmd_t *new;
1442
1443 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1444 pud_populate(&init_mm, pud, new);
1445 }
1446
1447 pmd = pmd_offset(pud, addr);
1448 if (!pmd_present(*pmd)) {
1449 pte_t *new;
1450
1451 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1452 pmd_populate_kernel(&init_mm, pmd, new);
1453 }
1454}
1455
1456void __init setup_per_cpu_areas(void)
1457{
1458 unsigned long delta;
1459 unsigned int cpu;
1460 int rc = -EINVAL;
1461
1462 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1463 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1464 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1465 pcpu_cpu_distance,
1466 pcpu_alloc_bootmem,
1467 pcpu_free_bootmem);
1468 if (rc)
1469 pr_warning("PERCPU: %s allocator failed (%d), "
1470 "falling back to page size\n",
1471 pcpu_fc_names[pcpu_chosen_fc], rc);
1472 }
1473 if (rc < 0)
1474 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1475 pcpu_alloc_bootmem,
1476 pcpu_free_bootmem,
1477 pcpu_populate_pte);
1478 if (rc < 0)
1479 panic("cannot initialize percpu area (err=%d)", rc);
1480
1481 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1482 for_each_possible_cpu(cpu)
1483 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1484
1485 /* Setup %g5 for the boot cpu. */
1486 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1487
1488 of_fill_in_cpu_data();
1489 if (tlb_type == hypervisor)
1490 mdesc_fill_in_cpu_data(cpu_all_mask);
1491}
1/* smp.c: Sparc64 SMP support.
2 *
3 * Copyright (C) 1997, 2007, 2008 David S. Miller (davem@davemloft.net)
4 */
5
6#include <linux/export.h>
7#include <linux/kernel.h>
8#include <linux/sched.h>
9#include <linux/mm.h>
10#include <linux/pagemap.h>
11#include <linux/threads.h>
12#include <linux/smp.h>
13#include <linux/interrupt.h>
14#include <linux/kernel_stat.h>
15#include <linux/delay.h>
16#include <linux/init.h>
17#include <linux/spinlock.h>
18#include <linux/fs.h>
19#include <linux/seq_file.h>
20#include <linux/cache.h>
21#include <linux/jiffies.h>
22#include <linux/profile.h>
23#include <linux/bootmem.h>
24#include <linux/vmalloc.h>
25#include <linux/ftrace.h>
26#include <linux/cpu.h>
27#include <linux/slab.h>
28
29#include <asm/head.h>
30#include <asm/ptrace.h>
31#include <linux/atomic.h>
32#include <asm/tlbflush.h>
33#include <asm/mmu_context.h>
34#include <asm/cpudata.h>
35#include <asm/hvtramp.h>
36#include <asm/io.h>
37#include <asm/timer.h>
38
39#include <asm/irq.h>
40#include <asm/irq_regs.h>
41#include <asm/page.h>
42#include <asm/pgtable.h>
43#include <asm/oplib.h>
44#include <asm/uaccess.h>
45#include <asm/starfire.h>
46#include <asm/tlb.h>
47#include <asm/sections.h>
48#include <asm/prom.h>
49#include <asm/mdesc.h>
50#include <asm/ldc.h>
51#include <asm/hypervisor.h>
52#include <asm/pcr.h>
53
54#include "cpumap.h"
55
56DEFINE_PER_CPU(cpumask_t, cpu_sibling_map) = CPU_MASK_NONE;
57cpumask_t cpu_core_map[NR_CPUS] __read_mostly =
58 { [0 ... NR_CPUS-1] = CPU_MASK_NONE };
59
60EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
61EXPORT_SYMBOL(cpu_core_map);
62
63static cpumask_t smp_commenced_mask;
64
65void smp_info(struct seq_file *m)
66{
67 int i;
68
69 seq_printf(m, "State:\n");
70 for_each_online_cpu(i)
71 seq_printf(m, "CPU%d:\t\tonline\n", i);
72}
73
74void smp_bogo(struct seq_file *m)
75{
76 int i;
77
78 for_each_online_cpu(i)
79 seq_printf(m,
80 "Cpu%dClkTck\t: %016lx\n",
81 i, cpu_data(i).clock_tick);
82}
83
84extern void setup_sparc64_timer(void);
85
86static volatile unsigned long callin_flag = 0;
87
88void smp_callin(void)
89{
90 int cpuid = hard_smp_processor_id();
91
92 __local_per_cpu_offset = __per_cpu_offset(cpuid);
93
94 if (tlb_type == hypervisor)
95 sun4v_ktsb_register();
96
97 __flush_tlb_all();
98
99 setup_sparc64_timer();
100
101 if (cheetah_pcache_forced_on)
102 cheetah_enable_pcache();
103
104 callin_flag = 1;
105 __asm__ __volatile__("membar #Sync\n\t"
106 "flush %%g6" : : : "memory");
107
108 /* Clear this or we will die instantly when we
109 * schedule back to this idler...
110 */
111 current_thread_info()->new_child = 0;
112
113 /* Attach to the address space of init_task. */
114 atomic_inc(&init_mm.mm_count);
115 current->active_mm = &init_mm;
116
117 /* inform the notifiers about the new cpu */
118 notify_cpu_starting(cpuid);
119
120 while (!cpumask_test_cpu(cpuid, &smp_commenced_mask))
121 rmb();
122
123 set_cpu_online(cpuid, true);
124
125 /* idle thread is expected to have preempt disabled */
126 preempt_disable();
127
128 local_irq_enable();
129
130 cpu_startup_entry(CPUHP_ONLINE);
131}
132
133void cpu_panic(void)
134{
135 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
136 panic("SMP bolixed\n");
137}
138
139/* This tick register synchronization scheme is taken entirely from
140 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
141 *
142 * The only change I've made is to rework it so that the master
143 * initiates the synchonization instead of the slave. -DaveM
144 */
145
146#define MASTER 0
147#define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
148
149#define NUM_ROUNDS 64 /* magic value */
150#define NUM_ITERS 5 /* likewise */
151
152static DEFINE_RAW_SPINLOCK(itc_sync_lock);
153static unsigned long go[SLAVE + 1];
154
155#define DEBUG_TICK_SYNC 0
156
157static inline long get_delta (long *rt, long *master)
158{
159 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
160 unsigned long tcenter, t0, t1, tm;
161 unsigned long i;
162
163 for (i = 0; i < NUM_ITERS; i++) {
164 t0 = tick_ops->get_tick();
165 go[MASTER] = 1;
166 membar_safe("#StoreLoad");
167 while (!(tm = go[SLAVE]))
168 rmb();
169 go[SLAVE] = 0;
170 wmb();
171 t1 = tick_ops->get_tick();
172
173 if (t1 - t0 < best_t1 - best_t0)
174 best_t0 = t0, best_t1 = t1, best_tm = tm;
175 }
176
177 *rt = best_t1 - best_t0;
178 *master = best_tm - best_t0;
179
180 /* average best_t0 and best_t1 without overflow: */
181 tcenter = (best_t0/2 + best_t1/2);
182 if (best_t0 % 2 + best_t1 % 2 == 2)
183 tcenter++;
184 return tcenter - best_tm;
185}
186
187void smp_synchronize_tick_client(void)
188{
189 long i, delta, adj, adjust_latency = 0, done = 0;
190 unsigned long flags, rt, master_time_stamp;
191#if DEBUG_TICK_SYNC
192 struct {
193 long rt; /* roundtrip time */
194 long master; /* master's timestamp */
195 long diff; /* difference between midpoint and master's timestamp */
196 long lat; /* estimate of itc adjustment latency */
197 } t[NUM_ROUNDS];
198#endif
199
200 go[MASTER] = 1;
201
202 while (go[MASTER])
203 rmb();
204
205 local_irq_save(flags);
206 {
207 for (i = 0; i < NUM_ROUNDS; i++) {
208 delta = get_delta(&rt, &master_time_stamp);
209 if (delta == 0)
210 done = 1; /* let's lock on to this... */
211
212 if (!done) {
213 if (i > 0) {
214 adjust_latency += -delta;
215 adj = -delta + adjust_latency/4;
216 } else
217 adj = -delta;
218
219 tick_ops->add_tick(adj);
220 }
221#if DEBUG_TICK_SYNC
222 t[i].rt = rt;
223 t[i].master = master_time_stamp;
224 t[i].diff = delta;
225 t[i].lat = adjust_latency/4;
226#endif
227 }
228 }
229 local_irq_restore(flags);
230
231#if DEBUG_TICK_SYNC
232 for (i = 0; i < NUM_ROUNDS; i++)
233 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
234 t[i].rt, t[i].master, t[i].diff, t[i].lat);
235#endif
236
237 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU "
238 "(last diff %ld cycles, maxerr %lu cycles)\n",
239 smp_processor_id(), delta, rt);
240}
241
242static void smp_start_sync_tick_client(int cpu);
243
244static void smp_synchronize_one_tick(int cpu)
245{
246 unsigned long flags, i;
247
248 go[MASTER] = 0;
249
250 smp_start_sync_tick_client(cpu);
251
252 /* wait for client to be ready */
253 while (!go[MASTER])
254 rmb();
255
256 /* now let the client proceed into his loop */
257 go[MASTER] = 0;
258 membar_safe("#StoreLoad");
259
260 raw_spin_lock_irqsave(&itc_sync_lock, flags);
261 {
262 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
263 while (!go[MASTER])
264 rmb();
265 go[MASTER] = 0;
266 wmb();
267 go[SLAVE] = tick_ops->get_tick();
268 membar_safe("#StoreLoad");
269 }
270 }
271 raw_spin_unlock_irqrestore(&itc_sync_lock, flags);
272}
273
274#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
275/* XXX Put this in some common place. XXX */
276static unsigned long kimage_addr_to_ra(void *p)
277{
278 unsigned long val = (unsigned long) p;
279
280 return kern_base + (val - KERNBASE);
281}
282
283static void ldom_startcpu_cpuid(unsigned int cpu, unsigned long thread_reg,
284 void **descrp)
285{
286 extern unsigned long sparc64_ttable_tl0;
287 extern unsigned long kern_locked_tte_data;
288 struct hvtramp_descr *hdesc;
289 unsigned long trampoline_ra;
290 struct trap_per_cpu *tb;
291 u64 tte_vaddr, tte_data;
292 unsigned long hv_err;
293 int i;
294
295 hdesc = kzalloc(sizeof(*hdesc) +
296 (sizeof(struct hvtramp_mapping) *
297 num_kernel_image_mappings - 1),
298 GFP_KERNEL);
299 if (!hdesc) {
300 printk(KERN_ERR "ldom_startcpu_cpuid: Cannot allocate "
301 "hvtramp_descr.\n");
302 return;
303 }
304 *descrp = hdesc;
305
306 hdesc->cpu = cpu;
307 hdesc->num_mappings = num_kernel_image_mappings;
308
309 tb = &trap_block[cpu];
310
311 hdesc->fault_info_va = (unsigned long) &tb->fault_info;
312 hdesc->fault_info_pa = kimage_addr_to_ra(&tb->fault_info);
313
314 hdesc->thread_reg = thread_reg;
315
316 tte_vaddr = (unsigned long) KERNBASE;
317 tte_data = kern_locked_tte_data;
318
319 for (i = 0; i < hdesc->num_mappings; i++) {
320 hdesc->maps[i].vaddr = tte_vaddr;
321 hdesc->maps[i].tte = tte_data;
322 tte_vaddr += 0x400000;
323 tte_data += 0x400000;
324 }
325
326 trampoline_ra = kimage_addr_to_ra(hv_cpu_startup);
327
328 hv_err = sun4v_cpu_start(cpu, trampoline_ra,
329 kimage_addr_to_ra(&sparc64_ttable_tl0),
330 __pa(hdesc));
331 if (hv_err)
332 printk(KERN_ERR "ldom_startcpu_cpuid: sun4v_cpu_start() "
333 "gives error %lu\n", hv_err);
334}
335#endif
336
337extern unsigned long sparc64_cpu_startup;
338
339/* The OBP cpu startup callback truncates the 3rd arg cookie to
340 * 32-bits (I think) so to be safe we have it read the pointer
341 * contained here so we work on >4GB machines. -DaveM
342 */
343static struct thread_info *cpu_new_thread = NULL;
344
345static int smp_boot_one_cpu(unsigned int cpu, struct task_struct *idle)
346{
347 unsigned long entry =
348 (unsigned long)(&sparc64_cpu_startup);
349 unsigned long cookie =
350 (unsigned long)(&cpu_new_thread);
351 void *descr = NULL;
352 int timeout, ret;
353
354 callin_flag = 0;
355 cpu_new_thread = task_thread_info(idle);
356
357 if (tlb_type == hypervisor) {
358#if defined(CONFIG_SUN_LDOMS) && defined(CONFIG_HOTPLUG_CPU)
359 if (ldom_domaining_enabled)
360 ldom_startcpu_cpuid(cpu,
361 (unsigned long) cpu_new_thread,
362 &descr);
363 else
364#endif
365 prom_startcpu_cpuid(cpu, entry, cookie);
366 } else {
367 struct device_node *dp = of_find_node_by_cpuid(cpu);
368
369 prom_startcpu(dp->phandle, entry, cookie);
370 }
371
372 for (timeout = 0; timeout < 50000; timeout++) {
373 if (callin_flag)
374 break;
375 udelay(100);
376 }
377
378 if (callin_flag) {
379 ret = 0;
380 } else {
381 printk("Processor %d is stuck.\n", cpu);
382 ret = -ENODEV;
383 }
384 cpu_new_thread = NULL;
385
386 kfree(descr);
387
388 return ret;
389}
390
391static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
392{
393 u64 result, target;
394 int stuck, tmp;
395
396 if (this_is_starfire) {
397 /* map to real upaid */
398 cpu = (((cpu & 0x3c) << 1) |
399 ((cpu & 0x40) >> 4) |
400 (cpu & 0x3));
401 }
402
403 target = (cpu << 14) | 0x70;
404again:
405 /* Ok, this is the real Spitfire Errata #54.
406 * One must read back from a UDB internal register
407 * after writes to the UDB interrupt dispatch, but
408 * before the membar Sync for that write.
409 * So we use the high UDB control register (ASI 0x7f,
410 * ADDR 0x20) for the dummy read. -DaveM
411 */
412 tmp = 0x40;
413 __asm__ __volatile__(
414 "wrpr %1, %2, %%pstate\n\t"
415 "stxa %4, [%0] %3\n\t"
416 "stxa %5, [%0+%8] %3\n\t"
417 "add %0, %8, %0\n\t"
418 "stxa %6, [%0+%8] %3\n\t"
419 "membar #Sync\n\t"
420 "stxa %%g0, [%7] %3\n\t"
421 "membar #Sync\n\t"
422 "mov 0x20, %%g1\n\t"
423 "ldxa [%%g1] 0x7f, %%g0\n\t"
424 "membar #Sync"
425 : "=r" (tmp)
426 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
427 "r" (data0), "r" (data1), "r" (data2), "r" (target),
428 "r" (0x10), "0" (tmp)
429 : "g1");
430
431 /* NOTE: PSTATE_IE is still clear. */
432 stuck = 100000;
433 do {
434 __asm__ __volatile__("ldxa [%%g0] %1, %0"
435 : "=r" (result)
436 : "i" (ASI_INTR_DISPATCH_STAT));
437 if (result == 0) {
438 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
439 : : "r" (pstate));
440 return;
441 }
442 stuck -= 1;
443 if (stuck == 0)
444 break;
445 } while (result & 0x1);
446 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
447 : : "r" (pstate));
448 if (stuck == 0) {
449 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
450 smp_processor_id(), result);
451 } else {
452 udelay(2);
453 goto again;
454 }
455}
456
457static void spitfire_xcall_deliver(struct trap_per_cpu *tb, int cnt)
458{
459 u64 *mondo, data0, data1, data2;
460 u16 *cpu_list;
461 u64 pstate;
462 int i;
463
464 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
465 cpu_list = __va(tb->cpu_list_pa);
466 mondo = __va(tb->cpu_mondo_block_pa);
467 data0 = mondo[0];
468 data1 = mondo[1];
469 data2 = mondo[2];
470 for (i = 0; i < cnt; i++)
471 spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
472}
473
474/* Cheetah now allows to send the whole 64-bytes of data in the interrupt
475 * packet, but we have no use for that. However we do take advantage of
476 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
477 */
478static void cheetah_xcall_deliver(struct trap_per_cpu *tb, int cnt)
479{
480 int nack_busy_id, is_jbus, need_more;
481 u64 *mondo, pstate, ver, busy_mask;
482 u16 *cpu_list;
483
484 cpu_list = __va(tb->cpu_list_pa);
485 mondo = __va(tb->cpu_mondo_block_pa);
486
487 /* Unfortunately, someone at Sun had the brilliant idea to make the
488 * busy/nack fields hard-coded by ITID number for this Ultra-III
489 * derivative processor.
490 */
491 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
492 is_jbus = ((ver >> 32) == __JALAPENO_ID ||
493 (ver >> 32) == __SERRANO_ID);
494
495 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
496
497retry:
498 need_more = 0;
499 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
500 : : "r" (pstate), "i" (PSTATE_IE));
501
502 /* Setup the dispatch data registers. */
503 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
504 "stxa %1, [%4] %6\n\t"
505 "stxa %2, [%5] %6\n\t"
506 "membar #Sync\n\t"
507 : /* no outputs */
508 : "r" (mondo[0]), "r" (mondo[1]), "r" (mondo[2]),
509 "r" (0x40), "r" (0x50), "r" (0x60),
510 "i" (ASI_INTR_W));
511
512 nack_busy_id = 0;
513 busy_mask = 0;
514 {
515 int i;
516
517 for (i = 0; i < cnt; i++) {
518 u64 target, nr;
519
520 nr = cpu_list[i];
521 if (nr == 0xffff)
522 continue;
523
524 target = (nr << 14) | 0x70;
525 if (is_jbus) {
526 busy_mask |= (0x1UL << (nr * 2));
527 } else {
528 target |= (nack_busy_id << 24);
529 busy_mask |= (0x1UL <<
530 (nack_busy_id * 2));
531 }
532 __asm__ __volatile__(
533 "stxa %%g0, [%0] %1\n\t"
534 "membar #Sync\n\t"
535 : /* no outputs */
536 : "r" (target), "i" (ASI_INTR_W));
537 nack_busy_id++;
538 if (nack_busy_id == 32) {
539 need_more = 1;
540 break;
541 }
542 }
543 }
544
545 /* Now, poll for completion. */
546 {
547 u64 dispatch_stat, nack_mask;
548 long stuck;
549
550 stuck = 100000 * nack_busy_id;
551 nack_mask = busy_mask << 1;
552 do {
553 __asm__ __volatile__("ldxa [%%g0] %1, %0"
554 : "=r" (dispatch_stat)
555 : "i" (ASI_INTR_DISPATCH_STAT));
556 if (!(dispatch_stat & (busy_mask | nack_mask))) {
557 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
558 : : "r" (pstate));
559 if (unlikely(need_more)) {
560 int i, this_cnt = 0;
561 for (i = 0; i < cnt; i++) {
562 if (cpu_list[i] == 0xffff)
563 continue;
564 cpu_list[i] = 0xffff;
565 this_cnt++;
566 if (this_cnt == 32)
567 break;
568 }
569 goto retry;
570 }
571 return;
572 }
573 if (!--stuck)
574 break;
575 } while (dispatch_stat & busy_mask);
576
577 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
578 : : "r" (pstate));
579
580 if (dispatch_stat & busy_mask) {
581 /* Busy bits will not clear, continue instead
582 * of freezing up on this cpu.
583 */
584 printk("CPU[%d]: mondo stuckage result[%016llx]\n",
585 smp_processor_id(), dispatch_stat);
586 } else {
587 int i, this_busy_nack = 0;
588
589 /* Delay some random time with interrupts enabled
590 * to prevent deadlock.
591 */
592 udelay(2 * nack_busy_id);
593
594 /* Clear out the mask bits for cpus which did not
595 * NACK us.
596 */
597 for (i = 0; i < cnt; i++) {
598 u64 check_mask, nr;
599
600 nr = cpu_list[i];
601 if (nr == 0xffff)
602 continue;
603
604 if (is_jbus)
605 check_mask = (0x2UL << (2*nr));
606 else
607 check_mask = (0x2UL <<
608 this_busy_nack);
609 if ((dispatch_stat & check_mask) == 0)
610 cpu_list[i] = 0xffff;
611 this_busy_nack += 2;
612 if (this_busy_nack == 64)
613 break;
614 }
615
616 goto retry;
617 }
618 }
619}
620
621/* Multi-cpu list version. */
622static void hypervisor_xcall_deliver(struct trap_per_cpu *tb, int cnt)
623{
624 int retries, this_cpu, prev_sent, i, saw_cpu_error;
625 unsigned long status;
626 u16 *cpu_list;
627
628 this_cpu = smp_processor_id();
629
630 cpu_list = __va(tb->cpu_list_pa);
631
632 saw_cpu_error = 0;
633 retries = 0;
634 prev_sent = 0;
635 do {
636 int forward_progress, n_sent;
637
638 status = sun4v_cpu_mondo_send(cnt,
639 tb->cpu_list_pa,
640 tb->cpu_mondo_block_pa);
641
642 /* HV_EOK means all cpus received the xcall, we're done. */
643 if (likely(status == HV_EOK))
644 break;
645
646 /* First, see if we made any forward progress.
647 *
648 * The hypervisor indicates successful sends by setting
649 * cpu list entries to the value 0xffff.
650 */
651 n_sent = 0;
652 for (i = 0; i < cnt; i++) {
653 if (likely(cpu_list[i] == 0xffff))
654 n_sent++;
655 }
656
657 forward_progress = 0;
658 if (n_sent > prev_sent)
659 forward_progress = 1;
660
661 prev_sent = n_sent;
662
663 /* If we get a HV_ECPUERROR, then one or more of the cpus
664 * in the list are in error state. Use the cpu_state()
665 * hypervisor call to find out which cpus are in error state.
666 */
667 if (unlikely(status == HV_ECPUERROR)) {
668 for (i = 0; i < cnt; i++) {
669 long err;
670 u16 cpu;
671
672 cpu = cpu_list[i];
673 if (cpu == 0xffff)
674 continue;
675
676 err = sun4v_cpu_state(cpu);
677 if (err == HV_CPU_STATE_ERROR) {
678 saw_cpu_error = (cpu + 1);
679 cpu_list[i] = 0xffff;
680 }
681 }
682 } else if (unlikely(status != HV_EWOULDBLOCK))
683 goto fatal_mondo_error;
684
685 /* Don't bother rewriting the CPU list, just leave the
686 * 0xffff and non-0xffff entries in there and the
687 * hypervisor will do the right thing.
688 *
689 * Only advance timeout state if we didn't make any
690 * forward progress.
691 */
692 if (unlikely(!forward_progress)) {
693 if (unlikely(++retries > 10000))
694 goto fatal_mondo_timeout;
695
696 /* Delay a little bit to let other cpus catch up
697 * on their cpu mondo queue work.
698 */
699 udelay(2 * cnt);
700 }
701 } while (1);
702
703 if (unlikely(saw_cpu_error))
704 goto fatal_mondo_cpu_error;
705
706 return;
707
708fatal_mondo_cpu_error:
709 printk(KERN_CRIT "CPU[%d]: SUN4V mondo cpu error, some target cpus "
710 "(including %d) were in error state\n",
711 this_cpu, saw_cpu_error - 1);
712 return;
713
714fatal_mondo_timeout:
715 printk(KERN_CRIT "CPU[%d]: SUN4V mondo timeout, no forward "
716 " progress after %d retries.\n",
717 this_cpu, retries);
718 goto dump_cpu_list_and_out;
719
720fatal_mondo_error:
721 printk(KERN_CRIT "CPU[%d]: Unexpected SUN4V mondo error %lu\n",
722 this_cpu, status);
723 printk(KERN_CRIT "CPU[%d]: Args were cnt(%d) cpulist_pa(%lx) "
724 "mondo_block_pa(%lx)\n",
725 this_cpu, cnt, tb->cpu_list_pa, tb->cpu_mondo_block_pa);
726
727dump_cpu_list_and_out:
728 printk(KERN_CRIT "CPU[%d]: CPU list [ ", this_cpu);
729 for (i = 0; i < cnt; i++)
730 printk("%u ", cpu_list[i]);
731 printk("]\n");
732}
733
734static void (*xcall_deliver_impl)(struct trap_per_cpu *, int);
735
736static void xcall_deliver(u64 data0, u64 data1, u64 data2, const cpumask_t *mask)
737{
738 struct trap_per_cpu *tb;
739 int this_cpu, i, cnt;
740 unsigned long flags;
741 u16 *cpu_list;
742 u64 *mondo;
743
744 /* We have to do this whole thing with interrupts fully disabled.
745 * Otherwise if we send an xcall from interrupt context it will
746 * corrupt both our mondo block and cpu list state.
747 *
748 * One consequence of this is that we cannot use timeout mechanisms
749 * that depend upon interrupts being delivered locally. So, for
750 * example, we cannot sample jiffies and expect it to advance.
751 *
752 * Fortunately, udelay() uses %stick/%tick so we can use that.
753 */
754 local_irq_save(flags);
755
756 this_cpu = smp_processor_id();
757 tb = &trap_block[this_cpu];
758
759 mondo = __va(tb->cpu_mondo_block_pa);
760 mondo[0] = data0;
761 mondo[1] = data1;
762 mondo[2] = data2;
763 wmb();
764
765 cpu_list = __va(tb->cpu_list_pa);
766
767 /* Setup the initial cpu list. */
768 cnt = 0;
769 for_each_cpu(i, mask) {
770 if (i == this_cpu || !cpu_online(i))
771 continue;
772 cpu_list[cnt++] = i;
773 }
774
775 if (cnt)
776 xcall_deliver_impl(tb, cnt);
777
778 local_irq_restore(flags);
779}
780
781/* Send cross call to all processors mentioned in MASK_P
782 * except self. Really, there are only two cases currently,
783 * "cpu_online_mask" and "mm_cpumask(mm)".
784 */
785static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, const cpumask_t *mask)
786{
787 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
788
789 xcall_deliver(data0, data1, data2, mask);
790}
791
792/* Send cross call to all processors except self. */
793static void smp_cross_call(unsigned long *func, u32 ctx, u64 data1, u64 data2)
794{
795 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_mask);
796}
797
798extern unsigned long xcall_sync_tick;
799
800static void smp_start_sync_tick_client(int cpu)
801{
802 xcall_deliver((u64) &xcall_sync_tick, 0, 0,
803 cpumask_of(cpu));
804}
805
806extern unsigned long xcall_call_function;
807
808void arch_send_call_function_ipi_mask(const struct cpumask *mask)
809{
810 xcall_deliver((u64) &xcall_call_function, 0, 0, mask);
811}
812
813extern unsigned long xcall_call_function_single;
814
815void arch_send_call_function_single_ipi(int cpu)
816{
817 xcall_deliver((u64) &xcall_call_function_single, 0, 0,
818 cpumask_of(cpu));
819}
820
821void __irq_entry smp_call_function_client(int irq, struct pt_regs *regs)
822{
823 clear_softint(1 << irq);
824 generic_smp_call_function_interrupt();
825}
826
827void __irq_entry smp_call_function_single_client(int irq, struct pt_regs *regs)
828{
829 clear_softint(1 << irq);
830 generic_smp_call_function_single_interrupt();
831}
832
833static void tsb_sync(void *info)
834{
835 struct trap_per_cpu *tp = &trap_block[raw_smp_processor_id()];
836 struct mm_struct *mm = info;
837
838 /* It is not valid to test "current->active_mm == mm" here.
839 *
840 * The value of "current" is not changed atomically with
841 * switch_mm(). But that's OK, we just need to check the
842 * current cpu's trap block PGD physical address.
843 */
844 if (tp->pgd_paddr == __pa(mm->pgd))
845 tsb_context_switch(mm);
846}
847
848void smp_tsb_sync(struct mm_struct *mm)
849{
850 smp_call_function_many(mm_cpumask(mm), tsb_sync, mm, 1);
851}
852
853extern unsigned long xcall_flush_tlb_mm;
854extern unsigned long xcall_flush_tlb_page;
855extern unsigned long xcall_flush_tlb_kernel_range;
856extern unsigned long xcall_fetch_glob_regs;
857extern unsigned long xcall_fetch_glob_pmu;
858extern unsigned long xcall_fetch_glob_pmu_n4;
859extern unsigned long xcall_receive_signal;
860extern unsigned long xcall_new_mmu_context_version;
861#ifdef CONFIG_KGDB
862extern unsigned long xcall_kgdb_capture;
863#endif
864
865#ifdef DCACHE_ALIASING_POSSIBLE
866extern unsigned long xcall_flush_dcache_page_cheetah;
867#endif
868extern unsigned long xcall_flush_dcache_page_spitfire;
869
870#ifdef CONFIG_DEBUG_DCFLUSH
871extern atomic_t dcpage_flushes;
872extern atomic_t dcpage_flushes_xcall;
873#endif
874
875static inline void __local_flush_dcache_page(struct page *page)
876{
877#ifdef DCACHE_ALIASING_POSSIBLE
878 __flush_dcache_page(page_address(page),
879 ((tlb_type == spitfire) &&
880 page_mapping(page) != NULL));
881#else
882 if (page_mapping(page) != NULL &&
883 tlb_type == spitfire)
884 __flush_icache_page(__pa(page_address(page)));
885#endif
886}
887
888void smp_flush_dcache_page_impl(struct page *page, int cpu)
889{
890 int this_cpu;
891
892 if (tlb_type == hypervisor)
893 return;
894
895#ifdef CONFIG_DEBUG_DCFLUSH
896 atomic_inc(&dcpage_flushes);
897#endif
898
899 this_cpu = get_cpu();
900
901 if (cpu == this_cpu) {
902 __local_flush_dcache_page(page);
903 } else if (cpu_online(cpu)) {
904 void *pg_addr = page_address(page);
905 u64 data0 = 0;
906
907 if (tlb_type == spitfire) {
908 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
909 if (page_mapping(page) != NULL)
910 data0 |= ((u64)1 << 32);
911 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
912#ifdef DCACHE_ALIASING_POSSIBLE
913 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
914#endif
915 }
916 if (data0) {
917 xcall_deliver(data0, __pa(pg_addr),
918 (u64) pg_addr, cpumask_of(cpu));
919#ifdef CONFIG_DEBUG_DCFLUSH
920 atomic_inc(&dcpage_flushes_xcall);
921#endif
922 }
923 }
924
925 put_cpu();
926}
927
928void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
929{
930 void *pg_addr;
931 u64 data0;
932
933 if (tlb_type == hypervisor)
934 return;
935
936 preempt_disable();
937
938#ifdef CONFIG_DEBUG_DCFLUSH
939 atomic_inc(&dcpage_flushes);
940#endif
941 data0 = 0;
942 pg_addr = page_address(page);
943 if (tlb_type == spitfire) {
944 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
945 if (page_mapping(page) != NULL)
946 data0 |= ((u64)1 << 32);
947 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
948#ifdef DCACHE_ALIASING_POSSIBLE
949 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
950#endif
951 }
952 if (data0) {
953 xcall_deliver(data0, __pa(pg_addr),
954 (u64) pg_addr, cpu_online_mask);
955#ifdef CONFIG_DEBUG_DCFLUSH
956 atomic_inc(&dcpage_flushes_xcall);
957#endif
958 }
959 __local_flush_dcache_page(page);
960
961 preempt_enable();
962}
963
964void __irq_entry smp_new_mmu_context_version_client(int irq, struct pt_regs *regs)
965{
966 struct mm_struct *mm;
967 unsigned long flags;
968
969 clear_softint(1 << irq);
970
971 /* See if we need to allocate a new TLB context because
972 * the version of the one we are using is now out of date.
973 */
974 mm = current->active_mm;
975 if (unlikely(!mm || (mm == &init_mm)))
976 return;
977
978 spin_lock_irqsave(&mm->context.lock, flags);
979
980 if (unlikely(!CTX_VALID(mm->context)))
981 get_new_mmu_context(mm);
982
983 spin_unlock_irqrestore(&mm->context.lock, flags);
984
985 load_secondary_context(mm);
986 __flush_tlb_mm(CTX_HWBITS(mm->context),
987 SECONDARY_CONTEXT);
988}
989
990void smp_new_mmu_context_version(void)
991{
992 smp_cross_call(&xcall_new_mmu_context_version, 0, 0, 0);
993}
994
995#ifdef CONFIG_KGDB
996void kgdb_roundup_cpus(unsigned long flags)
997{
998 smp_cross_call(&xcall_kgdb_capture, 0, 0, 0);
999}
1000#endif
1001
1002void smp_fetch_global_regs(void)
1003{
1004 smp_cross_call(&xcall_fetch_glob_regs, 0, 0, 0);
1005}
1006
1007void smp_fetch_global_pmu(void)
1008{
1009 if (tlb_type == hypervisor &&
1010 sun4v_chip_type >= SUN4V_CHIP_NIAGARA4)
1011 smp_cross_call(&xcall_fetch_glob_pmu_n4, 0, 0, 0);
1012 else
1013 smp_cross_call(&xcall_fetch_glob_pmu, 0, 0, 0);
1014}
1015
1016/* We know that the window frames of the user have been flushed
1017 * to the stack before we get here because all callers of us
1018 * are flush_tlb_*() routines, and these run after flush_cache_*()
1019 * which performs the flushw.
1020 *
1021 * The SMP TLB coherency scheme we use works as follows:
1022 *
1023 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
1024 * space has (potentially) executed on, this is the heuristic
1025 * we use to avoid doing cross calls.
1026 *
1027 * Also, for flushing from kswapd and also for clones, we
1028 * use cpu_vm_mask as the list of cpus to make run the TLB.
1029 *
1030 * 2) TLB context numbers are shared globally across all processors
1031 * in the system, this allows us to play several games to avoid
1032 * cross calls.
1033 *
1034 * One invariant is that when a cpu switches to a process, and
1035 * that processes tsk->active_mm->cpu_vm_mask does not have the
1036 * current cpu's bit set, that tlb context is flushed locally.
1037 *
1038 * If the address space is non-shared (ie. mm->count == 1) we avoid
1039 * cross calls when we want to flush the currently running process's
1040 * tlb state. This is done by clearing all cpu bits except the current
1041 * processor's in current->mm->cpu_vm_mask and performing the
1042 * flush locally only. This will force any subsequent cpus which run
1043 * this task to flush the context from the local tlb if the process
1044 * migrates to another cpu (again).
1045 *
1046 * 3) For shared address spaces (threads) and swapping we bite the
1047 * bullet for most cases and perform the cross call (but only to
1048 * the cpus listed in cpu_vm_mask).
1049 *
1050 * The performance gain from "optimizing" away the cross call for threads is
1051 * questionable (in theory the big win for threads is the massive sharing of
1052 * address space state across processors).
1053 */
1054
1055/* This currently is only used by the hugetlb arch pre-fault
1056 * hook on UltraSPARC-III+ and later when changing the pagesize
1057 * bits of the context register for an address space.
1058 */
1059void smp_flush_tlb_mm(struct mm_struct *mm)
1060{
1061 u32 ctx = CTX_HWBITS(mm->context);
1062 int cpu = get_cpu();
1063
1064 if (atomic_read(&mm->mm_users) == 1) {
1065 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1066 goto local_flush_and_out;
1067 }
1068
1069 smp_cross_call_masked(&xcall_flush_tlb_mm,
1070 ctx, 0, 0,
1071 mm_cpumask(mm));
1072
1073local_flush_and_out:
1074 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
1075
1076 put_cpu();
1077}
1078
1079struct tlb_pending_info {
1080 unsigned long ctx;
1081 unsigned long nr;
1082 unsigned long *vaddrs;
1083};
1084
1085static void tlb_pending_func(void *info)
1086{
1087 struct tlb_pending_info *t = info;
1088
1089 __flush_tlb_pending(t->ctx, t->nr, t->vaddrs);
1090}
1091
1092void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
1093{
1094 u32 ctx = CTX_HWBITS(mm->context);
1095 struct tlb_pending_info info;
1096 int cpu = get_cpu();
1097
1098 info.ctx = ctx;
1099 info.nr = nr;
1100 info.vaddrs = vaddrs;
1101
1102 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1103 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1104 else
1105 smp_call_function_many(mm_cpumask(mm), tlb_pending_func,
1106 &info, 1);
1107
1108 __flush_tlb_pending(ctx, nr, vaddrs);
1109
1110 put_cpu();
1111}
1112
1113void smp_flush_tlb_page(struct mm_struct *mm, unsigned long vaddr)
1114{
1115 unsigned long context = CTX_HWBITS(mm->context);
1116 int cpu = get_cpu();
1117
1118 if (mm == current->mm && atomic_read(&mm->mm_users) == 1)
1119 cpumask_copy(mm_cpumask(mm), cpumask_of(cpu));
1120 else
1121 smp_cross_call_masked(&xcall_flush_tlb_page,
1122 context, vaddr, 0,
1123 mm_cpumask(mm));
1124 __flush_tlb_page(context, vaddr);
1125
1126 put_cpu();
1127}
1128
1129void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
1130{
1131 start &= PAGE_MASK;
1132 end = PAGE_ALIGN(end);
1133 if (start != end) {
1134 smp_cross_call(&xcall_flush_tlb_kernel_range,
1135 0, start, end);
1136
1137 __flush_tlb_kernel_range(start, end);
1138 }
1139}
1140
1141/* CPU capture. */
1142/* #define CAPTURE_DEBUG */
1143extern unsigned long xcall_capture;
1144
1145static atomic_t smp_capture_depth = ATOMIC_INIT(0);
1146static atomic_t smp_capture_registry = ATOMIC_INIT(0);
1147static unsigned long penguins_are_doing_time;
1148
1149void smp_capture(void)
1150{
1151 int result = atomic_add_ret(1, &smp_capture_depth);
1152
1153 if (result == 1) {
1154 int ncpus = num_online_cpus();
1155
1156#ifdef CAPTURE_DEBUG
1157 printk("CPU[%d]: Sending penguins to jail...",
1158 smp_processor_id());
1159#endif
1160 penguins_are_doing_time = 1;
1161 atomic_inc(&smp_capture_registry);
1162 smp_cross_call(&xcall_capture, 0, 0, 0);
1163 while (atomic_read(&smp_capture_registry) != ncpus)
1164 rmb();
1165#ifdef CAPTURE_DEBUG
1166 printk("done\n");
1167#endif
1168 }
1169}
1170
1171void smp_release(void)
1172{
1173 if (atomic_dec_and_test(&smp_capture_depth)) {
1174#ifdef CAPTURE_DEBUG
1175 printk("CPU[%d]: Giving pardon to "
1176 "imprisoned penguins\n",
1177 smp_processor_id());
1178#endif
1179 penguins_are_doing_time = 0;
1180 membar_safe("#StoreLoad");
1181 atomic_dec(&smp_capture_registry);
1182 }
1183}
1184
1185/* Imprisoned penguins run with %pil == PIL_NORMAL_MAX, but PSTATE_IE
1186 * set, so they can service tlb flush xcalls...
1187 */
1188extern void prom_world(int);
1189
1190void __irq_entry smp_penguin_jailcell(int irq, struct pt_regs *regs)
1191{
1192 clear_softint(1 << irq);
1193
1194 preempt_disable();
1195
1196 __asm__ __volatile__("flushw");
1197 prom_world(1);
1198 atomic_inc(&smp_capture_registry);
1199 membar_safe("#StoreLoad");
1200 while (penguins_are_doing_time)
1201 rmb();
1202 atomic_dec(&smp_capture_registry);
1203 prom_world(0);
1204
1205 preempt_enable();
1206}
1207
1208/* /proc/profile writes can call this, don't __init it please. */
1209int setup_profiling_timer(unsigned int multiplier)
1210{
1211 return -EINVAL;
1212}
1213
1214void __init smp_prepare_cpus(unsigned int max_cpus)
1215{
1216}
1217
1218void smp_prepare_boot_cpu(void)
1219{
1220}
1221
1222void __init smp_setup_processor_id(void)
1223{
1224 if (tlb_type == spitfire)
1225 xcall_deliver_impl = spitfire_xcall_deliver;
1226 else if (tlb_type == cheetah || tlb_type == cheetah_plus)
1227 xcall_deliver_impl = cheetah_xcall_deliver;
1228 else
1229 xcall_deliver_impl = hypervisor_xcall_deliver;
1230}
1231
1232void smp_fill_in_sib_core_maps(void)
1233{
1234 unsigned int i;
1235
1236 for_each_present_cpu(i) {
1237 unsigned int j;
1238
1239 cpumask_clear(&cpu_core_map[i]);
1240 if (cpu_data(i).core_id == 0) {
1241 cpumask_set_cpu(i, &cpu_core_map[i]);
1242 continue;
1243 }
1244
1245 for_each_present_cpu(j) {
1246 if (cpu_data(i).core_id ==
1247 cpu_data(j).core_id)
1248 cpumask_set_cpu(j, &cpu_core_map[i]);
1249 }
1250 }
1251
1252 for_each_present_cpu(i) {
1253 unsigned int j;
1254
1255 cpumask_clear(&per_cpu(cpu_sibling_map, i));
1256 if (cpu_data(i).proc_id == -1) {
1257 cpumask_set_cpu(i, &per_cpu(cpu_sibling_map, i));
1258 continue;
1259 }
1260
1261 for_each_present_cpu(j) {
1262 if (cpu_data(i).proc_id ==
1263 cpu_data(j).proc_id)
1264 cpumask_set_cpu(j, &per_cpu(cpu_sibling_map, i));
1265 }
1266 }
1267}
1268
1269int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1270{
1271 int ret = smp_boot_one_cpu(cpu, tidle);
1272
1273 if (!ret) {
1274 cpumask_set_cpu(cpu, &smp_commenced_mask);
1275 while (!cpu_online(cpu))
1276 mb();
1277 if (!cpu_online(cpu)) {
1278 ret = -ENODEV;
1279 } else {
1280 /* On SUN4V, writes to %tick and %stick are
1281 * not allowed.
1282 */
1283 if (tlb_type != hypervisor)
1284 smp_synchronize_one_tick(cpu);
1285 }
1286 }
1287 return ret;
1288}
1289
1290#ifdef CONFIG_HOTPLUG_CPU
1291void cpu_play_dead(void)
1292{
1293 int cpu = smp_processor_id();
1294 unsigned long pstate;
1295
1296 idle_task_exit();
1297
1298 if (tlb_type == hypervisor) {
1299 struct trap_per_cpu *tb = &trap_block[cpu];
1300
1301 sun4v_cpu_qconf(HV_CPU_QUEUE_CPU_MONDO,
1302 tb->cpu_mondo_pa, 0);
1303 sun4v_cpu_qconf(HV_CPU_QUEUE_DEVICE_MONDO,
1304 tb->dev_mondo_pa, 0);
1305 sun4v_cpu_qconf(HV_CPU_QUEUE_RES_ERROR,
1306 tb->resum_mondo_pa, 0);
1307 sun4v_cpu_qconf(HV_CPU_QUEUE_NONRES_ERROR,
1308 tb->nonresum_mondo_pa, 0);
1309 }
1310
1311 cpumask_clear_cpu(cpu, &smp_commenced_mask);
1312 membar_safe("#Sync");
1313
1314 local_irq_disable();
1315
1316 __asm__ __volatile__(
1317 "rdpr %%pstate, %0\n\t"
1318 "wrpr %0, %1, %%pstate"
1319 : "=r" (pstate)
1320 : "i" (PSTATE_IE));
1321
1322 while (1)
1323 barrier();
1324}
1325
1326int __cpu_disable(void)
1327{
1328 int cpu = smp_processor_id();
1329 cpuinfo_sparc *c;
1330 int i;
1331
1332 for_each_cpu(i, &cpu_core_map[cpu])
1333 cpumask_clear_cpu(cpu, &cpu_core_map[i]);
1334 cpumask_clear(&cpu_core_map[cpu]);
1335
1336 for_each_cpu(i, &per_cpu(cpu_sibling_map, cpu))
1337 cpumask_clear_cpu(cpu, &per_cpu(cpu_sibling_map, i));
1338 cpumask_clear(&per_cpu(cpu_sibling_map, cpu));
1339
1340 c = &cpu_data(cpu);
1341
1342 c->core_id = 0;
1343 c->proc_id = -1;
1344
1345 smp_wmb();
1346
1347 /* Make sure no interrupts point to this cpu. */
1348 fixup_irqs();
1349
1350 local_irq_enable();
1351 mdelay(1);
1352 local_irq_disable();
1353
1354 set_cpu_online(cpu, false);
1355
1356 cpu_map_rebuild();
1357
1358 return 0;
1359}
1360
1361void __cpu_die(unsigned int cpu)
1362{
1363 int i;
1364
1365 for (i = 0; i < 100; i++) {
1366 smp_rmb();
1367 if (!cpumask_test_cpu(cpu, &smp_commenced_mask))
1368 break;
1369 msleep(100);
1370 }
1371 if (cpumask_test_cpu(cpu, &smp_commenced_mask)) {
1372 printk(KERN_ERR "CPU %u didn't die...\n", cpu);
1373 } else {
1374#if defined(CONFIG_SUN_LDOMS)
1375 unsigned long hv_err;
1376 int limit = 100;
1377
1378 do {
1379 hv_err = sun4v_cpu_stop(cpu);
1380 if (hv_err == HV_EOK) {
1381 set_cpu_present(cpu, false);
1382 break;
1383 }
1384 } while (--limit > 0);
1385 if (limit <= 0) {
1386 printk(KERN_ERR "sun4v_cpu_stop() fails err=%lu\n",
1387 hv_err);
1388 }
1389#endif
1390 }
1391}
1392#endif
1393
1394void __init smp_cpus_done(unsigned int max_cpus)
1395{
1396 pcr_arch_init();
1397}
1398
1399void smp_send_reschedule(int cpu)
1400{
1401 if (cpu == smp_processor_id()) {
1402 WARN_ON_ONCE(preemptible());
1403 set_softint(1 << PIL_SMP_RECEIVE_SIGNAL);
1404 } else {
1405 xcall_deliver((u64) &xcall_receive_signal,
1406 0, 0, cpumask_of(cpu));
1407 }
1408}
1409
1410void __irq_entry smp_receive_signal_client(int irq, struct pt_regs *regs)
1411{
1412 clear_softint(1 << irq);
1413 scheduler_ipi();
1414}
1415
1416/* This is a nop because we capture all other cpus
1417 * anyways when making the PROM active.
1418 */
1419void smp_send_stop(void)
1420{
1421}
1422
1423/**
1424 * pcpu_alloc_bootmem - NUMA friendly alloc_bootmem wrapper for percpu
1425 * @cpu: cpu to allocate for
1426 * @size: size allocation in bytes
1427 * @align: alignment
1428 *
1429 * Allocate @size bytes aligned at @align for cpu @cpu. This wrapper
1430 * does the right thing for NUMA regardless of the current
1431 * configuration.
1432 *
1433 * RETURNS:
1434 * Pointer to the allocated area on success, NULL on failure.
1435 */
1436static void * __init pcpu_alloc_bootmem(unsigned int cpu, size_t size,
1437 size_t align)
1438{
1439 const unsigned long goal = __pa(MAX_DMA_ADDRESS);
1440#ifdef CONFIG_NEED_MULTIPLE_NODES
1441 int node = cpu_to_node(cpu);
1442 void *ptr;
1443
1444 if (!node_online(node) || !NODE_DATA(node)) {
1445 ptr = __alloc_bootmem(size, align, goal);
1446 pr_info("cpu %d has no node %d or node-local memory\n",
1447 cpu, node);
1448 pr_debug("per cpu data for cpu%d %lu bytes at %016lx\n",
1449 cpu, size, __pa(ptr));
1450 } else {
1451 ptr = __alloc_bootmem_node(NODE_DATA(node),
1452 size, align, goal);
1453 pr_debug("per cpu data for cpu%d %lu bytes on node%d at "
1454 "%016lx\n", cpu, size, node, __pa(ptr));
1455 }
1456 return ptr;
1457#else
1458 return __alloc_bootmem(size, align, goal);
1459#endif
1460}
1461
1462static void __init pcpu_free_bootmem(void *ptr, size_t size)
1463{
1464 free_bootmem(__pa(ptr), size);
1465}
1466
1467static int __init pcpu_cpu_distance(unsigned int from, unsigned int to)
1468{
1469 if (cpu_to_node(from) == cpu_to_node(to))
1470 return LOCAL_DISTANCE;
1471 else
1472 return REMOTE_DISTANCE;
1473}
1474
1475static void __init pcpu_populate_pte(unsigned long addr)
1476{
1477 pgd_t *pgd = pgd_offset_k(addr);
1478 pud_t *pud;
1479 pmd_t *pmd;
1480
1481 pud = pud_offset(pgd, addr);
1482 if (pud_none(*pud)) {
1483 pmd_t *new;
1484
1485 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1486 pud_populate(&init_mm, pud, new);
1487 }
1488
1489 pmd = pmd_offset(pud, addr);
1490 if (!pmd_present(*pmd)) {
1491 pte_t *new;
1492
1493 new = __alloc_bootmem(PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1494 pmd_populate_kernel(&init_mm, pmd, new);
1495 }
1496}
1497
1498void __init setup_per_cpu_areas(void)
1499{
1500 unsigned long delta;
1501 unsigned int cpu;
1502 int rc = -EINVAL;
1503
1504 if (pcpu_chosen_fc != PCPU_FC_PAGE) {
1505 rc = pcpu_embed_first_chunk(PERCPU_MODULE_RESERVE,
1506 PERCPU_DYNAMIC_RESERVE, 4 << 20,
1507 pcpu_cpu_distance,
1508 pcpu_alloc_bootmem,
1509 pcpu_free_bootmem);
1510 if (rc)
1511 pr_warning("PERCPU: %s allocator failed (%d), "
1512 "falling back to page size\n",
1513 pcpu_fc_names[pcpu_chosen_fc], rc);
1514 }
1515 if (rc < 0)
1516 rc = pcpu_page_first_chunk(PERCPU_MODULE_RESERVE,
1517 pcpu_alloc_bootmem,
1518 pcpu_free_bootmem,
1519 pcpu_populate_pte);
1520 if (rc < 0)
1521 panic("cannot initialize percpu area (err=%d)", rc);
1522
1523 delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
1524 for_each_possible_cpu(cpu)
1525 __per_cpu_offset(cpu) = delta + pcpu_unit_offsets[cpu];
1526
1527 /* Setup %g5 for the boot cpu. */
1528 __local_per_cpu_offset = __per_cpu_offset(smp_processor_id());
1529
1530 of_fill_in_cpu_data();
1531 if (tlb_type == hypervisor)
1532 mdesc_fill_in_cpu_data(cpu_all_mask);
1533}