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1/*
2 * OpenRISC time.c
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/kernel.h>
18#include <linux/time.h>
19#include <linux/timex.h>
20#include <linux/interrupt.h>
21#include <linux/ftrace.h>
22
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27
28#include <asm/cpuinfo.h>
29
30static int openrisc_timer_set_next_event(unsigned long delta,
31 struct clock_event_device *dev)
32{
33 u32 c;
34
35 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
36 * We're guaranteed delta won't be bigger than 28 bits because the
37 * generic timekeeping code ensures that for us.
38 */
39 c = mfspr(SPR_TTCR);
40 c += delta;
41 c &= SPR_TTMR_TP;
42
43 /* Set counter and enable interrupt.
44 * Keep timer in continuous mode always.
45 */
46 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
47
48 return 0;
49}
50
51static void openrisc_timer_set_mode(enum clock_event_mode mode,
52 struct clock_event_device *evt)
53{
54 switch (mode) {
55 case CLOCK_EVT_MODE_PERIODIC:
56 pr_debug(KERN_INFO "%s: periodic\n", __func__);
57 BUG();
58 break;
59 case CLOCK_EVT_MODE_ONESHOT:
60 pr_debug(KERN_INFO "%s: oneshot\n", __func__);
61 break;
62 case CLOCK_EVT_MODE_UNUSED:
63 pr_debug(KERN_INFO "%s: unused\n", __func__);
64 break;
65 case CLOCK_EVT_MODE_SHUTDOWN:
66 pr_debug(KERN_INFO "%s: shutdown\n", __func__);
67 break;
68 case CLOCK_EVT_MODE_RESUME:
69 pr_debug(KERN_INFO "%s: resume\n", __func__);
70 break;
71 }
72}
73
74/* This is the clock event device based on the OR1K tick timer.
75 * As the timer is being used as a continuous clock-source (required for HR
76 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
77 * one-shot events, so no problem.
78 */
79
80static struct clock_event_device clockevent_openrisc_timer = {
81 .name = "openrisc_timer_clockevent",
82 .features = CLOCK_EVT_FEAT_ONESHOT,
83 .rating = 300,
84 .set_next_event = openrisc_timer_set_next_event,
85 .set_mode = openrisc_timer_set_mode,
86};
87
88static inline void timer_ack(void)
89{
90 /* Clear the IP bit and disable further interrupts */
91 /* This can be done very simply... we just need to keep the timer
92 running, so just maintain the CR bits while clearing the rest
93 of the register
94 */
95 mtspr(SPR_TTMR, SPR_TTMR_CR);
96}
97
98/*
99 * The timer interrupt is mostly handled in generic code nowadays... this
100 * function just acknowledges the interrupt and fires the event handler that
101 * has been set on the clockevent device by the generic time management code.
102 *
103 * This function needs to be called by the timer exception handler and that's
104 * all the exception handler needs to do.
105 */
106
107irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
108{
109 struct pt_regs *old_regs = set_irq_regs(regs);
110 struct clock_event_device *evt = &clockevent_openrisc_timer;
111
112 timer_ack();
113
114 /*
115 * update_process_times() expects us to have called irq_enter().
116 */
117 irq_enter();
118 evt->event_handler(evt);
119 irq_exit();
120
121 set_irq_regs(old_regs);
122
123 return IRQ_HANDLED;
124}
125
126static __init void openrisc_clockevent_init(void)
127{
128 clockevents_calc_mult_shift(&clockevent_openrisc_timer,
129 cpuinfo.clock_frequency, 4);
130
131 /* We only have 28 bits */
132 clockevent_openrisc_timer.max_delta_ns =
133 clockevent_delta2ns((u32) 0x0fffffff, &clockevent_openrisc_timer);
134 clockevent_openrisc_timer.min_delta_ns =
135 clockevent_delta2ns(1, &clockevent_openrisc_timer);
136 clockevent_openrisc_timer.cpumask = cpumask_of(0);
137 clockevents_register_device(&clockevent_openrisc_timer);
138}
139
140/**
141 * Clocksource: Based on OpenRISC timer/counter
142 *
143 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
144 * is 32 bits wide and runs at the CPU clock frequency.
145 */
146
147static cycle_t openrisc_timer_read(struct clocksource *cs)
148{
149 return (cycle_t) mfspr(SPR_TTCR);
150}
151
152static struct clocksource openrisc_timer = {
153 .name = "openrisc_timer",
154 .rating = 200,
155 .read = openrisc_timer_read,
156 .mask = CLOCKSOURCE_MASK(32),
157 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
158};
159
160static int __init openrisc_timer_init(void)
161{
162 if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
163 panic("failed to register clocksource");
164
165 /* Enable the incrementer: 'continuous' mode with interrupt disabled */
166 mtspr(SPR_TTMR, SPR_TTMR_CR);
167
168 return 0;
169}
170
171void __init time_init(void)
172{
173 u32 upr;
174
175 upr = mfspr(SPR_UPR);
176 if (!(upr & SPR_UPR_TTP))
177 panic("Linux not supported on devices without tick timer");
178
179 openrisc_timer_init();
180 openrisc_clockevent_init();
181}
1/*
2 * OpenRISC time.c
3 *
4 * Linux architectural port borrowing liberally from similar works of
5 * others. All original copyrights apply as per the original source
6 * declaration.
7 *
8 * Modifications for the OpenRISC architecture:
9 * Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
15 */
16
17#include <linux/kernel.h>
18#include <linux/time.h>
19#include <linux/timex.h>
20#include <linux/interrupt.h>
21#include <linux/ftrace.h>
22
23#include <linux/clocksource.h>
24#include <linux/clockchips.h>
25#include <linux/irq.h>
26#include <linux/io.h>
27
28#include <asm/cpuinfo.h>
29
30static int openrisc_timer_set_next_event(unsigned long delta,
31 struct clock_event_device *dev)
32{
33 u32 c;
34
35 /* Read 32-bit counter value, add delta, mask off the low 28 bits.
36 * We're guaranteed delta won't be bigger than 28 bits because the
37 * generic timekeeping code ensures that for us.
38 */
39 c = mfspr(SPR_TTCR);
40 c += delta;
41 c &= SPR_TTMR_TP;
42
43 /* Set counter and enable interrupt.
44 * Keep timer in continuous mode always.
45 */
46 mtspr(SPR_TTMR, SPR_TTMR_CR | SPR_TTMR_IE | c);
47
48 return 0;
49}
50
51static void openrisc_timer_set_mode(enum clock_event_mode mode,
52 struct clock_event_device *evt)
53{
54 switch (mode) {
55 case CLOCK_EVT_MODE_PERIODIC:
56 pr_debug(KERN_INFO "%s: periodic\n", __func__);
57 BUG();
58 break;
59 case CLOCK_EVT_MODE_ONESHOT:
60 pr_debug(KERN_INFO "%s: oneshot\n", __func__);
61 break;
62 case CLOCK_EVT_MODE_UNUSED:
63 pr_debug(KERN_INFO "%s: unused\n", __func__);
64 break;
65 case CLOCK_EVT_MODE_SHUTDOWN:
66 pr_debug(KERN_INFO "%s: shutdown\n", __func__);
67 break;
68 case CLOCK_EVT_MODE_RESUME:
69 pr_debug(KERN_INFO "%s: resume\n", __func__);
70 break;
71 }
72}
73
74/* This is the clock event device based on the OR1K tick timer.
75 * As the timer is being used as a continuous clock-source (required for HR
76 * timers) we cannot enable the PERIODIC feature. The tick timer can run using
77 * one-shot events, so no problem.
78 */
79
80static struct clock_event_device clockevent_openrisc_timer = {
81 .name = "openrisc_timer_clockevent",
82 .features = CLOCK_EVT_FEAT_ONESHOT,
83 .rating = 300,
84 .set_next_event = openrisc_timer_set_next_event,
85 .set_mode = openrisc_timer_set_mode,
86};
87
88static inline void timer_ack(void)
89{
90 /* Clear the IP bit and disable further interrupts */
91 /* This can be done very simply... we just need to keep the timer
92 running, so just maintain the CR bits while clearing the rest
93 of the register
94 */
95 mtspr(SPR_TTMR, SPR_TTMR_CR);
96}
97
98/*
99 * The timer interrupt is mostly handled in generic code nowadays... this
100 * function just acknowledges the interrupt and fires the event handler that
101 * has been set on the clockevent device by the generic time management code.
102 *
103 * This function needs to be called by the timer exception handler and that's
104 * all the exception handler needs to do.
105 */
106
107irqreturn_t __irq_entry timer_interrupt(struct pt_regs *regs)
108{
109 struct pt_regs *old_regs = set_irq_regs(regs);
110 struct clock_event_device *evt = &clockevent_openrisc_timer;
111
112 timer_ack();
113
114 /*
115 * update_process_times() expects us to have called irq_enter().
116 */
117 irq_enter();
118 evt->event_handler(evt);
119 irq_exit();
120
121 set_irq_regs(old_regs);
122
123 return IRQ_HANDLED;
124}
125
126static __init void openrisc_clockevent_init(void)
127{
128 clockevent_openrisc_timer.cpumask = cpumask_of(0);
129
130 /* We only have 28 bits */
131 clockevents_config_and_register(&clockevent_openrisc_timer,
132 cpuinfo.clock_frequency,
133 100, 0x0fffffff);
134
135}
136
137/**
138 * Clocksource: Based on OpenRISC timer/counter
139 *
140 * This sets up the OpenRISC Tick Timer as a clock source. The tick timer
141 * is 32 bits wide and runs at the CPU clock frequency.
142 */
143
144static cycle_t openrisc_timer_read(struct clocksource *cs)
145{
146 return (cycle_t) mfspr(SPR_TTCR);
147}
148
149static struct clocksource openrisc_timer = {
150 .name = "openrisc_timer",
151 .rating = 200,
152 .read = openrisc_timer_read,
153 .mask = CLOCKSOURCE_MASK(32),
154 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
155};
156
157static int __init openrisc_timer_init(void)
158{
159 if (clocksource_register_hz(&openrisc_timer, cpuinfo.clock_frequency))
160 panic("failed to register clocksource");
161
162 /* Enable the incrementer: 'continuous' mode with interrupt disabled */
163 mtspr(SPR_TTMR, SPR_TTMR_CR);
164
165 return 0;
166}
167
168void __init time_init(void)
169{
170 u32 upr;
171
172 upr = mfspr(SPR_UPR);
173 if (!(upr & SPR_UPR_TTP))
174 panic("Linux not supported on devices without tick timer");
175
176 openrisc_timer_init();
177 openrisc_clockevent_init();
178}