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1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/vmalloc.h>
16#include <linux/platform_device.h>
17
18#include <asm/pci.h>
19#include <asm/gpio.h>
20#include <asm/addrspace.h>
21
22#include <lantiq_soc.h>
23#include <lantiq_irq.h>
24#include <lantiq_platform.h>
25
26#include "pci-lantiq.h"
27
28#define LTQ_PCI_CFG_BASE 0x17000000
29#define LTQ_PCI_CFG_SIZE 0x00008000
30#define LTQ_PCI_MEM_BASE 0x18000000
31#define LTQ_PCI_MEM_SIZE 0x02000000
32#define LTQ_PCI_IO_BASE 0x1AE00000
33#define LTQ_PCI_IO_SIZE 0x00200000
34
35#define PCI_CR_FCI_ADDR_MAP0 0x00C0
36#define PCI_CR_FCI_ADDR_MAP1 0x00C4
37#define PCI_CR_FCI_ADDR_MAP2 0x00C8
38#define PCI_CR_FCI_ADDR_MAP3 0x00CC
39#define PCI_CR_FCI_ADDR_MAP4 0x00D0
40#define PCI_CR_FCI_ADDR_MAP5 0x00D4
41#define PCI_CR_FCI_ADDR_MAP6 0x00D8
42#define PCI_CR_FCI_ADDR_MAP7 0x00DC
43#define PCI_CR_CLK_CTRL 0x0000
44#define PCI_CR_PCI_MOD 0x0030
45#define PCI_CR_PC_ARB 0x0080
46#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
47#define PCI_CR_BAR11MASK 0x0044
48#define PCI_CR_BAR12MASK 0x0048
49#define PCI_CR_BAR13MASK 0x004C
50#define PCI_CS_BASE_ADDR1 0x0010
51#define PCI_CR_PCI_ADDR_MAP11 0x0064
52#define PCI_CR_FCI_BURST_LENGTH 0x00E8
53#define PCI_CR_PCI_EOI 0x002C
54#define PCI_CS_STS_CMD 0x0004
55
56#define PCI_MASTER0_REQ_MASK_2BITS 8
57#define PCI_MASTER1_REQ_MASK_2BITS 10
58#define PCI_MASTER2_REQ_MASK_2BITS 12
59#define INTERNAL_ARB_ENABLE_BIT 0
60
61#define LTQ_CGU_IFCCR 0x0018
62#define LTQ_CGU_PCICR 0x0034
63
64#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
65#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
66
67#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
68#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
69
70struct ltq_pci_gpio_map {
71 int pin;
72 int alt0;
73 int alt1;
74 int dir;
75 char *name;
76};
77
78/* the pci core can make use of the following gpios */
79static struct ltq_pci_gpio_map ltq_pci_gpio_map[] = {
80 { 0, 1, 0, 0, "pci-exin0" },
81 { 1, 1, 0, 0, "pci-exin1" },
82 { 2, 1, 0, 0, "pci-exin2" },
83 { 39, 1, 0, 0, "pci-exin3" },
84 { 10, 1, 0, 0, "pci-exin4" },
85 { 9, 1, 0, 0, "pci-exin5" },
86 { 30, 1, 0, 1, "pci-gnt1" },
87 { 23, 1, 0, 1, "pci-gnt2" },
88 { 19, 1, 0, 1, "pci-gnt3" },
89 { 38, 1, 0, 1, "pci-gnt4" },
90 { 29, 1, 0, 0, "pci-req1" },
91 { 31, 1, 0, 0, "pci-req2" },
92 { 3, 1, 0, 0, "pci-req3" },
93 { 37, 1, 0, 0, "pci-req4" },
94};
95
96__iomem void *ltq_pci_mapped_cfg;
97static __iomem void *ltq_pci_membase;
98
99int (*ltqpci_plat_dev_init)(struct pci_dev *dev) = NULL;
100
101/* Since the PCI REQ pins can be reused for other functionality, make it
102 possible to exclude those from interpretation by the PCI controller */
103static int ltq_pci_req_mask = 0xf;
104
105static int *ltq_pci_irq_map;
106
107struct pci_ops ltq_pci_ops = {
108 .read = ltq_pci_read_config_dword,
109 .write = ltq_pci_write_config_dword
110};
111
112static struct resource pci_io_resource = {
113 .name = "pci io space",
114 .start = LTQ_PCI_IO_BASE,
115 .end = LTQ_PCI_IO_BASE + LTQ_PCI_IO_SIZE - 1,
116 .flags = IORESOURCE_IO
117};
118
119static struct resource pci_mem_resource = {
120 .name = "pci memory space",
121 .start = LTQ_PCI_MEM_BASE,
122 .end = LTQ_PCI_MEM_BASE + LTQ_PCI_MEM_SIZE - 1,
123 .flags = IORESOURCE_MEM
124};
125
126static struct pci_controller ltq_pci_controller = {
127 .pci_ops = <q_pci_ops,
128 .mem_resource = &pci_mem_resource,
129 .mem_offset = 0x00000000UL,
130 .io_resource = &pci_io_resource,
131 .io_offset = 0x00000000UL,
132};
133
134int pcibios_plat_dev_init(struct pci_dev *dev)
135{
136 if (ltqpci_plat_dev_init)
137 return ltqpci_plat_dev_init(dev);
138
139 return 0;
140}
141
142static u32 ltq_calc_bar11mask(void)
143{
144 u32 mem, bar11mask;
145
146 /* BAR11MASK value depends on available memory on system. */
147 mem = num_physpages * PAGE_SIZE;
148 bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
149
150 return bar11mask;
151}
152
153static void ltq_pci_setup_gpio(int gpio)
154{
155 int i;
156 for (i = 0; i < ARRAY_SIZE(ltq_pci_gpio_map); i++) {
157 if (gpio & (1 << i)) {
158 ltq_gpio_request(ltq_pci_gpio_map[i].pin,
159 ltq_pci_gpio_map[i].alt0,
160 ltq_pci_gpio_map[i].alt1,
161 ltq_pci_gpio_map[i].dir,
162 ltq_pci_gpio_map[i].name);
163 }
164 }
165 ltq_gpio_request(21, 0, 0, 1, "pci-reset");
166 ltq_pci_req_mask = (gpio >> PCI_REQ_SHIFT) & PCI_REQ_MASK;
167}
168
169static int __devinit ltq_pci_startup(struct ltq_pci_data *conf)
170{
171 u32 temp_buffer;
172
173 /* set clock to 33Mhz */
174 if (ltq_is_ar9()) {
175 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0x1f00000, LTQ_CGU_IFCCR);
176 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0xe00000, LTQ_CGU_IFCCR);
177 } else {
178 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~0xf00000, LTQ_CGU_IFCCR);
179 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | 0x800000, LTQ_CGU_IFCCR);
180 }
181
182 /* external or internal clock ? */
183 if (conf->clock) {
184 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) & ~(1 << 16),
185 LTQ_CGU_IFCCR);
186 ltq_cgu_w32((1 << 30), LTQ_CGU_PCICR);
187 } else {
188 ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | (1 << 16),
189 LTQ_CGU_IFCCR);
190 ltq_cgu_w32((1 << 31) | (1 << 30), LTQ_CGU_PCICR);
191 }
192
193 /* setup pci clock and gpis used by pci */
194 ltq_pci_setup_gpio(conf->gpio);
195
196 /* enable auto-switching between PCI and EBU */
197 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
198
199 /* busy, i.e. configuration is not done, PCI access has to be retried */
200 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
201 wmb();
202 /* BUS Master/IO/MEM access */
203 ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
204
205 /* enable external 2 PCI masters */
206 temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
207 temp_buffer &= (~(ltq_pci_req_mask << 16));
208 /* enable internal arbiter */
209 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
210 /* enable internal PCI master reqest */
211 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
212
213 /* enable EBU request */
214 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
215
216 /* enable all external masters request */
217 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
218 ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
219 wmb();
220
221 /* setup BAR memory regions */
222 ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
223 ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
224 ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
225 ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
226 ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
227 ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
228 ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
229 ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
230 ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
231 ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
232 ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
233 ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
234 /* both TX and RX endian swap are enabled */
235 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
236 wmb();
237 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
238 PCI_CR_BAR12MASK);
239 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
240 PCI_CR_BAR13MASK);
241 /*use 8 dw burst length */
242 ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
243 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
244 wmb();
245
246 /* setup irq line */
247 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
248 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
249
250 /* toggle reset pin */
251 __gpio_set_value(21, 0);
252 wmb();
253 mdelay(1);
254 __gpio_set_value(21, 1);
255 return 0;
256}
257
258int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
259{
260 if (ltq_pci_irq_map[slot])
261 return ltq_pci_irq_map[slot];
262 printk(KERN_ERR "lq_pci: trying to map irq for unknown slot %d\n",
263 slot);
264
265 return 0;
266}
267
268static int __devinit ltq_pci_probe(struct platform_device *pdev)
269{
270 struct ltq_pci_data *ltq_pci_data =
271 (struct ltq_pci_data *) pdev->dev.platform_data;
272 pci_probe_only = 0;
273 ltq_pci_irq_map = ltq_pci_data->irq;
274 ltq_pci_membase = ioremap_nocache(PCI_CR_BASE_ADDR, PCI_CR_SIZE);
275 ltq_pci_mapped_cfg =
276 ioremap_nocache(LTQ_PCI_CFG_BASE, LTQ_PCI_CFG_BASE);
277 ltq_pci_controller.io_map_base =
278 (unsigned long)ioremap(LTQ_PCI_IO_BASE, LTQ_PCI_IO_SIZE - 1);
279 ltq_pci_startup(ltq_pci_data);
280 register_pci_controller(<q_pci_controller);
281
282 return 0;
283}
284
285static struct platform_driver
286ltq_pci_driver = {
287 .probe = ltq_pci_probe,
288 .driver = {
289 .name = "ltq_pci",
290 .owner = THIS_MODULE,
291 },
292};
293
294int __init pcibios_init(void)
295{
296 int ret = platform_driver_register(<q_pci_driver);
297 if (ret)
298 printk(KERN_INFO "ltq_pci: Error registering platfom driver!");
299 return ret;
300}
301
302arch_initcall(pcibios_init);
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
7 */
8
9#include <linux/types.h>
10#include <linux/pci.h>
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/delay.h>
14#include <linux/mm.h>
15#include <linux/vmalloc.h>
16#include <linux/module.h>
17#include <linux/clk.h>
18#include <linux/of_platform.h>
19#include <linux/of_gpio.h>
20#include <linux/of_irq.h>
21#include <linux/of_pci.h>
22
23#include <asm/pci.h>
24#include <asm/gpio.h>
25#include <asm/addrspace.h>
26
27#include <lantiq_soc.h>
28#include <lantiq_irq.h>
29
30#include "pci-lantiq.h"
31
32#define PCI_CR_FCI_ADDR_MAP0 0x00C0
33#define PCI_CR_FCI_ADDR_MAP1 0x00C4
34#define PCI_CR_FCI_ADDR_MAP2 0x00C8
35#define PCI_CR_FCI_ADDR_MAP3 0x00CC
36#define PCI_CR_FCI_ADDR_MAP4 0x00D0
37#define PCI_CR_FCI_ADDR_MAP5 0x00D4
38#define PCI_CR_FCI_ADDR_MAP6 0x00D8
39#define PCI_CR_FCI_ADDR_MAP7 0x00DC
40#define PCI_CR_CLK_CTRL 0x0000
41#define PCI_CR_PCI_MOD 0x0030
42#define PCI_CR_PC_ARB 0x0080
43#define PCI_CR_FCI_ADDR_MAP11hg 0x00E4
44#define PCI_CR_BAR11MASK 0x0044
45#define PCI_CR_BAR12MASK 0x0048
46#define PCI_CR_BAR13MASK 0x004C
47#define PCI_CS_BASE_ADDR1 0x0010
48#define PCI_CR_PCI_ADDR_MAP11 0x0064
49#define PCI_CR_FCI_BURST_LENGTH 0x00E8
50#define PCI_CR_PCI_EOI 0x002C
51#define PCI_CS_STS_CMD 0x0004
52
53#define PCI_MASTER0_REQ_MASK_2BITS 8
54#define PCI_MASTER1_REQ_MASK_2BITS 10
55#define PCI_MASTER2_REQ_MASK_2BITS 12
56#define INTERNAL_ARB_ENABLE_BIT 0
57
58#define LTQ_CGU_IFCCR 0x0018
59#define LTQ_CGU_PCICR 0x0034
60
61#define ltq_pci_w32(x, y) ltq_w32((x), ltq_pci_membase + (y))
62#define ltq_pci_r32(x) ltq_r32(ltq_pci_membase + (x))
63
64#define ltq_pci_cfg_w32(x, y) ltq_w32((x), ltq_pci_mapped_cfg + (y))
65#define ltq_pci_cfg_r32(x) ltq_r32(ltq_pci_mapped_cfg + (x))
66
67__iomem void *ltq_pci_mapped_cfg;
68static __iomem void *ltq_pci_membase;
69
70static int reset_gpio;
71static struct clk *clk_pci, *clk_external;
72static struct resource pci_io_resource;
73static struct resource pci_mem_resource;
74static struct pci_ops pci_ops = {
75 .read = ltq_pci_read_config_dword,
76 .write = ltq_pci_write_config_dword
77};
78
79static struct pci_controller pci_controller = {
80 .pci_ops = &pci_ops,
81 .mem_resource = &pci_mem_resource,
82 .mem_offset = 0x00000000UL,
83 .io_resource = &pci_io_resource,
84 .io_offset = 0x00000000UL,
85};
86
87static inline u32 ltq_calc_bar11mask(void)
88{
89 u32 mem, bar11mask;
90
91 /* BAR11MASK value depends on available memory on system. */
92 mem = get_num_physpages() * PAGE_SIZE;
93 bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
94
95 return bar11mask;
96}
97
98static int ltq_pci_startup(struct platform_device *pdev)
99{
100 struct device_node *node = pdev->dev.of_node;
101 const __be32 *req_mask, *bus_clk;
102 u32 temp_buffer;
103
104 /* get our clocks */
105 clk_pci = clk_get(&pdev->dev, NULL);
106 if (IS_ERR(clk_pci)) {
107 dev_err(&pdev->dev, "failed to get pci clock\n");
108 return PTR_ERR(clk_pci);
109 }
110
111 clk_external = clk_get(&pdev->dev, "external");
112 if (IS_ERR(clk_external)) {
113 clk_put(clk_pci);
114 dev_err(&pdev->dev, "failed to get external pci clock\n");
115 return PTR_ERR(clk_external);
116 }
117
118 /* read the bus speed that we want */
119 bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
120 if (bus_clk)
121 clk_set_rate(clk_pci, *bus_clk);
122
123 /* and enable the clocks */
124 clk_enable(clk_pci);
125 if (of_find_property(node, "lantiq,external-clock", NULL))
126 clk_enable(clk_external);
127 else
128 clk_disable(clk_external);
129
130 /* setup reset gpio used by pci */
131 reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
132 if (gpio_is_valid(reset_gpio)) {
133 int ret = devm_gpio_request(&pdev->dev,
134 reset_gpio, "pci-reset");
135 if (ret) {
136 dev_err(&pdev->dev,
137 "failed to request gpio %d\n", reset_gpio);
138 return ret;
139 }
140 gpio_direction_output(reset_gpio, 1);
141 }
142
143 /* enable auto-switching between PCI and EBU */
144 ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
145
146 /* busy, i.e. configuration is not done, PCI access has to be retried */
147 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
148 wmb();
149 /* BUS Master/IO/MEM access */
150 ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
151
152 /* enable external 2 PCI masters */
153 temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
154 /* setup the request mask */
155 req_mask = of_get_property(node, "req-mask", NULL);
156 if (req_mask)
157 temp_buffer &= ~((*req_mask & 0xf) << 16);
158 else
159 temp_buffer &= ~0xf0000;
160 /* enable internal arbiter */
161 temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
162 /* enable internal PCI master reqest */
163 temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
164
165 /* enable EBU request */
166 temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
167
168 /* enable all external masters request */
169 temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
170 ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
171 wmb();
172
173 /* setup BAR memory regions */
174 ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
175 ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
176 ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
177 ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
178 ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
179 ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
180 ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
181 ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
182 ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
183 ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
184 ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
185 ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
186 /* both TX and RX endian swap are enabled */
187 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
188 wmb();
189 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
190 PCI_CR_BAR12MASK);
191 ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
192 PCI_CR_BAR13MASK);
193 /*use 8 dw burst length */
194 ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
195 ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
196 wmb();
197
198 /* setup irq line */
199 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
200 ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
201
202 /* toggle reset pin */
203 if (gpio_is_valid(reset_gpio)) {
204 __gpio_set_value(reset_gpio, 0);
205 wmb();
206 mdelay(1);
207 __gpio_set_value(reset_gpio, 1);
208 }
209 return 0;
210}
211
212static int ltq_pci_probe(struct platform_device *pdev)
213{
214 struct resource *res_cfg, *res_bridge;
215
216 pci_clear_flags(PCI_PROBE_ONLY);
217
218 res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
219 res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
220 if (!res_cfg || !res_bridge) {
221 dev_err(&pdev->dev, "missing memory reources\n");
222 return -EINVAL;
223 }
224
225 ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
226 if (IS_ERR(ltq_pci_membase))
227 return PTR_ERR(ltq_pci_membase);
228
229 ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
230 if (IS_ERR(ltq_pci_mapped_cfg))
231 return PTR_ERR(ltq_pci_mapped_cfg);
232
233 ltq_pci_startup(pdev);
234
235 pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
236 register_pci_controller(&pci_controller);
237 return 0;
238}
239
240static const struct of_device_id ltq_pci_match[] = {
241 { .compatible = "lantiq,pci-xway" },
242 {},
243};
244MODULE_DEVICE_TABLE(of, ltq_pci_match);
245
246static struct platform_driver ltq_pci_driver = {
247 .probe = ltq_pci_probe,
248 .driver = {
249 .name = "pci-xway",
250 .owner = THIS_MODULE,
251 .of_match_table = ltq_pci_match,
252 },
253};
254
255int __init pcibios_init(void)
256{
257 int ret = platform_driver_register(<q_pci_driver);
258 if (ret)
259 pr_info("pci-xway: Error registering platform driver!");
260 return ret;
261}
262
263arch_initcall(pcibios_init);