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1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/types.h>
36#include <linux/kernel.h>
37#include <linux/mm.h>
38#include <linux/delay.h>
39
40#include <asm/mipsregs.h>
41#include <asm/time.h>
42
43#include <asm/netlogic/common.h>
44#include <asm/netlogic/haldefs.h>
45#include <asm/netlogic/xlp-hal/iomap.h>
46#include <asm/netlogic/xlp-hal/xlp.h>
47#include <asm/netlogic/xlp-hal/bridge.h>
48#include <asm/netlogic/xlp-hal/pic.h>
49#include <asm/netlogic/xlp-hal/sys.h>
50
51/* Main initialization */
52void nlm_node_init(int node)
53{
54 struct nlm_soc_info *nodep;
55
56 nodep = nlm_get_node(node);
57 nodep->sysbase = nlm_get_sys_regbase(node);
58 nodep->picbase = nlm_get_pic_regbase(node);
59 nodep->ebase = read_c0_ebase() & (~((1 << 12) - 1));
60 if (cpu_is_xlp9xx())
61 nodep->socbus = xlp9xx_get_socbus(node);
62 else
63 nodep->socbus = 0;
64 spin_lock_init(&nodep->piclock);
65}
66
67int nlm_irq_to_irt(int irq)
68{
69 uint64_t pcibase;
70 int devoff, irt;
71
72 /* bypass for 9xx */
73 if (cpu_is_xlp9xx()) {
74 switch (irq) {
75 case PIC_9XX_XHCI_0_IRQ:
76 return 114;
77 case PIC_9XX_XHCI_1_IRQ:
78 return 115;
79 case PIC_UART_0_IRQ:
80 return 133;
81 case PIC_UART_1_IRQ:
82 return 134;
83 case PIC_PCIE_LINK_LEGACY_IRQ(0):
84 case PIC_PCIE_LINK_LEGACY_IRQ(1):
85 case PIC_PCIE_LINK_LEGACY_IRQ(2):
86 case PIC_PCIE_LINK_LEGACY_IRQ(3):
87 return 191 + irq - PIC_PCIE_LINK_LEGACY_IRQ_BASE;
88 }
89 return -1;
90 }
91
92 devoff = 0;
93 switch (irq) {
94 case PIC_UART_0_IRQ:
95 devoff = XLP_IO_UART0_OFFSET(0);
96 break;
97 case PIC_UART_1_IRQ:
98 devoff = XLP_IO_UART1_OFFSET(0);
99 break;
100 case PIC_MMC_IRQ:
101 devoff = XLP_IO_SD_OFFSET(0);
102 break;
103 case PIC_I2C_0_IRQ: /* I2C will be fixed up */
104 case PIC_I2C_1_IRQ:
105 case PIC_I2C_2_IRQ:
106 case PIC_I2C_3_IRQ:
107 if (cpu_is_xlpii())
108 devoff = XLP2XX_IO_I2C_OFFSET(0);
109 else
110 devoff = XLP_IO_I2C0_OFFSET(0);
111 break;
112 default:
113 if (cpu_is_xlpii()) {
114 switch (irq) {
115 /* XLP2XX has three XHCI USB controller */
116 case PIC_2XX_XHCI_0_IRQ:
117 devoff = XLP2XX_IO_USB_XHCI0_OFFSET(0);
118 break;
119 case PIC_2XX_XHCI_1_IRQ:
120 devoff = XLP2XX_IO_USB_XHCI1_OFFSET(0);
121 break;
122 case PIC_2XX_XHCI_2_IRQ:
123 devoff = XLP2XX_IO_USB_XHCI2_OFFSET(0);
124 break;
125 }
126 } else {
127 switch (irq) {
128 case PIC_EHCI_0_IRQ:
129 devoff = XLP_IO_USB_EHCI0_OFFSET(0);
130 break;
131 case PIC_EHCI_1_IRQ:
132 devoff = XLP_IO_USB_EHCI1_OFFSET(0);
133 break;
134 case PIC_OHCI_0_IRQ:
135 devoff = XLP_IO_USB_OHCI0_OFFSET(0);
136 break;
137 case PIC_OHCI_1_IRQ:
138 devoff = XLP_IO_USB_OHCI1_OFFSET(0);
139 break;
140 case PIC_OHCI_2_IRQ:
141 devoff = XLP_IO_USB_OHCI2_OFFSET(0);
142 break;
143 case PIC_OHCI_3_IRQ:
144 devoff = XLP_IO_USB_OHCI3_OFFSET(0);
145 break;
146 }
147 }
148 }
149
150 if (devoff != 0) {
151 pcibase = nlm_pcicfg_base(devoff);
152 irt = nlm_read_reg(pcibase, XLP_PCI_IRTINFO_REG) & 0xffff;
153 /* HW weirdness, I2C IRT entry has to be fixed up */
154 switch (irq) {
155 case PIC_I2C_1_IRQ:
156 irt = irt + 1; break;
157 case PIC_I2C_2_IRQ:
158 irt = irt + 2; break;
159 case PIC_I2C_3_IRQ:
160 irt = irt + 3; break;
161 }
162 } else if (irq >= PIC_PCIE_LINK_LEGACY_IRQ(0) &&
163 irq <= PIC_PCIE_LINK_LEGACY_IRQ(3)) {
164 /* HW bug, PCI IRT entries are bad on early silicon, fix */
165 irt = PIC_IRT_PCIE_LINK_INDEX(irq -
166 PIC_PCIE_LINK_LEGACY_IRQ_BASE);
167 } else if (irq >= PIC_PCIE_LINK_MSI_IRQ(0) &&
168 irq <= PIC_PCIE_LINK_MSI_IRQ(3)) {
169 irt = -2;
170 } else if (irq >= PIC_PCIE_MSIX_IRQ(0) &&
171 irq <= PIC_PCIE_MSIX_IRQ(3)) {
172 irt = -2;
173 } else {
174 irt = -1;
175 }
176 return irt;
177}
178
179unsigned int nlm_get_core_frequency(int node, int core)
180{
181 unsigned int pll_divf, pll_divr, dfs_div, ext_div;
182 unsigned int rstval, dfsval, denom;
183 uint64_t num, sysbase;
184
185 sysbase = nlm_get_node(node)->sysbase;
186 if (cpu_is_xlp9xx())
187 rstval = nlm_read_sys_reg(sysbase, SYS_9XX_POWER_ON_RESET_CFG);
188 else
189 rstval = nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG);
190 if (cpu_is_xlpii()) {
191 num = 1000000ULL * (400 * 3 + 100 * (rstval >> 26));
192 denom = 3;
193 } else {
194 dfsval = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIV_VALUE);
195 pll_divf = ((rstval >> 10) & 0x7f) + 1;
196 pll_divr = ((rstval >> 8) & 0x3) + 1;
197 ext_div = ((rstval >> 30) & 0x3) + 1;
198 dfs_div = ((dfsval >> (core * 4)) & 0xf) + 1;
199
200 num = 800000000ULL * pll_divf;
201 denom = 3 * pll_divr * ext_div * dfs_div;
202 }
203 do_div(num, denom);
204 return (unsigned int)num;
205}
206
207/* Calculate Frequency to the PIC from PLL.
208 * freq_out = ( ref_freq/2 * (6 + ctrl2[7:0]) + ctrl2[20:8]/2^13 ) /
209 * ((2^ctrl0[7:5]) * Table(ctrl0[26:24]))
210 */
211static unsigned int nlm_2xx_get_pic_frequency(int node)
212{
213 u32 ctrl_val0, ctrl_val2, vco_post_div, pll_post_div;
214 u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div;
215 u64 ref_clk, sysbase, pll_out_freq_num, ref_clk_select;
216
217 sysbase = nlm_get_node(node)->sysbase;
218
219 /* Find ref_clk_base */
220 ref_clk_select =
221 (nlm_read_sys_reg(sysbase, SYS_POWER_ON_RESET_CFG) >> 18) & 0x3;
222 switch (ref_clk_select) {
223 case 0:
224 ref_clk = 200000000ULL;
225 ref_div = 3;
226 break;
227 case 1:
228 ref_clk = 100000000ULL;
229 ref_div = 1;
230 break;
231 case 2:
232 ref_clk = 125000000ULL;
233 ref_div = 1;
234 break;
235 case 3:
236 ref_clk = 400000000ULL;
237 ref_div = 3;
238 break;
239 }
240
241 /* Find the clock source PLL device for PIC */
242 reg_select = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_SEL) >> 22) & 0x3;
243 switch (reg_select) {
244 case 0:
245 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0);
246 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2);
247 break;
248 case 1:
249 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(0));
250 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(0));
251 break;
252 case 2:
253 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(1));
254 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(1));
255 break;
256 case 3:
257 ctrl_val0 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL0_DEVX(2));
258 ctrl_val2 = nlm_read_sys_reg(sysbase, SYS_PLL_CTRL2_DEVX(2));
259 break;
260 }
261
262 vco_post_div = (ctrl_val0 >> 5) & 0x7;
263 pll_post_div = (ctrl_val0 >> 24) & 0x7;
264 mdiv = ctrl_val2 & 0xff;
265 fdiv = (ctrl_val2 >> 8) & 0xfff;
266
267 /* Find PLL post divider value */
268 switch (pll_post_div) {
269 case 1:
270 pll_post_div = 2;
271 break;
272 case 3:
273 pll_post_div = 4;
274 break;
275 case 7:
276 pll_post_div = 8;
277 break;
278 case 6:
279 pll_post_div = 16;
280 break;
281 case 0:
282 default:
283 pll_post_div = 1;
284 break;
285 }
286
287 fdiv = fdiv/(1 << 13);
288 pll_out_freq_num = ((ref_clk >> 1) * (6 + mdiv)) + fdiv;
289 pll_out_freq_den = (1 << vco_post_div) * pll_post_div * 3;
290
291 if (pll_out_freq_den > 0)
292 do_div(pll_out_freq_num, pll_out_freq_den);
293
294 /* PIC post divider, which happens after PLL */
295 pic_div = (nlm_read_sys_reg(sysbase, SYS_CLK_DEV_DIV) >> 22) & 0x3;
296 do_div(pll_out_freq_num, 1 << pic_div);
297
298 return pll_out_freq_num;
299}
300
301unsigned int nlm_get_pic_frequency(int node)
302{
303 /* TODO Has to calculate freq as like 2xx */
304 if (cpu_is_xlp9xx())
305 return 250000000;
306
307 if (cpu_is_xlpii())
308 return nlm_2xx_get_pic_frequency(node);
309 else
310 return 133333333;
311}
312
313unsigned int nlm_get_cpu_frequency(void)
314{
315 return nlm_get_core_frequency(0, 0);
316}
317
318/*
319 * Fills upto 8 pairs of entries containing the DRAM map of a node
320 * if n < 0, get dram map for all nodes
321 */
322int xlp_get_dram_map(int n, uint64_t *dram_map)
323{
324 uint64_t bridgebase, base, lim;
325 uint32_t val;
326 unsigned int barreg, limreg, xlatreg;
327 int i, node, rv;
328
329 /* Look only at mapping on Node 0, we don't handle crazy configs */
330 bridgebase = nlm_get_bridge_regbase(0);
331 rv = 0;
332 for (i = 0; i < 8; i++) {
333 if (cpu_is_xlp9xx()) {
334 barreg = BRIDGE_9XX_DRAM_BAR(i);
335 limreg = BRIDGE_9XX_DRAM_LIMIT(i);
336 xlatreg = BRIDGE_9XX_DRAM_NODE_TRANSLN(i);
337 } else {
338 barreg = BRIDGE_DRAM_BAR(i);
339 limreg = BRIDGE_DRAM_LIMIT(i);
340 xlatreg = BRIDGE_DRAM_NODE_TRANSLN(i);
341 }
342 if (n >= 0) {
343 /* node specified, get node mapping of BAR */
344 val = nlm_read_bridge_reg(bridgebase, xlatreg);
345 node = (val >> 1) & 0x3;
346 if (n != node)
347 continue;
348 }
349 val = nlm_read_bridge_reg(bridgebase, barreg);
350 val = (val >> 12) & 0xfffff;
351 base = (uint64_t) val << 20;
352 val = nlm_read_bridge_reg(bridgebase, limreg);
353 val = (val >> 12) & 0xfffff;
354 if (val == 0) /* BAR not used */
355 continue;
356 lim = ((uint64_t)val + 1) << 20;
357 dram_map[rv] = base;
358 dram_map[rv + 1] = lim;
359 rv += 2;
360 }
361 return rv;
362}