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1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/smp.h>
39#include <linux/irq.h>
40
41#include <asm/mmu_context.h>
42
43#include <asm/netlogic/interrupt.h>
44#include <asm/netlogic/mips-extns.h>
45#include <asm/netlogic/haldefs.h>
46#include <asm/netlogic/common.h>
47
48#if defined(CONFIG_CPU_XLP)
49#include <asm/netlogic/xlp-hal/iomap.h>
50#include <asm/netlogic/xlp-hal/xlp.h>
51#include <asm/netlogic/xlp-hal/pic.h>
52#elif defined(CONFIG_CPU_XLR)
53#include <asm/netlogic/xlr/iomap.h>
54#include <asm/netlogic/xlr/pic.h>
55#include <asm/netlogic/xlr/xlr.h>
56#else
57#error "Unknown CPU"
58#endif
59
60void nlm_send_ipi_single(int logical_cpu, unsigned int action)
61{
62 int cpu, node;
63 uint64_t picbase;
64
65 cpu = cpu_logical_map(logical_cpu);
66 node = nlm_cpuid_to_node(cpu);
67 picbase = nlm_get_node(node)->picbase;
68
69 if (action & SMP_CALL_FUNCTION)
70 nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_FUNCTION, 0);
71 if (action & SMP_RESCHEDULE_YOURSELF)
72 nlm_pic_send_ipi(picbase, cpu, IRQ_IPI_SMP_RESCHEDULE, 0);
73}
74
75void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
76{
77 int cpu;
78
79 for_each_cpu(cpu, mask) {
80 nlm_send_ipi_single(cpu, action);
81 }
82}
83
84/* IRQ_IPI_SMP_FUNCTION Handler */
85void nlm_smp_function_ipi_handler(unsigned int irq, struct irq_desc *desc)
86{
87 clear_c0_eimr(irq);
88 ack_c0_eirr(irq);
89 smp_call_function_interrupt();
90 set_c0_eimr(irq);
91}
92
93/* IRQ_IPI_SMP_RESCHEDULE handler */
94void nlm_smp_resched_ipi_handler(unsigned int irq, struct irq_desc *desc)
95{
96 clear_c0_eimr(irq);
97 ack_c0_eirr(irq);
98 scheduler_ipi();
99 set_c0_eimr(irq);
100}
101
102/*
103 * Called before going into mips code, early cpu init
104 */
105void nlm_early_init_secondary(int cpu)
106{
107 change_c0_config(CONF_CM_CMASK, 0x3);
108#ifdef CONFIG_CPU_XLP
109 xlp_mmu_init();
110#endif
111 write_c0_ebase(nlm_current_node()->ebase);
112}
113
114/*
115 * Code to run on secondary just after probing the CPU
116 */
117static void nlm_init_secondary(void)
118{
119 int hwtid;
120
121 hwtid = hard_smp_processor_id();
122 current_cpu_data.core = hwtid / NLM_THREADS_PER_CORE;
123 nlm_percpu_init(hwtid);
124 nlm_smp_irq_init(hwtid);
125}
126
127void nlm_prepare_cpus(unsigned int max_cpus)
128{
129 /* declare we are SMT capable */
130 smp_num_siblings = nlm_threads_per_core;
131}
132
133void nlm_smp_finish(void)
134{
135 local_irq_enable();
136}
137
138void nlm_cpus_done(void)
139{
140}
141
142/*
143 * Boot all other cpus in the system, initialize them, and bring them into
144 * the boot function
145 */
146unsigned long nlm_next_gp;
147unsigned long nlm_next_sp;
148static cpumask_t phys_cpu_present_mask;
149
150void nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
151{
152 int cpu, node;
153
154 cpu = cpu_logical_map(logical_cpu);
155 node = nlm_cpuid_to_node(logical_cpu);
156 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
157 nlm_next_gp = (unsigned long)task_thread_info(idle);
158
159 /* barrier for sp/gp store above */
160 __sync();
161 nlm_pic_send_ipi(nlm_get_node(node)->picbase, cpu, 1, 1); /* NMI */
162}
163
164void __init nlm_smp_setup(void)
165{
166 unsigned int boot_cpu;
167 int num_cpus, i, ncore, node;
168 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
169 char buf[64];
170
171 boot_cpu = hard_smp_processor_id();
172 cpumask_clear(&phys_cpu_present_mask);
173
174 cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
175 __cpu_number_map[boot_cpu] = 0;
176 __cpu_logical_map[0] = boot_cpu;
177 set_cpu_possible(0, true);
178
179 num_cpus = 1;
180 for (i = 0; i < NR_CPUS; i++) {
181 /*
182 * cpu_ready array is not set for the boot_cpu,
183 * it is only set for ASPs (see smpboot.S)
184 */
185 if (cpu_ready[i]) {
186 cpumask_set_cpu(i, &phys_cpu_present_mask);
187 __cpu_number_map[i] = num_cpus;
188 __cpu_logical_map[num_cpus] = i;
189 set_cpu_possible(num_cpus, true);
190 node = nlm_cpuid_to_node(i);
191 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
192 ++num_cpus;
193 }
194 }
195
196 cpumask_scnprintf(buf, ARRAY_SIZE(buf), &phys_cpu_present_mask);
197 pr_info("Physical CPU mask: %s\n", buf);
198 cpumask_scnprintf(buf, ARRAY_SIZE(buf), cpu_possible_mask);
199 pr_info("Possible CPU mask: %s\n", buf);
200
201 /* check with the cores we have worken up */
202 for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
203 ncore += hweight32(nlm_get_node(i)->coremask);
204
205 pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
206 nlm_threads_per_core, num_cpus);
207
208 /* switch NMI handler to boot CPUs */
209 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
210}
211
212static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
213{
214 uint32_t core0_thr_mask, core_thr_mask;
215 int threadmode, i, j;
216
217 core0_thr_mask = 0;
218 for (i = 0; i < NLM_THREADS_PER_CORE; i++)
219 if (cpumask_test_cpu(i, wakeup_mask))
220 core0_thr_mask |= (1 << i);
221 switch (core0_thr_mask) {
222 case 1:
223 nlm_threads_per_core = 1;
224 threadmode = 0;
225 break;
226 case 3:
227 nlm_threads_per_core = 2;
228 threadmode = 2;
229 break;
230 case 0xf:
231 nlm_threads_per_core = 4;
232 threadmode = 3;
233 break;
234 default:
235 goto unsupp;
236 }
237
238 /* Verify other cores CPU masks */
239 for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
240 core_thr_mask = 0;
241 for (j = 0; j < NLM_THREADS_PER_CORE; j++)
242 if (cpumask_test_cpu(i + j, wakeup_mask))
243 core_thr_mask |= (1 << j);
244 if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
245 goto unsupp;
246 }
247 return threadmode;
248
249unsupp:
250 panic("Unsupported CPU mask %lx",
251 (unsigned long)cpumask_bits(wakeup_mask)[0]);
252 return 0;
253}
254
255int nlm_wakeup_secondary_cpus(void)
256{
257 u32 *reset_data;
258 int threadmode;
259
260 /* verify the mask and setup core config variables */
261 threadmode = nlm_parse_cpumask(&nlm_cpumask);
262
263 /* Setup CPU init parameters */
264 reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
265 *reset_data = threadmode;
266
267#ifdef CONFIG_CPU_XLP
268 xlp_wakeup_secondary_cpus();
269#else
270 xlr_wakeup_secondary_cpus();
271#endif
272 return 0;
273}
274
275struct plat_smp_ops nlm_smp_ops = {
276 .send_ipi_single = nlm_send_ipi_single,
277 .send_ipi_mask = nlm_send_ipi_mask,
278 .init_secondary = nlm_init_secondary,
279 .smp_finish = nlm_smp_finish,
280 .cpus_done = nlm_cpus_done,
281 .boot_secondary = nlm_boot_secondary,
282 .smp_setup = nlm_smp_setup,
283 .prepare_cpus = nlm_prepare_cpus,
284};