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1/*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * A small micro-assembler. It is intentionally kept simple, does only
7 * support a subset of instructions, and does not try to hide pipeline
8 * effects like branch delay slots.
9 *
10 * Copyright (C) 2004, 2005, 2006, 2008 Thiemo Seufer
11 * Copyright (C) 2005, 2007 Maciej W. Rozycki
12 * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
13 * Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
14 */
15
16#include <linux/kernel.h>
17#include <linux/types.h>
18
19#include <asm/inst.h>
20#include <asm/elf.h>
21#include <asm/bugs.h>
22#define UASM_ISA _UASM_ISA_CLASSIC
23#include <asm/uasm.h>
24
25#define RS_MASK 0x1f
26#define RS_SH 21
27#define RT_MASK 0x1f
28#define RT_SH 16
29#define SCIMM_MASK 0xfffff
30#define SCIMM_SH 6
31
32/* This macro sets the non-variable bits of an instruction. */
33#define M(a, b, c, d, e, f) \
34 ((a) << OP_SH \
35 | (b) << RS_SH \
36 | (c) << RT_SH \
37 | (d) << RD_SH \
38 | (e) << RE_SH \
39 | (f) << FUNC_SH)
40
41/* Define these when we are not the ISA the kernel is being compiled with. */
42#ifdef CONFIG_CPU_MICROMIPS
43#define CL_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
44#define CL_uasm_i_beqz(buf, rs, off) ISAOPC(_beq)(buf, rs, 0, off)
45#define CL_uasm_i_beqzl(buf, rs, off) ISAOPC(_beql)(buf, rs, 0, off)
46#define CL_uasm_i_bnez(buf, rs, off) ISAOPC(_bne)(buf, rs, 0, off)
47#endif
48
49#include "uasm.c"
50
51static struct insn insn_table[] = {
52 { insn_addiu, M(addiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
53 { insn_addu, M(spec_op, 0, 0, 0, 0, addu_op), RS | RT | RD },
54 { insn_andi, M(andi_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
55 { insn_and, M(spec_op, 0, 0, 0, 0, and_op), RS | RT | RD },
56 { insn_bbit0, M(lwc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
57 { insn_bbit1, M(swc2_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
58 { insn_beql, M(beql_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
59 { insn_beq, M(beq_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
60 { insn_bgezl, M(bcond_op, 0, bgezl_op, 0, 0, 0), RS | BIMM },
61 { insn_bgez, M(bcond_op, 0, bgez_op, 0, 0, 0), RS | BIMM },
62 { insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
63 { insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
64 { insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
65 { insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
66 { insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
67 { insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
68 { insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
69 { insn_dins, M(spec3_op, 0, 0, 0, 0, dins_op), RS | RT | RD | RE },
70 { insn_dmfc0, M(cop0_op, dmfc_op, 0, 0, 0, 0), RT | RD | SET},
71 { insn_dmtc0, M(cop0_op, dmtc_op, 0, 0, 0, 0), RT | RD | SET},
72 { insn_drotr32, M(spec_op, 1, 0, 0, 0, dsrl32_op), RT | RD | RE },
73 { insn_drotr, M(spec_op, 1, 0, 0, 0, dsrl_op), RT | RD | RE },
74 { insn_dsll32, M(spec_op, 0, 0, 0, 0, dsll32_op), RT | RD | RE },
75 { insn_dsll, M(spec_op, 0, 0, 0, 0, dsll_op), RT | RD | RE },
76 { insn_dsra, M(spec_op, 0, 0, 0, 0, dsra_op), RT | RD | RE },
77 { insn_dsrl32, M(spec_op, 0, 0, 0, 0, dsrl32_op), RT | RD | RE },
78 { insn_dsrl, M(spec_op, 0, 0, 0, 0, dsrl_op), RT | RD | RE },
79 { insn_dsubu, M(spec_op, 0, 0, 0, 0, dsubu_op), RS | RT | RD },
80 { insn_eret, M(cop0_op, cop_op, 0, 0, 0, eret_op), 0 },
81 { insn_ext, M(spec3_op, 0, 0, 0, 0, ext_op), RS | RT | RD | RE },
82 { insn_ins, M(spec3_op, 0, 0, 0, 0, ins_op), RS | RT | RD | RE },
83 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
84 { insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
85 { insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
86 { insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
87 { insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
88 { insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
89 { insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
90 { insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
91 { insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
92 { insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
93 { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
94 { insn_mfc0, M(cop0_op, mfc_op, 0, 0, 0, 0), RT | RD | SET},
95 { insn_mtc0, M(cop0_op, mtc_op, 0, 0, 0, 0), RT | RD | SET},
96 { insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
97 { insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
98 { insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
99 { insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
100 { insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
101 { insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
102 { insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
103 { insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
104 { insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
105 { insn_sra, M(spec_op, 0, 0, 0, 0, sra_op), RT | RD | RE },
106 { insn_srl, M(spec_op, 0, 0, 0, 0, srl_op), RT | RD | RE },
107 { insn_subu, M(spec_op, 0, 0, 0, 0, subu_op), RS | RT | RD },
108 { insn_sw, M(sw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
109 { insn_syscall, M(spec_op, 0, 0, 0, 0, syscall_op), SCIMM},
110 { insn_tlbp, M(cop0_op, cop_op, 0, 0, 0, tlbp_op), 0 },
111 { insn_tlbr, M(cop0_op, cop_op, 0, 0, 0, tlbr_op), 0 },
112 { insn_tlbwi, M(cop0_op, cop_op, 0, 0, 0, tlbwi_op), 0 },
113 { insn_tlbwr, M(cop0_op, cop_op, 0, 0, 0, tlbwr_op), 0 },
114 { insn_xori, M(xori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
115 { insn_xor, M(spec_op, 0, 0, 0, 0, xor_op), RS | RT | RD },
116 { insn_invalid, 0, 0 }
117};
118
119#undef M
120
121static inline u32 build_bimm(s32 arg)
122{
123 WARN(arg > 0x1ffff || arg < -0x20000,
124 KERN_WARNING "Micro-assembler field overflow\n");
125
126 WARN(arg & 0x3, KERN_WARNING "Invalid micro-assembler branch target\n");
127
128 return ((arg < 0) ? (1 << 15) : 0) | ((arg >> 2) & 0x7fff);
129}
130
131static inline u32 build_jimm(u32 arg)
132{
133 WARN(arg & ~(JIMM_MASK << 2),
134 KERN_WARNING "Micro-assembler field overflow\n");
135
136 return (arg >> 2) & JIMM_MASK;
137}
138
139/*
140 * The order of opcode arguments is implicitly left to right,
141 * starting with RS and ending with FUNC or IMM.
142 */
143static void build_insn(u32 **buf, enum opcode opc, ...)
144{
145 struct insn *ip = NULL;
146 unsigned int i;
147 va_list ap;
148 u32 op;
149
150 for (i = 0; insn_table[i].opcode != insn_invalid; i++)
151 if (insn_table[i].opcode == opc) {
152 ip = &insn_table[i];
153 break;
154 }
155
156 if (!ip || (opc == insn_daddiu && r4k_daddiu_bug()))
157 panic("Unsupported Micro-assembler instruction %d", opc);
158
159 op = ip->match;
160 va_start(ap, opc);
161 if (ip->fields & RS)
162 op |= build_rs(va_arg(ap, u32));
163 if (ip->fields & RT)
164 op |= build_rt(va_arg(ap, u32));
165 if (ip->fields & RD)
166 op |= build_rd(va_arg(ap, u32));
167 if (ip->fields & RE)
168 op |= build_re(va_arg(ap, u32));
169 if (ip->fields & SIMM)
170 op |= build_simm(va_arg(ap, s32));
171 if (ip->fields & UIMM)
172 op |= build_uimm(va_arg(ap, u32));
173 if (ip->fields & BIMM)
174 op |= build_bimm(va_arg(ap, s32));
175 if (ip->fields & JIMM)
176 op |= build_jimm(va_arg(ap, u32));
177 if (ip->fields & FUNC)
178 op |= build_func(va_arg(ap, u32));
179 if (ip->fields & SET)
180 op |= build_set(va_arg(ap, u32));
181 if (ip->fields & SCIMM)
182 op |= build_scimm(va_arg(ap, u32));
183 va_end(ap);
184
185 **buf = op;
186 (*buf)++;
187}
188
189static inline void
190__resolve_relocs(struct uasm_reloc *rel, struct uasm_label *lab)
191{
192 long laddr = (long)lab->addr;
193 long raddr = (long)rel->addr;
194
195 switch (rel->type) {
196 case R_MIPS_PC16:
197 *rel->addr |= build_bimm(laddr - (raddr + 4));
198 break;
199
200 default:
201 panic("Unsupported Micro-assembler relocation %d",
202 rel->type);
203 }
204}