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1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * You should have received a copy of the GNU General Public License
12 * along with this program; if not, write to the Free Software
13 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
14 *
15 * Copyright (C) 2012 ARM Limited
16 *
17 * Author: Will Deacon <will.deacon@arm.com>
18 */
19#define pr_fmt(fmt) "CPU PMU: " fmt
20
21#include <linux/bitmap.h>
22#include <linux/export.h>
23#include <linux/kernel.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/slab.h>
27#include <linux/spinlock.h>
28#include <linux/irq.h>
29#include <linux/irqdesc.h>
30
31#include <asm/cputype.h>
32#include <asm/irq_regs.h>
33#include <asm/pmu.h>
34
35/* Set at runtime when we know what CPU type we are. */
36static struct arm_pmu *cpu_pmu;
37
38static DEFINE_PER_CPU(struct arm_pmu *, percpu_pmu);
39static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
40static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
41static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
42
43/*
44 * Despite the names, these two functions are CPU-specific and are used
45 * by the OProfile/perf code.
46 */
47const char *perf_pmu_name(void)
48{
49 if (!cpu_pmu)
50 return NULL;
51
52 return cpu_pmu->name;
53}
54EXPORT_SYMBOL_GPL(perf_pmu_name);
55
56int perf_num_counters(void)
57{
58 int max_events = 0;
59
60 if (cpu_pmu != NULL)
61 max_events = cpu_pmu->num_events;
62
63 return max_events;
64}
65EXPORT_SYMBOL_GPL(perf_num_counters);
66
67/* Include the PMU-specific implementations. */
68#include "perf_event_xscale.c"
69#include "perf_event_v6.c"
70#include "perf_event_v7.c"
71
72static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
73{
74 return this_cpu_ptr(&cpu_hw_events);
75}
76
77static void cpu_pmu_enable_percpu_irq(void *data)
78{
79 struct arm_pmu *cpu_pmu = data;
80 struct platform_device *pmu_device = cpu_pmu->plat_device;
81 int irq = platform_get_irq(pmu_device, 0);
82
83 enable_percpu_irq(irq, IRQ_TYPE_NONE);
84 cpumask_set_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
85}
86
87static void cpu_pmu_disable_percpu_irq(void *data)
88{
89 struct arm_pmu *cpu_pmu = data;
90 struct platform_device *pmu_device = cpu_pmu->plat_device;
91 int irq = platform_get_irq(pmu_device, 0);
92
93 cpumask_clear_cpu(smp_processor_id(), &cpu_pmu->active_irqs);
94 disable_percpu_irq(irq);
95}
96
97static void cpu_pmu_free_irq(struct arm_pmu *cpu_pmu)
98{
99 int i, irq, irqs;
100 struct platform_device *pmu_device = cpu_pmu->plat_device;
101
102 irqs = min(pmu_device->num_resources, num_possible_cpus());
103
104 irq = platform_get_irq(pmu_device, 0);
105 if (irq >= 0 && irq_is_percpu(irq)) {
106 on_each_cpu(cpu_pmu_disable_percpu_irq, cpu_pmu, 1);
107 free_percpu_irq(irq, &percpu_pmu);
108 } else {
109 for (i = 0; i < irqs; ++i) {
110 if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
111 continue;
112 irq = platform_get_irq(pmu_device, i);
113 if (irq >= 0)
114 free_irq(irq, cpu_pmu);
115 }
116 }
117}
118
119static int cpu_pmu_request_irq(struct arm_pmu *cpu_pmu, irq_handler_t handler)
120{
121 int i, err, irq, irqs;
122 struct platform_device *pmu_device = cpu_pmu->plat_device;
123
124 if (!pmu_device)
125 return -ENODEV;
126
127 irqs = min(pmu_device->num_resources, num_possible_cpus());
128 if (irqs < 1) {
129 pr_err("no irqs for PMUs defined\n");
130 return -ENODEV;
131 }
132
133 irq = platform_get_irq(pmu_device, 0);
134 if (irq >= 0 && irq_is_percpu(irq)) {
135 err = request_percpu_irq(irq, handler, "arm-pmu", &percpu_pmu);
136 if (err) {
137 pr_err("unable to request IRQ%d for ARM PMU counters\n",
138 irq);
139 return err;
140 }
141 on_each_cpu(cpu_pmu_enable_percpu_irq, cpu_pmu, 1);
142 } else {
143 for (i = 0; i < irqs; ++i) {
144 err = 0;
145 irq = platform_get_irq(pmu_device, i);
146 if (irq < 0)
147 continue;
148
149 /*
150 * If we have a single PMU interrupt that we can't shift,
151 * assume that we're running on a uniprocessor machine and
152 * continue. Otherwise, continue without this interrupt.
153 */
154 if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
155 pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
156 irq, i);
157 continue;
158 }
159
160 err = request_irq(irq, handler,
161 IRQF_NOBALANCING | IRQF_NO_THREAD, "arm-pmu",
162 cpu_pmu);
163 if (err) {
164 pr_err("unable to request IRQ%d for ARM PMU counters\n",
165 irq);
166 return err;
167 }
168
169 cpumask_set_cpu(i, &cpu_pmu->active_irqs);
170 }
171 }
172
173 return 0;
174}
175
176static void cpu_pmu_init(struct arm_pmu *cpu_pmu)
177{
178 int cpu;
179 for_each_possible_cpu(cpu) {
180 struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
181 events->events = per_cpu(hw_events, cpu);
182 events->used_mask = per_cpu(used_mask, cpu);
183 raw_spin_lock_init(&events->pmu_lock);
184 per_cpu(percpu_pmu, cpu) = cpu_pmu;
185 }
186
187 cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
188 cpu_pmu->request_irq = cpu_pmu_request_irq;
189 cpu_pmu->free_irq = cpu_pmu_free_irq;
190
191 /* Ensure the PMU has sane values out of reset. */
192 if (cpu_pmu->reset)
193 on_each_cpu(cpu_pmu->reset, cpu_pmu, 1);
194}
195
196/*
197 * PMU hardware loses all context when a CPU goes offline.
198 * When a CPU is hotplugged back in, since some hardware registers are
199 * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
200 * junk values out of them.
201 */
202static int cpu_pmu_notify(struct notifier_block *b, unsigned long action,
203 void *hcpu)
204{
205 if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
206 return NOTIFY_DONE;
207
208 if (cpu_pmu && cpu_pmu->reset)
209 cpu_pmu->reset(cpu_pmu);
210 else
211 return NOTIFY_DONE;
212
213 return NOTIFY_OK;
214}
215
216static struct notifier_block cpu_pmu_hotplug_notifier = {
217 .notifier_call = cpu_pmu_notify,
218};
219
220/*
221 * PMU platform driver and devicetree bindings.
222 */
223static struct of_device_id cpu_pmu_of_device_ids[] = {
224 {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
225 {.compatible = "arm,cortex-a12-pmu", .data = armv7_a12_pmu_init},
226 {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
227 {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
228 {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
229 {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
230 {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
231 {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
232 {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
233 {.compatible = "qcom,krait-pmu", .data = krait_pmu_init},
234 {},
235};
236
237static struct platform_device_id cpu_pmu_plat_device_ids[] = {
238 {.name = "arm-pmu"},
239 {},
240};
241
242/*
243 * CPU PMU identification and probing.
244 */
245static int probe_current_pmu(struct arm_pmu *pmu)
246{
247 int cpu = get_cpu();
248 unsigned long implementor = read_cpuid_implementor();
249 unsigned long part_number = read_cpuid_part_number();
250 int ret = -ENODEV;
251
252 pr_info("probing PMU on CPU %d\n", cpu);
253
254 /* ARM Ltd CPUs. */
255 if (implementor == ARM_CPU_IMP_ARM) {
256 switch (part_number) {
257 case ARM_CPU_PART_ARM1136:
258 case ARM_CPU_PART_ARM1156:
259 case ARM_CPU_PART_ARM1176:
260 ret = armv6pmu_init(pmu);
261 break;
262 case ARM_CPU_PART_ARM11MPCORE:
263 ret = armv6mpcore_pmu_init(pmu);
264 break;
265 case ARM_CPU_PART_CORTEX_A8:
266 ret = armv7_a8_pmu_init(pmu);
267 break;
268 case ARM_CPU_PART_CORTEX_A9:
269 ret = armv7_a9_pmu_init(pmu);
270 break;
271 }
272 /* Intel CPUs [xscale]. */
273 } else if (implementor == ARM_CPU_IMP_INTEL) {
274 switch (xscale_cpu_arch_version()) {
275 case ARM_CPU_XSCALE_ARCH_V1:
276 ret = xscale1pmu_init(pmu);
277 break;
278 case ARM_CPU_XSCALE_ARCH_V2:
279 ret = xscale2pmu_init(pmu);
280 break;
281 }
282 }
283
284 put_cpu();
285 return ret;
286}
287
288static int cpu_pmu_device_probe(struct platform_device *pdev)
289{
290 const struct of_device_id *of_id;
291 const int (*init_fn)(struct arm_pmu *);
292 struct device_node *node = pdev->dev.of_node;
293 struct arm_pmu *pmu;
294 int ret = -ENODEV;
295
296 if (cpu_pmu) {
297 pr_info("attempt to register multiple PMU devices!");
298 return -ENOSPC;
299 }
300
301 pmu = kzalloc(sizeof(struct arm_pmu), GFP_KERNEL);
302 if (!pmu) {
303 pr_info("failed to allocate PMU device!");
304 return -ENOMEM;
305 }
306
307 cpu_pmu = pmu;
308 cpu_pmu->plat_device = pdev;
309
310 if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
311 init_fn = of_id->data;
312 ret = init_fn(pmu);
313 } else {
314 ret = probe_current_pmu(pmu);
315 }
316
317 if (ret) {
318 pr_info("failed to probe PMU!");
319 goto out_free;
320 }
321
322 cpu_pmu_init(cpu_pmu);
323 ret = armpmu_register(cpu_pmu, PERF_TYPE_RAW);
324
325 if (!ret)
326 return 0;
327
328out_free:
329 pr_info("failed to register PMU devices!");
330 kfree(pmu);
331 return ret;
332}
333
334static struct platform_driver cpu_pmu_driver = {
335 .driver = {
336 .name = "arm-pmu",
337 .pm = &armpmu_dev_pm_ops,
338 .of_match_table = cpu_pmu_of_device_ids,
339 },
340 .probe = cpu_pmu_device_probe,
341 .id_table = cpu_pmu_plat_device_ids,
342};
343
344static int __init register_pmu_driver(void)
345{
346 int err;
347
348 err = register_cpu_notifier(&cpu_pmu_hotplug_notifier);
349 if (err)
350 return err;
351
352 err = platform_driver_register(&cpu_pmu_driver);
353 if (err)
354 unregister_cpu_notifier(&cpu_pmu_hotplug_notifier);
355
356 return err;
357}
358device_initcall(register_pmu_driver);