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1/*
2 * omap_wdt.c
3 *
4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#include <linux/module.h>
30#include <linux/types.h>
31#include <linux/kernel.h>
32#include <linux/fs.h>
33#include <linux/mm.h>
34#include <linux/miscdevice.h>
35#include <linux/watchdog.h>
36#include <linux/reboot.h>
37#include <linux/init.h>
38#include <linux/err.h>
39#include <linux/platform_device.h>
40#include <linux/moduleparam.h>
41#include <linux/bitops.h>
42#include <linux/io.h>
43#include <linux/uaccess.h>
44#include <linux/slab.h>
45#include <linux/pm_runtime.h>
46#include <mach/hardware.h>
47#include <plat/prcm.h>
48
49#include "omap_wdt.h"
50
51static struct platform_device *omap_wdt_dev;
52
53static unsigned timer_margin;
54module_param(timer_margin, uint, 0);
55MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
56
57static unsigned int wdt_trgr_pattern = 0x1234;
58static spinlock_t wdt_lock;
59
60struct omap_wdt_dev {
61 void __iomem *base; /* physical */
62 struct device *dev;
63 int omap_wdt_users;
64 struct resource *mem;
65 struct miscdevice omap_wdt_miscdev;
66};
67
68static void omap_wdt_ping(struct omap_wdt_dev *wdev)
69{
70 void __iomem *base = wdev->base;
71
72 /* wait for posted write to complete */
73 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
74 cpu_relax();
75
76 wdt_trgr_pattern = ~wdt_trgr_pattern;
77 __raw_writel(wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
78
79 /* wait for posted write to complete */
80 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x08)
81 cpu_relax();
82 /* reloaded WCRR from WLDR */
83}
84
85static void omap_wdt_enable(struct omap_wdt_dev *wdev)
86{
87 void __iomem *base = wdev->base;
88
89 /* Sequence to enable the watchdog */
90 __raw_writel(0xBBBB, base + OMAP_WATCHDOG_SPR);
91 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
92 cpu_relax();
93
94 __raw_writel(0x4444, base + OMAP_WATCHDOG_SPR);
95 while ((__raw_readl(base + OMAP_WATCHDOG_WPS)) & 0x10)
96 cpu_relax();
97}
98
99static void omap_wdt_disable(struct omap_wdt_dev *wdev)
100{
101 void __iomem *base = wdev->base;
102
103 /* sequence required to disable watchdog */
104 __raw_writel(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
105 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
106 cpu_relax();
107
108 __raw_writel(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
109 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x10)
110 cpu_relax();
111}
112
113static void omap_wdt_adjust_timeout(unsigned new_timeout)
114{
115 if (new_timeout < TIMER_MARGIN_MIN)
116 new_timeout = TIMER_MARGIN_DEFAULT;
117 if (new_timeout > TIMER_MARGIN_MAX)
118 new_timeout = TIMER_MARGIN_MAX;
119 timer_margin = new_timeout;
120}
121
122static void omap_wdt_set_timeout(struct omap_wdt_dev *wdev)
123{
124 u32 pre_margin = GET_WLDR_VAL(timer_margin);
125 void __iomem *base = wdev->base;
126
127 pm_runtime_get_sync(wdev->dev);
128
129 /* just count up at 32 KHz */
130 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
131 cpu_relax();
132
133 __raw_writel(pre_margin, base + OMAP_WATCHDOG_LDR);
134 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x04)
135 cpu_relax();
136
137 pm_runtime_put_sync(wdev->dev);
138}
139
140/*
141 * Allow only one task to hold it open
142 */
143static int omap_wdt_open(struct inode *inode, struct file *file)
144{
145 struct omap_wdt_dev *wdev = platform_get_drvdata(omap_wdt_dev);
146 void __iomem *base = wdev->base;
147
148 if (test_and_set_bit(1, (unsigned long *)&(wdev->omap_wdt_users)))
149 return -EBUSY;
150
151 pm_runtime_get_sync(wdev->dev);
152
153 /* initialize prescaler */
154 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
155 cpu_relax();
156
157 __raw_writel((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
158 while (__raw_readl(base + OMAP_WATCHDOG_WPS) & 0x01)
159 cpu_relax();
160
161 file->private_data = (void *) wdev;
162
163 omap_wdt_set_timeout(wdev);
164 omap_wdt_ping(wdev); /* trigger loading of new timeout value */
165 omap_wdt_enable(wdev);
166
167 pm_runtime_put_sync(wdev->dev);
168
169 return nonseekable_open(inode, file);
170}
171
172static int omap_wdt_release(struct inode *inode, struct file *file)
173{
174 struct omap_wdt_dev *wdev = file->private_data;
175
176 /*
177 * Shut off the timer unless NOWAYOUT is defined.
178 */
179#ifndef CONFIG_WATCHDOG_NOWAYOUT
180 pm_runtime_get_sync(wdev->dev);
181
182 omap_wdt_disable(wdev);
183
184 pm_runtime_put_sync(wdev->dev);
185#else
186 printk(KERN_CRIT "omap_wdt: Unexpected close, not stopping!\n");
187#endif
188 wdev->omap_wdt_users = 0;
189
190 return 0;
191}
192
193static ssize_t omap_wdt_write(struct file *file, const char __user *data,
194 size_t len, loff_t *ppos)
195{
196 struct omap_wdt_dev *wdev = file->private_data;
197
198 /* Refresh LOAD_TIME. */
199 if (len) {
200 pm_runtime_get_sync(wdev->dev);
201 spin_lock(&wdt_lock);
202 omap_wdt_ping(wdev);
203 spin_unlock(&wdt_lock);
204 pm_runtime_put_sync(wdev->dev);
205 }
206 return len;
207}
208
209static long omap_wdt_ioctl(struct file *file, unsigned int cmd,
210 unsigned long arg)
211{
212 struct omap_wdt_dev *wdev;
213 int new_margin;
214 static const struct watchdog_info ident = {
215 .identity = "OMAP Watchdog",
216 .options = WDIOF_SETTIMEOUT,
217 .firmware_version = 0,
218 };
219
220 wdev = file->private_data;
221
222 switch (cmd) {
223 case WDIOC_GETSUPPORT:
224 return copy_to_user((struct watchdog_info __user *)arg, &ident,
225 sizeof(ident));
226 case WDIOC_GETSTATUS:
227 return put_user(0, (int __user *)arg);
228 case WDIOC_GETBOOTSTATUS:
229 if (cpu_is_omap16xx())
230 return put_user(__raw_readw(ARM_SYSST),
231 (int __user *)arg);
232 if (cpu_is_omap24xx())
233 return put_user(omap_prcm_get_reset_sources(),
234 (int __user *)arg);
235 case WDIOC_KEEPALIVE:
236 pm_runtime_get_sync(wdev->dev);
237 spin_lock(&wdt_lock);
238 omap_wdt_ping(wdev);
239 spin_unlock(&wdt_lock);
240 pm_runtime_put_sync(wdev->dev);
241 return 0;
242 case WDIOC_SETTIMEOUT:
243 if (get_user(new_margin, (int __user *)arg))
244 return -EFAULT;
245 omap_wdt_adjust_timeout(new_margin);
246
247 pm_runtime_get_sync(wdev->dev);
248 spin_lock(&wdt_lock);
249 omap_wdt_disable(wdev);
250 omap_wdt_set_timeout(wdev);
251 omap_wdt_enable(wdev);
252
253 omap_wdt_ping(wdev);
254 spin_unlock(&wdt_lock);
255 pm_runtime_put_sync(wdev->dev);
256 /* Fall */
257 case WDIOC_GETTIMEOUT:
258 return put_user(timer_margin, (int __user *)arg);
259 default:
260 return -ENOTTY;
261 }
262}
263
264static const struct file_operations omap_wdt_fops = {
265 .owner = THIS_MODULE,
266 .write = omap_wdt_write,
267 .unlocked_ioctl = omap_wdt_ioctl,
268 .open = omap_wdt_open,
269 .release = omap_wdt_release,
270 .llseek = no_llseek,
271};
272
273static int __devinit omap_wdt_probe(struct platform_device *pdev)
274{
275 struct resource *res, *mem;
276 struct omap_wdt_dev *wdev;
277 int ret;
278
279 /* reserve static register mappings */
280 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
281 if (!res) {
282 ret = -ENOENT;
283 goto err_get_resource;
284 }
285
286 if (omap_wdt_dev) {
287 ret = -EBUSY;
288 goto err_busy;
289 }
290
291 mem = request_mem_region(res->start, resource_size(res), pdev->name);
292 if (!mem) {
293 ret = -EBUSY;
294 goto err_busy;
295 }
296
297 wdev = kzalloc(sizeof(struct omap_wdt_dev), GFP_KERNEL);
298 if (!wdev) {
299 ret = -ENOMEM;
300 goto err_kzalloc;
301 }
302
303 wdev->omap_wdt_users = 0;
304 wdev->mem = mem;
305 wdev->dev = &pdev->dev;
306
307 wdev->base = ioremap(res->start, resource_size(res));
308 if (!wdev->base) {
309 ret = -ENOMEM;
310 goto err_ioremap;
311 }
312
313 platform_set_drvdata(pdev, wdev);
314
315 pm_runtime_enable(wdev->dev);
316 pm_runtime_get_sync(wdev->dev);
317
318 omap_wdt_disable(wdev);
319 omap_wdt_adjust_timeout(timer_margin);
320
321 wdev->omap_wdt_miscdev.parent = &pdev->dev;
322 wdev->omap_wdt_miscdev.minor = WATCHDOG_MINOR;
323 wdev->omap_wdt_miscdev.name = "watchdog";
324 wdev->omap_wdt_miscdev.fops = &omap_wdt_fops;
325
326 ret = misc_register(&(wdev->omap_wdt_miscdev));
327 if (ret)
328 goto err_misc;
329
330 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
331 __raw_readl(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
332 timer_margin);
333
334 pm_runtime_put_sync(wdev->dev);
335
336 omap_wdt_dev = pdev;
337
338 return 0;
339
340err_misc:
341 platform_set_drvdata(pdev, NULL);
342 iounmap(wdev->base);
343
344err_ioremap:
345 wdev->base = NULL;
346 kfree(wdev);
347
348err_kzalloc:
349 release_mem_region(res->start, resource_size(res));
350
351err_busy:
352err_get_resource:
353
354 return ret;
355}
356
357static void omap_wdt_shutdown(struct platform_device *pdev)
358{
359 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
360
361 if (wdev->omap_wdt_users) {
362 pm_runtime_get_sync(wdev->dev);
363 omap_wdt_disable(wdev);
364 pm_runtime_put_sync(wdev->dev);
365 }
366}
367
368static int __devexit omap_wdt_remove(struct platform_device *pdev)
369{
370 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
371 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
372
373 if (!res)
374 return -ENOENT;
375
376 misc_deregister(&(wdev->omap_wdt_miscdev));
377 release_mem_region(res->start, resource_size(res));
378 platform_set_drvdata(pdev, NULL);
379
380 iounmap(wdev->base);
381
382 kfree(wdev);
383 omap_wdt_dev = NULL;
384
385 return 0;
386}
387
388#ifdef CONFIG_PM
389
390/* REVISIT ... not clear this is the best way to handle system suspend; and
391 * it's very inappropriate for selective device suspend (e.g. suspending this
392 * through sysfs rather than by stopping the watchdog daemon). Also, this
393 * may not play well enough with NOWAYOUT...
394 */
395
396static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
397{
398 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
399
400 if (wdev->omap_wdt_users) {
401 pm_runtime_get_sync(wdev->dev);
402 omap_wdt_disable(wdev);
403 pm_runtime_put_sync(wdev->dev);
404 }
405
406 return 0;
407}
408
409static int omap_wdt_resume(struct platform_device *pdev)
410{
411 struct omap_wdt_dev *wdev = platform_get_drvdata(pdev);
412
413 if (wdev->omap_wdt_users) {
414 pm_runtime_get_sync(wdev->dev);
415 omap_wdt_enable(wdev);
416 omap_wdt_ping(wdev);
417 pm_runtime_put_sync(wdev->dev);
418 }
419
420 return 0;
421}
422
423#else
424#define omap_wdt_suspend NULL
425#define omap_wdt_resume NULL
426#endif
427
428static struct platform_driver omap_wdt_driver = {
429 .probe = omap_wdt_probe,
430 .remove = __devexit_p(omap_wdt_remove),
431 .shutdown = omap_wdt_shutdown,
432 .suspend = omap_wdt_suspend,
433 .resume = omap_wdt_resume,
434 .driver = {
435 .owner = THIS_MODULE,
436 .name = "omap_wdt",
437 },
438};
439
440static int __init omap_wdt_init(void)
441{
442 spin_lock_init(&wdt_lock);
443 return platform_driver_register(&omap_wdt_driver);
444}
445
446static void __exit omap_wdt_exit(void)
447{
448 platform_driver_unregister(&omap_wdt_driver);
449}
450
451module_init(omap_wdt_init);
452module_exit(omap_wdt_exit);
453
454MODULE_AUTHOR("George G. Davis");
455MODULE_LICENSE("GPL");
456MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
457MODULE_ALIAS("platform:omap_wdt");
1/*
2 * omap_wdt.c
3 *
4 * Watchdog driver for the TI OMAP 16xx & 24xx/34xx 32KHz (non-secure) watchdog
5 *
6 * Author: MontaVista Software, Inc.
7 * <gdavis@mvista.com> or <source@mvista.com>
8 *
9 * 2003 (c) MontaVista Software, Inc. This file is licensed under the
10 * terms of the GNU General Public License version 2. This program is
11 * licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 *
14 * History:
15 *
16 * 20030527: George G. Davis <gdavis@mvista.com>
17 * Initially based on linux-2.4.19-rmk7-pxa1/drivers/char/sa1100_wdt.c
18 * (c) Copyright 2000 Oleg Drokin <green@crimea.edu>
19 * Based on SoftDog driver by Alan Cox <alan@lxorguk.ukuu.org.uk>
20 *
21 * Copyright (c) 2004 Texas Instruments.
22 * 1. Modified to support OMAP1610 32-KHz watchdog timer
23 * 2. Ported to 2.6 kernel
24 *
25 * Copyright (c) 2005 David Brownell
26 * Use the driver model and standard identifiers; handle bigger timeouts.
27 */
28
29#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
31#include <linux/module.h>
32#include <linux/types.h>
33#include <linux/kernel.h>
34#include <linux/mm.h>
35#include <linux/watchdog.h>
36#include <linux/reboot.h>
37#include <linux/err.h>
38#include <linux/platform_device.h>
39#include <linux/moduleparam.h>
40#include <linux/io.h>
41#include <linux/slab.h>
42#include <linux/pm_runtime.h>
43#include <linux/platform_data/omap-wd-timer.h>
44
45#include "omap_wdt.h"
46
47static bool nowayout = WATCHDOG_NOWAYOUT;
48module_param(nowayout, bool, 0);
49MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started "
50 "(default=" __MODULE_STRING(WATCHDOG_NOWAYOUT) ")");
51
52static unsigned timer_margin;
53module_param(timer_margin, uint, 0);
54MODULE_PARM_DESC(timer_margin, "initial watchdog timeout (in seconds)");
55
56struct omap_wdt_dev {
57 void __iomem *base; /* physical */
58 struct device *dev;
59 bool omap_wdt_users;
60 int wdt_trgr_pattern;
61 struct mutex lock; /* to avoid races with PM */
62};
63
64static void omap_wdt_reload(struct omap_wdt_dev *wdev)
65{
66 void __iomem *base = wdev->base;
67
68 /* wait for posted write to complete */
69 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
70 cpu_relax();
71
72 wdev->wdt_trgr_pattern = ~wdev->wdt_trgr_pattern;
73 writel_relaxed(wdev->wdt_trgr_pattern, (base + OMAP_WATCHDOG_TGR));
74
75 /* wait for posted write to complete */
76 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x08)
77 cpu_relax();
78 /* reloaded WCRR from WLDR */
79}
80
81static void omap_wdt_enable(struct omap_wdt_dev *wdev)
82{
83 void __iomem *base = wdev->base;
84
85 /* Sequence to enable the watchdog */
86 writel_relaxed(0xBBBB, base + OMAP_WATCHDOG_SPR);
87 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
88 cpu_relax();
89
90 writel_relaxed(0x4444, base + OMAP_WATCHDOG_SPR);
91 while ((readl_relaxed(base + OMAP_WATCHDOG_WPS)) & 0x10)
92 cpu_relax();
93}
94
95static void omap_wdt_disable(struct omap_wdt_dev *wdev)
96{
97 void __iomem *base = wdev->base;
98
99 /* sequence required to disable watchdog */
100 writel_relaxed(0xAAAA, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
101 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
102 cpu_relax();
103
104 writel_relaxed(0x5555, base + OMAP_WATCHDOG_SPR); /* TIMER_MODE */
105 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x10)
106 cpu_relax();
107}
108
109static void omap_wdt_set_timer(struct omap_wdt_dev *wdev,
110 unsigned int timeout)
111{
112 u32 pre_margin = GET_WLDR_VAL(timeout);
113 void __iomem *base = wdev->base;
114
115 /* just count up at 32 KHz */
116 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
117 cpu_relax();
118
119 writel_relaxed(pre_margin, base + OMAP_WATCHDOG_LDR);
120 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x04)
121 cpu_relax();
122}
123
124static int omap_wdt_start(struct watchdog_device *wdog)
125{
126 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
127 void __iomem *base = wdev->base;
128
129 mutex_lock(&wdev->lock);
130
131 wdev->omap_wdt_users = true;
132
133 pm_runtime_get_sync(wdev->dev);
134
135 /* initialize prescaler */
136 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
137 cpu_relax();
138
139 writel_relaxed((1 << 5) | (PTV << 2), base + OMAP_WATCHDOG_CNTRL);
140 while (readl_relaxed(base + OMAP_WATCHDOG_WPS) & 0x01)
141 cpu_relax();
142
143 omap_wdt_set_timer(wdev, wdog->timeout);
144 omap_wdt_reload(wdev); /* trigger loading of new timeout value */
145 omap_wdt_enable(wdev);
146
147 mutex_unlock(&wdev->lock);
148
149 return 0;
150}
151
152static int omap_wdt_stop(struct watchdog_device *wdog)
153{
154 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
155
156 mutex_lock(&wdev->lock);
157 omap_wdt_disable(wdev);
158 pm_runtime_put_sync(wdev->dev);
159 wdev->omap_wdt_users = false;
160 mutex_unlock(&wdev->lock);
161 return 0;
162}
163
164static int omap_wdt_ping(struct watchdog_device *wdog)
165{
166 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
167
168 mutex_lock(&wdev->lock);
169 omap_wdt_reload(wdev);
170 mutex_unlock(&wdev->lock);
171
172 return 0;
173}
174
175static int omap_wdt_set_timeout(struct watchdog_device *wdog,
176 unsigned int timeout)
177{
178 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
179
180 mutex_lock(&wdev->lock);
181 omap_wdt_disable(wdev);
182 omap_wdt_set_timer(wdev, timeout);
183 omap_wdt_enable(wdev);
184 omap_wdt_reload(wdev);
185 wdog->timeout = timeout;
186 mutex_unlock(&wdev->lock);
187
188 return 0;
189}
190
191static const struct watchdog_info omap_wdt_info = {
192 .options = WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
193 .identity = "OMAP Watchdog",
194};
195
196static const struct watchdog_ops omap_wdt_ops = {
197 .owner = THIS_MODULE,
198 .start = omap_wdt_start,
199 .stop = omap_wdt_stop,
200 .ping = omap_wdt_ping,
201 .set_timeout = omap_wdt_set_timeout,
202};
203
204static int omap_wdt_probe(struct platform_device *pdev)
205{
206 struct omap_wd_timer_platform_data *pdata = dev_get_platdata(&pdev->dev);
207 struct watchdog_device *omap_wdt;
208 struct resource *res;
209 struct omap_wdt_dev *wdev;
210 u32 rs;
211 int ret;
212
213 omap_wdt = devm_kzalloc(&pdev->dev, sizeof(*omap_wdt), GFP_KERNEL);
214 if (!omap_wdt)
215 return -ENOMEM;
216
217 wdev = devm_kzalloc(&pdev->dev, sizeof(*wdev), GFP_KERNEL);
218 if (!wdev)
219 return -ENOMEM;
220
221 wdev->omap_wdt_users = false;
222 wdev->dev = &pdev->dev;
223 wdev->wdt_trgr_pattern = 0x1234;
224 mutex_init(&wdev->lock);
225
226 /* reserve static register mappings */
227 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
228 wdev->base = devm_ioremap_resource(&pdev->dev, res);
229 if (IS_ERR(wdev->base))
230 return PTR_ERR(wdev->base);
231
232 omap_wdt->info = &omap_wdt_info;
233 omap_wdt->ops = &omap_wdt_ops;
234 omap_wdt->min_timeout = TIMER_MARGIN_MIN;
235 omap_wdt->max_timeout = TIMER_MARGIN_MAX;
236
237 if (timer_margin >= TIMER_MARGIN_MIN &&
238 timer_margin <= TIMER_MARGIN_MAX)
239 omap_wdt->timeout = timer_margin;
240 else
241 omap_wdt->timeout = TIMER_MARGIN_DEFAULT;
242
243 watchdog_set_drvdata(omap_wdt, wdev);
244 watchdog_set_nowayout(omap_wdt, nowayout);
245
246 platform_set_drvdata(pdev, omap_wdt);
247
248 pm_runtime_enable(wdev->dev);
249 pm_runtime_get_sync(wdev->dev);
250
251 if (pdata && pdata->read_reset_sources)
252 rs = pdata->read_reset_sources();
253 else
254 rs = 0;
255 omap_wdt->bootstatus = (rs & (1 << OMAP_MPU_WD_RST_SRC_ID_SHIFT)) ?
256 WDIOF_CARDRESET : 0;
257
258 omap_wdt_disable(wdev);
259
260 ret = watchdog_register_device(omap_wdt);
261 if (ret) {
262 pm_runtime_disable(wdev->dev);
263 return ret;
264 }
265
266 pr_info("OMAP Watchdog Timer Rev 0x%02x: initial timeout %d sec\n",
267 readl_relaxed(wdev->base + OMAP_WATCHDOG_REV) & 0xFF,
268 omap_wdt->timeout);
269
270 pm_runtime_put_sync(wdev->dev);
271
272 return 0;
273}
274
275static void omap_wdt_shutdown(struct platform_device *pdev)
276{
277 struct watchdog_device *wdog = platform_get_drvdata(pdev);
278 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
279
280 mutex_lock(&wdev->lock);
281 if (wdev->omap_wdt_users) {
282 omap_wdt_disable(wdev);
283 pm_runtime_put_sync(wdev->dev);
284 }
285 mutex_unlock(&wdev->lock);
286}
287
288static int omap_wdt_remove(struct platform_device *pdev)
289{
290 struct watchdog_device *wdog = platform_get_drvdata(pdev);
291 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
292
293 pm_runtime_disable(wdev->dev);
294 watchdog_unregister_device(wdog);
295
296 return 0;
297}
298
299#ifdef CONFIG_PM
300
301/* REVISIT ... not clear this is the best way to handle system suspend; and
302 * it's very inappropriate for selective device suspend (e.g. suspending this
303 * through sysfs rather than by stopping the watchdog daemon). Also, this
304 * may not play well enough with NOWAYOUT...
305 */
306
307static int omap_wdt_suspend(struct platform_device *pdev, pm_message_t state)
308{
309 struct watchdog_device *wdog = platform_get_drvdata(pdev);
310 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
311
312 mutex_lock(&wdev->lock);
313 if (wdev->omap_wdt_users) {
314 omap_wdt_disable(wdev);
315 pm_runtime_put_sync(wdev->dev);
316 }
317 mutex_unlock(&wdev->lock);
318
319 return 0;
320}
321
322static int omap_wdt_resume(struct platform_device *pdev)
323{
324 struct watchdog_device *wdog = platform_get_drvdata(pdev);
325 struct omap_wdt_dev *wdev = watchdog_get_drvdata(wdog);
326
327 mutex_lock(&wdev->lock);
328 if (wdev->omap_wdt_users) {
329 pm_runtime_get_sync(wdev->dev);
330 omap_wdt_enable(wdev);
331 omap_wdt_reload(wdev);
332 }
333 mutex_unlock(&wdev->lock);
334
335 return 0;
336}
337
338#else
339#define omap_wdt_suspend NULL
340#define omap_wdt_resume NULL
341#endif
342
343static const struct of_device_id omap_wdt_of_match[] = {
344 { .compatible = "ti,omap3-wdt", },
345 {},
346};
347MODULE_DEVICE_TABLE(of, omap_wdt_of_match);
348
349static struct platform_driver omap_wdt_driver = {
350 .probe = omap_wdt_probe,
351 .remove = omap_wdt_remove,
352 .shutdown = omap_wdt_shutdown,
353 .suspend = omap_wdt_suspend,
354 .resume = omap_wdt_resume,
355 .driver = {
356 .owner = THIS_MODULE,
357 .name = "omap_wdt",
358 .of_match_table = omap_wdt_of_match,
359 },
360};
361
362module_platform_driver(omap_wdt_driver);
363
364MODULE_AUTHOR("George G. Davis");
365MODULE_LICENSE("GPL");
366MODULE_ALIAS("platform:omap_wdt");