Loading...
1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/major.h>
24#include <linux/string.h>
25#include <linux/ptrace.h>
26#include <linux/ioport.h>
27#include <linux/circ_buf.h>
28#include <linux/serial.h>
29#include <linux/sysrq.h>
30#include <linux/console.h>
31#include <linux/spinlock.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/init.h>
35#include <linux/of_device.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/prom.h>
40
41#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
42#define SUPPORT_SYSRQ
43#endif
44
45#include <linux/serial_core.h>
46
47#include "suncore.h"
48#include "sunsab.h"
49
50struct uart_sunsab_port {
51 struct uart_port port; /* Generic UART port */
52 union sab82532_async_regs __iomem *regs; /* Chip registers */
53 unsigned long irqflags; /* IRQ state flags */
54 int dsr; /* Current DSR state */
55 unsigned int cec_timeout; /* Chip poll timeout... */
56 unsigned int tec_timeout; /* likewise */
57 unsigned char interrupt_mask0;/* ISR0 masking */
58 unsigned char interrupt_mask1;/* ISR1 masking */
59 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
60 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
61 unsigned int gis_shift;
62 int type; /* SAB82532 version */
63
64 /* Setting configuration bits while the transmitter is active
65 * can cause garbage characters to get emitted by the chip.
66 * Therefore, we cache such writes here and do the real register
67 * write the next time the transmitter becomes idle.
68 */
69 unsigned int cached_ebrg;
70 unsigned char cached_mode;
71 unsigned char cached_pvr;
72 unsigned char cached_dafo;
73};
74
75/*
76 * This assumes you have a 29.4912 MHz clock for your UART.
77 */
78#define SAB_BASE_BAUD ( 29491200 / 16 )
79
80static char *sab82532_version[16] = {
81 "V1.0", "V2.0", "V3.2", "V(0x03)",
82 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
83 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
84 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
85};
86
87#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
88#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
89
90#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
91#define SAB82532_XMIT_FIFO_SIZE 32
92
93static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
94{
95 int timeout = up->tec_timeout;
96
97 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
98 udelay(1);
99}
100
101static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
102{
103 int timeout = up->cec_timeout;
104
105 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
106 udelay(1);
107}
108
109static struct tty_struct *
110receive_chars(struct uart_sunsab_port *up,
111 union sab82532_irq_status *stat)
112{
113 struct tty_struct *tty = NULL;
114 unsigned char buf[32];
115 int saw_console_brk = 0;
116 int free_fifo = 0;
117 int count = 0;
118 int i;
119
120 if (up->port.state != NULL) /* Unopened serial console */
121 tty = up->port.state->port.tty;
122
123 /* Read number of BYTES (Character + Status) available. */
124 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
125 count = SAB82532_RECV_FIFO_SIZE;
126 free_fifo++;
127 }
128
129 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
130 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
131 free_fifo++;
132 }
133
134 /* Issue a FIFO read command in case we where idle. */
135 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
136 sunsab_cec_wait(up);
137 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
138 return tty;
139 }
140
141 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
142 free_fifo++;
143
144 /* Read the FIFO. */
145 for (i = 0; i < count; i++)
146 buf[i] = readb(&up->regs->r.rfifo[i]);
147
148 /* Issue Receive Message Complete command. */
149 if (free_fifo) {
150 sunsab_cec_wait(up);
151 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
152 }
153
154 /* Count may be zero for BRK, so we check for it here */
155 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
156 (up->port.line == up->port.cons->index))
157 saw_console_brk = 1;
158
159 for (i = 0; i < count; i++) {
160 unsigned char ch = buf[i], flag;
161
162 if (tty == NULL) {
163 uart_handle_sysrq_char(&up->port, ch);
164 continue;
165 }
166
167 flag = TTY_NORMAL;
168 up->port.icount.rx++;
169
170 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
171 SAB82532_ISR0_FERR |
172 SAB82532_ISR0_RFO)) ||
173 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
174 /*
175 * For statistics only
176 */
177 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
178 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
179 SAB82532_ISR0_FERR);
180 up->port.icount.brk++;
181 /*
182 * We do the SysRQ and SAK checking
183 * here because otherwise the break
184 * may get masked by ignore_status_mask
185 * or read_status_mask.
186 */
187 if (uart_handle_break(&up->port))
188 continue;
189 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
190 up->port.icount.parity++;
191 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
192 up->port.icount.frame++;
193 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
194 up->port.icount.overrun++;
195
196 /*
197 * Mask off conditions which should be ingored.
198 */
199 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
200 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
201
202 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
203 flag = TTY_BREAK;
204 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
205 flag = TTY_PARITY;
206 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
207 flag = TTY_FRAME;
208 }
209
210 if (uart_handle_sysrq_char(&up->port, ch))
211 continue;
212
213 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
214 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
215 tty_insert_flip_char(tty, ch, flag);
216 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
217 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
218 }
219
220 if (saw_console_brk)
221 sun_do_break();
222
223 return tty;
224}
225
226static void sunsab_stop_tx(struct uart_port *);
227static void sunsab_tx_idle(struct uart_sunsab_port *);
228
229static void transmit_chars(struct uart_sunsab_port *up,
230 union sab82532_irq_status *stat)
231{
232 struct circ_buf *xmit = &up->port.state->xmit;
233 int i;
234
235 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
236 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
237 writeb(up->interrupt_mask1, &up->regs->w.imr1);
238 set_bit(SAB82532_ALLS, &up->irqflags);
239 }
240
241#if 0 /* bde@nwlink.com says this check causes problems */
242 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
243 return;
244#endif
245
246 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
247 return;
248
249 set_bit(SAB82532_XPR, &up->irqflags);
250 sunsab_tx_idle(up);
251
252 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
253 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
254 writeb(up->interrupt_mask1, &up->regs->w.imr1);
255 return;
256 }
257
258 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
259 writeb(up->interrupt_mask1, &up->regs->w.imr1);
260 clear_bit(SAB82532_ALLS, &up->irqflags);
261
262 /* Stuff 32 bytes into Transmit FIFO. */
263 clear_bit(SAB82532_XPR, &up->irqflags);
264 for (i = 0; i < up->port.fifosize; i++) {
265 writeb(xmit->buf[xmit->tail],
266 &up->regs->w.xfifo[i]);
267 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
268 up->port.icount.tx++;
269 if (uart_circ_empty(xmit))
270 break;
271 }
272
273 /* Issue a Transmit Frame command. */
274 sunsab_cec_wait(up);
275 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
276
277 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
278 uart_write_wakeup(&up->port);
279
280 if (uart_circ_empty(xmit))
281 sunsab_stop_tx(&up->port);
282}
283
284static void check_status(struct uart_sunsab_port *up,
285 union sab82532_irq_status *stat)
286{
287 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
288 uart_handle_dcd_change(&up->port,
289 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
290
291 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
292 uart_handle_cts_change(&up->port,
293 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
294
295 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
296 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
297 up->port.icount.dsr++;
298 }
299
300 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
301}
302
303static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
304{
305 struct uart_sunsab_port *up = dev_id;
306 struct tty_struct *tty;
307 union sab82532_irq_status status;
308 unsigned long flags;
309 unsigned char gis;
310
311 spin_lock_irqsave(&up->port.lock, flags);
312
313 status.stat = 0;
314 gis = readb(&up->regs->r.gis) >> up->gis_shift;
315 if (gis & 1)
316 status.sreg.isr0 = readb(&up->regs->r.isr0);
317 if (gis & 2)
318 status.sreg.isr1 = readb(&up->regs->r.isr1);
319
320 tty = NULL;
321 if (status.stat) {
322 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
323 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
324 (status.sreg.isr1 & SAB82532_ISR1_BRK))
325 tty = receive_chars(up, &status);
326 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
327 (status.sreg.isr1 & SAB82532_ISR1_CSC))
328 check_status(up, &status);
329 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
330 transmit_chars(up, &status);
331 }
332
333 spin_unlock_irqrestore(&up->port.lock, flags);
334
335 if (tty)
336 tty_flip_buffer_push(tty);
337
338 return IRQ_HANDLED;
339}
340
341/* port->lock is not held. */
342static unsigned int sunsab_tx_empty(struct uart_port *port)
343{
344 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
345 int ret;
346
347 /* Do not need a lock for a state test like this. */
348 if (test_bit(SAB82532_ALLS, &up->irqflags))
349 ret = TIOCSER_TEMT;
350 else
351 ret = 0;
352
353 return ret;
354}
355
356/* port->lock held by caller. */
357static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
358{
359 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
360
361 if (mctrl & TIOCM_RTS) {
362 up->cached_mode &= ~SAB82532_MODE_FRTS;
363 up->cached_mode |= SAB82532_MODE_RTS;
364 } else {
365 up->cached_mode |= (SAB82532_MODE_FRTS |
366 SAB82532_MODE_RTS);
367 }
368 if (mctrl & TIOCM_DTR) {
369 up->cached_pvr &= ~(up->pvr_dtr_bit);
370 } else {
371 up->cached_pvr |= up->pvr_dtr_bit;
372 }
373
374 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
375 if (test_bit(SAB82532_XPR, &up->irqflags))
376 sunsab_tx_idle(up);
377}
378
379/* port->lock is held by caller and interrupts are disabled. */
380static unsigned int sunsab_get_mctrl(struct uart_port *port)
381{
382 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
383 unsigned char val;
384 unsigned int result;
385
386 result = 0;
387
388 val = readb(&up->regs->r.pvr);
389 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
390
391 val = readb(&up->regs->r.vstr);
392 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
393
394 val = readb(&up->regs->r.star);
395 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
396
397 return result;
398}
399
400/* port->lock held by caller. */
401static void sunsab_stop_tx(struct uart_port *port)
402{
403 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
404
405 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
406 writeb(up->interrupt_mask1, &up->regs->w.imr1);
407}
408
409/* port->lock held by caller. */
410static void sunsab_tx_idle(struct uart_sunsab_port *up)
411{
412 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
413 u8 tmp;
414
415 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
416 writeb(up->cached_mode, &up->regs->rw.mode);
417 writeb(up->cached_pvr, &up->regs->rw.pvr);
418 writeb(up->cached_dafo, &up->regs->w.dafo);
419
420 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
421 tmp = readb(&up->regs->rw.ccr2);
422 tmp &= ~0xc0;
423 tmp |= (up->cached_ebrg >> 2) & 0xc0;
424 writeb(tmp, &up->regs->rw.ccr2);
425 }
426}
427
428/* port->lock held by caller. */
429static void sunsab_start_tx(struct uart_port *port)
430{
431 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
432 struct circ_buf *xmit = &up->port.state->xmit;
433 int i;
434
435 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
436 writeb(up->interrupt_mask1, &up->regs->w.imr1);
437
438 if (!test_bit(SAB82532_XPR, &up->irqflags))
439 return;
440
441 clear_bit(SAB82532_ALLS, &up->irqflags);
442 clear_bit(SAB82532_XPR, &up->irqflags);
443
444 for (i = 0; i < up->port.fifosize; i++) {
445 writeb(xmit->buf[xmit->tail],
446 &up->regs->w.xfifo[i]);
447 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
448 up->port.icount.tx++;
449 if (uart_circ_empty(xmit))
450 break;
451 }
452
453 /* Issue a Transmit Frame command. */
454 sunsab_cec_wait(up);
455 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
456}
457
458/* port->lock is not held. */
459static void sunsab_send_xchar(struct uart_port *port, char ch)
460{
461 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
462 unsigned long flags;
463
464 spin_lock_irqsave(&up->port.lock, flags);
465
466 sunsab_tec_wait(up);
467 writeb(ch, &up->regs->w.tic);
468
469 spin_unlock_irqrestore(&up->port.lock, flags);
470}
471
472/* port->lock held by caller. */
473static void sunsab_stop_rx(struct uart_port *port)
474{
475 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
476
477 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
478 writeb(up->interrupt_mask1, &up->regs->w.imr0);
479}
480
481/* port->lock held by caller. */
482static void sunsab_enable_ms(struct uart_port *port)
483{
484 /* For now we always receive these interrupts. */
485}
486
487/* port->lock is not held. */
488static void sunsab_break_ctl(struct uart_port *port, int break_state)
489{
490 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
491 unsigned long flags;
492 unsigned char val;
493
494 spin_lock_irqsave(&up->port.lock, flags);
495
496 val = up->cached_dafo;
497 if (break_state)
498 val |= SAB82532_DAFO_XBRK;
499 else
500 val &= ~SAB82532_DAFO_XBRK;
501 up->cached_dafo = val;
502
503 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
504 if (test_bit(SAB82532_XPR, &up->irqflags))
505 sunsab_tx_idle(up);
506
507 spin_unlock_irqrestore(&up->port.lock, flags);
508}
509
510/* port->lock is not held. */
511static int sunsab_startup(struct uart_port *port)
512{
513 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
514 unsigned long flags;
515 unsigned char tmp;
516 int err = request_irq(up->port.irq, sunsab_interrupt,
517 IRQF_SHARED, "sab", up);
518 if (err)
519 return err;
520
521 spin_lock_irqsave(&up->port.lock, flags);
522
523 /*
524 * Wait for any commands or immediate characters
525 */
526 sunsab_cec_wait(up);
527 sunsab_tec_wait(up);
528
529 /*
530 * Clear the FIFO buffers.
531 */
532 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
533 sunsab_cec_wait(up);
534 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
535
536 /*
537 * Clear the interrupt registers.
538 */
539 (void) readb(&up->regs->r.isr0);
540 (void) readb(&up->regs->r.isr1);
541
542 /*
543 * Now, initialize the UART
544 */
545 writeb(0, &up->regs->w.ccr0); /* power-down */
546 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
547 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
548 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
549 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
550 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
551 writeb(0, &up->regs->w.ccr3);
552 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
553 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
554 SAB82532_MODE_RAC);
555 writeb(up->cached_mode, &up->regs->w.mode);
556 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
557
558 tmp = readb(&up->regs->rw.ccr0);
559 tmp |= SAB82532_CCR0_PU; /* power-up */
560 writeb(tmp, &up->regs->rw.ccr0);
561
562 /*
563 * Finally, enable interrupts
564 */
565 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
566 SAB82532_IMR0_PLLA);
567 writeb(up->interrupt_mask0, &up->regs->w.imr0);
568 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
569 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
570 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
571 SAB82532_IMR1_XPR);
572 writeb(up->interrupt_mask1, &up->regs->w.imr1);
573 set_bit(SAB82532_ALLS, &up->irqflags);
574 set_bit(SAB82532_XPR, &up->irqflags);
575
576 spin_unlock_irqrestore(&up->port.lock, flags);
577
578 return 0;
579}
580
581/* port->lock is not held. */
582static void sunsab_shutdown(struct uart_port *port)
583{
584 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
585 unsigned long flags;
586
587 spin_lock_irqsave(&up->port.lock, flags);
588
589 /* Disable Interrupts */
590 up->interrupt_mask0 = 0xff;
591 writeb(up->interrupt_mask0, &up->regs->w.imr0);
592 up->interrupt_mask1 = 0xff;
593 writeb(up->interrupt_mask1, &up->regs->w.imr1);
594
595 /* Disable break condition */
596 up->cached_dafo = readb(&up->regs->rw.dafo);
597 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
598 writeb(up->cached_dafo, &up->regs->rw.dafo);
599
600 /* Disable Receiver */
601 up->cached_mode &= ~SAB82532_MODE_RAC;
602 writeb(up->cached_mode, &up->regs->rw.mode);
603
604 /*
605 * XXX FIXME
606 *
607 * If the chip is powered down here the system hangs/crashes during
608 * reboot or shutdown. This needs to be investigated further,
609 * similar behaviour occurs in 2.4 when the driver is configured
610 * as a module only. One hint may be that data is sometimes
611 * transmitted at 9600 baud during shutdown (regardless of the
612 * speed the chip was configured for when the port was open).
613 */
614#if 0
615 /* Power Down */
616 tmp = readb(&up->regs->rw.ccr0);
617 tmp &= ~SAB82532_CCR0_PU;
618 writeb(tmp, &up->regs->rw.ccr0);
619#endif
620
621 spin_unlock_irqrestore(&up->port.lock, flags);
622 free_irq(up->port.irq, up);
623}
624
625/*
626 * This is used to figure out the divisor speeds.
627 *
628 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
629 *
630 * with 0 <= N < 64 and 0 <= M < 16
631 */
632
633static void calc_ebrg(int baud, int *n_ret, int *m_ret)
634{
635 int n, m;
636
637 if (baud == 0) {
638 *n_ret = 0;
639 *m_ret = 0;
640 return;
641 }
642
643 /*
644 * We scale numbers by 10 so that we get better accuracy
645 * without having to use floating point. Here we increment m
646 * until n is within the valid range.
647 */
648 n = (SAB_BASE_BAUD * 10) / baud;
649 m = 0;
650 while (n >= 640) {
651 n = n / 2;
652 m++;
653 }
654 n = (n+5) / 10;
655 /*
656 * We try very hard to avoid speeds with M == 0 since they may
657 * not work correctly for XTAL frequences above 10 MHz.
658 */
659 if ((m == 0) && ((n & 1) == 0)) {
660 n = n / 2;
661 m++;
662 }
663 *n_ret = n - 1;
664 *m_ret = m;
665}
666
667/* Internal routine, port->lock is held and local interrupts are disabled. */
668static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
669 unsigned int iflag, unsigned int baud,
670 unsigned int quot)
671{
672 unsigned char dafo;
673 int bits, n, m;
674
675 /* Byte size and parity */
676 switch (cflag & CSIZE) {
677 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
678 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
679 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
680 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
681 /* Never happens, but GCC is too dumb to figure it out */
682 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
683 }
684
685 if (cflag & CSTOPB) {
686 dafo |= SAB82532_DAFO_STOP;
687 bits++;
688 }
689
690 if (cflag & PARENB) {
691 dafo |= SAB82532_DAFO_PARE;
692 bits++;
693 }
694
695 if (cflag & PARODD) {
696 dafo |= SAB82532_DAFO_PAR_ODD;
697 } else {
698 dafo |= SAB82532_DAFO_PAR_EVEN;
699 }
700 up->cached_dafo = dafo;
701
702 calc_ebrg(baud, &n, &m);
703
704 up->cached_ebrg = n | (m << 6);
705
706 up->tec_timeout = (10 * 1000000) / baud;
707 up->cec_timeout = up->tec_timeout >> 2;
708
709 /* CTS flow control flags */
710 /* We encode read_status_mask and ignore_status_mask like so:
711 *
712 * ---------------------
713 * | ... | ISR1 | ISR0 |
714 * ---------------------
715 * .. 15 8 7 0
716 */
717
718 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
719 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
720 SAB82532_ISR0_CDSC);
721 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
722 SAB82532_ISR1_ALLS |
723 SAB82532_ISR1_XPR) << 8;
724 if (iflag & INPCK)
725 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
726 SAB82532_ISR0_FERR);
727 if (iflag & (BRKINT | PARMRK))
728 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
729
730 /*
731 * Characteres to ignore
732 */
733 up->port.ignore_status_mask = 0;
734 if (iflag & IGNPAR)
735 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
736 SAB82532_ISR0_FERR);
737 if (iflag & IGNBRK) {
738 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
739 /*
740 * If we're ignoring parity and break indicators,
741 * ignore overruns too (for real raw support).
742 */
743 if (iflag & IGNPAR)
744 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
745 }
746
747 /*
748 * ignore all characters if CREAD is not set
749 */
750 if ((cflag & CREAD) == 0)
751 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
752 SAB82532_ISR0_TCD);
753
754 uart_update_timeout(&up->port, cflag,
755 (up->port.uartclk / (16 * quot)));
756
757 /* Now schedule a register update when the chip's
758 * transmitter is idle.
759 */
760 up->cached_mode |= SAB82532_MODE_RAC;
761 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
762 if (test_bit(SAB82532_XPR, &up->irqflags))
763 sunsab_tx_idle(up);
764}
765
766/* port->lock is not held. */
767static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
768 struct ktermios *old)
769{
770 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
771 unsigned long flags;
772 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
773 unsigned int quot = uart_get_divisor(port, baud);
774
775 spin_lock_irqsave(&up->port.lock, flags);
776 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
777 spin_unlock_irqrestore(&up->port.lock, flags);
778}
779
780static const char *sunsab_type(struct uart_port *port)
781{
782 struct uart_sunsab_port *up = (void *)port;
783 static char buf[36];
784
785 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
786 return buf;
787}
788
789static void sunsab_release_port(struct uart_port *port)
790{
791}
792
793static int sunsab_request_port(struct uart_port *port)
794{
795 return 0;
796}
797
798static void sunsab_config_port(struct uart_port *port, int flags)
799{
800}
801
802static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
803{
804 return -EINVAL;
805}
806
807static struct uart_ops sunsab_pops = {
808 .tx_empty = sunsab_tx_empty,
809 .set_mctrl = sunsab_set_mctrl,
810 .get_mctrl = sunsab_get_mctrl,
811 .stop_tx = sunsab_stop_tx,
812 .start_tx = sunsab_start_tx,
813 .send_xchar = sunsab_send_xchar,
814 .stop_rx = sunsab_stop_rx,
815 .enable_ms = sunsab_enable_ms,
816 .break_ctl = sunsab_break_ctl,
817 .startup = sunsab_startup,
818 .shutdown = sunsab_shutdown,
819 .set_termios = sunsab_set_termios,
820 .type = sunsab_type,
821 .release_port = sunsab_release_port,
822 .request_port = sunsab_request_port,
823 .config_port = sunsab_config_port,
824 .verify_port = sunsab_verify_port,
825};
826
827static struct uart_driver sunsab_reg = {
828 .owner = THIS_MODULE,
829 .driver_name = "sunsab",
830 .dev_name = "ttyS",
831 .major = TTY_MAJOR,
832};
833
834static struct uart_sunsab_port *sunsab_ports;
835
836#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
837
838static void sunsab_console_putchar(struct uart_port *port, int c)
839{
840 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
841
842 sunsab_tec_wait(up);
843 writeb(c, &up->regs->w.tic);
844}
845
846static void sunsab_console_write(struct console *con, const char *s, unsigned n)
847{
848 struct uart_sunsab_port *up = &sunsab_ports[con->index];
849 unsigned long flags;
850 int locked = 1;
851
852 local_irq_save(flags);
853 if (up->port.sysrq) {
854 locked = 0;
855 } else if (oops_in_progress) {
856 locked = spin_trylock(&up->port.lock);
857 } else
858 spin_lock(&up->port.lock);
859
860 uart_console_write(&up->port, s, n, sunsab_console_putchar);
861 sunsab_tec_wait(up);
862
863 if (locked)
864 spin_unlock(&up->port.lock);
865 local_irq_restore(flags);
866}
867
868static int sunsab_console_setup(struct console *con, char *options)
869{
870 struct uart_sunsab_port *up = &sunsab_ports[con->index];
871 unsigned long flags;
872 unsigned int baud, quot;
873
874 /*
875 * The console framework calls us for each and every port
876 * registered. Defer the console setup until the requested
877 * port has been properly discovered. A bit of a hack,
878 * though...
879 */
880 if (up->port.type != PORT_SUNSAB)
881 return -1;
882
883 printk("Console: ttyS%d (SAB82532)\n",
884 (sunsab_reg.minor - 64) + con->index);
885
886 sunserial_console_termios(con, up->port.dev->of_node);
887
888 switch (con->cflag & CBAUD) {
889 case B150: baud = 150; break;
890 case B300: baud = 300; break;
891 case B600: baud = 600; break;
892 case B1200: baud = 1200; break;
893 case B2400: baud = 2400; break;
894 case B4800: baud = 4800; break;
895 default: case B9600: baud = 9600; break;
896 case B19200: baud = 19200; break;
897 case B38400: baud = 38400; break;
898 case B57600: baud = 57600; break;
899 case B115200: baud = 115200; break;
900 case B230400: baud = 230400; break;
901 case B460800: baud = 460800; break;
902 };
903
904 /*
905 * Temporary fix.
906 */
907 spin_lock_init(&up->port.lock);
908
909 /*
910 * Initialize the hardware
911 */
912 sunsab_startup(&up->port);
913
914 spin_lock_irqsave(&up->port.lock, flags);
915
916 /*
917 * Finally, enable interrupts
918 */
919 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
920 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
921 writeb(up->interrupt_mask0, &up->regs->w.imr0);
922 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
923 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
924 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
925 SAB82532_IMR1_XPR;
926 writeb(up->interrupt_mask1, &up->regs->w.imr1);
927
928 quot = uart_get_divisor(&up->port, baud);
929 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
930 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
931
932 spin_unlock_irqrestore(&up->port.lock, flags);
933
934 return 0;
935}
936
937static struct console sunsab_console = {
938 .name = "ttyS",
939 .write = sunsab_console_write,
940 .device = uart_console_device,
941 .setup = sunsab_console_setup,
942 .flags = CON_PRINTBUFFER,
943 .index = -1,
944 .data = &sunsab_reg,
945};
946
947static inline struct console *SUNSAB_CONSOLE(void)
948{
949 return &sunsab_console;
950}
951#else
952#define SUNSAB_CONSOLE() (NULL)
953#define sunsab_console_init() do { } while (0)
954#endif
955
956static int __devinit sunsab_init_one(struct uart_sunsab_port *up,
957 struct platform_device *op,
958 unsigned long offset,
959 int line)
960{
961 up->port.line = line;
962 up->port.dev = &op->dev;
963
964 up->port.mapbase = op->resource[0].start + offset;
965 up->port.membase = of_ioremap(&op->resource[0], offset,
966 sizeof(union sab82532_async_regs),
967 "sab");
968 if (!up->port.membase)
969 return -ENOMEM;
970 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
971
972 up->port.irq = op->archdata.irqs[0];
973
974 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
975 up->port.iotype = UPIO_MEM;
976
977 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
978
979 up->port.ops = &sunsab_pops;
980 up->port.type = PORT_SUNSAB;
981 up->port.uartclk = SAB_BASE_BAUD;
982
983 up->type = readb(&up->regs->r.vstr) & 0x0f;
984 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
985 writeb(0xff, &up->regs->w.pim);
986 if ((up->port.line & 0x1) == 0) {
987 up->pvr_dsr_bit = (1 << 0);
988 up->pvr_dtr_bit = (1 << 1);
989 up->gis_shift = 2;
990 } else {
991 up->pvr_dsr_bit = (1 << 3);
992 up->pvr_dtr_bit = (1 << 2);
993 up->gis_shift = 0;
994 }
995 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
996 writeb(up->cached_pvr, &up->regs->w.pvr);
997 up->cached_mode = readb(&up->regs->rw.mode);
998 up->cached_mode |= SAB82532_MODE_FRTS;
999 writeb(up->cached_mode, &up->regs->rw.mode);
1000 up->cached_mode |= SAB82532_MODE_RTS;
1001 writeb(up->cached_mode, &up->regs->rw.mode);
1002
1003 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
1004 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
1005
1006 return 0;
1007}
1008
1009static int __devinit sab_probe(struct platform_device *op)
1010{
1011 static int inst;
1012 struct uart_sunsab_port *up;
1013 int err;
1014
1015 up = &sunsab_ports[inst * 2];
1016
1017 err = sunsab_init_one(&up[0], op,
1018 0,
1019 (inst * 2) + 0);
1020 if (err)
1021 goto out;
1022
1023 err = sunsab_init_one(&up[1], op,
1024 sizeof(union sab82532_async_regs),
1025 (inst * 2) + 1);
1026 if (err)
1027 goto out1;
1028
1029 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1030 &sunsab_reg, up[0].port.line,
1031 false);
1032
1033 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1034 &sunsab_reg, up[1].port.line,
1035 false);
1036
1037 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1038 if (err)
1039 goto out2;
1040
1041 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1042 if (err)
1043 goto out3;
1044
1045 dev_set_drvdata(&op->dev, &up[0]);
1046
1047 inst++;
1048
1049 return 0;
1050
1051out3:
1052 uart_remove_one_port(&sunsab_reg, &up[0].port);
1053out2:
1054 of_iounmap(&op->resource[0],
1055 up[1].port.membase,
1056 sizeof(union sab82532_async_regs));
1057out1:
1058 of_iounmap(&op->resource[0],
1059 up[0].port.membase,
1060 sizeof(union sab82532_async_regs));
1061out:
1062 return err;
1063}
1064
1065static int __devexit sab_remove(struct platform_device *op)
1066{
1067 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev);
1068
1069 uart_remove_one_port(&sunsab_reg, &up[1].port);
1070 uart_remove_one_port(&sunsab_reg, &up[0].port);
1071 of_iounmap(&op->resource[0],
1072 up[1].port.membase,
1073 sizeof(union sab82532_async_regs));
1074 of_iounmap(&op->resource[0],
1075 up[0].port.membase,
1076 sizeof(union sab82532_async_regs));
1077
1078 dev_set_drvdata(&op->dev, NULL);
1079
1080 return 0;
1081}
1082
1083static const struct of_device_id sab_match[] = {
1084 {
1085 .name = "se",
1086 },
1087 {
1088 .name = "serial",
1089 .compatible = "sab82532",
1090 },
1091 {},
1092};
1093MODULE_DEVICE_TABLE(of, sab_match);
1094
1095static struct platform_driver sab_driver = {
1096 .driver = {
1097 .name = "sab",
1098 .owner = THIS_MODULE,
1099 .of_match_table = sab_match,
1100 },
1101 .probe = sab_probe,
1102 .remove = __devexit_p(sab_remove),
1103};
1104
1105static int __init sunsab_init(void)
1106{
1107 struct device_node *dp;
1108 int err;
1109 int num_channels = 0;
1110
1111 for_each_node_by_name(dp, "se")
1112 num_channels += 2;
1113 for_each_node_by_name(dp, "serial") {
1114 if (of_device_is_compatible(dp, "sab82532"))
1115 num_channels += 2;
1116 }
1117
1118 if (num_channels) {
1119 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1120 num_channels, GFP_KERNEL);
1121 if (!sunsab_ports)
1122 return -ENOMEM;
1123
1124 err = sunserial_register_minors(&sunsab_reg, num_channels);
1125 if (err) {
1126 kfree(sunsab_ports);
1127 sunsab_ports = NULL;
1128
1129 return err;
1130 }
1131 }
1132
1133 return platform_driver_register(&sab_driver);
1134}
1135
1136static void __exit sunsab_exit(void)
1137{
1138 platform_driver_unregister(&sab_driver);
1139 if (sunsab_reg.nr) {
1140 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1141 }
1142
1143 kfree(sunsab_ports);
1144 sunsab_ports = NULL;
1145}
1146
1147module_init(sunsab_init);
1148module_exit(sunsab_exit);
1149
1150MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1151MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1152MODULE_LICENSE("GPL");
1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC.
2 *
3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be)
4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net)
5 *
6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros.
7 * Maxim Krasnyanskiy <maxk@qualcomm.com>
8 *
9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud
10 * rates to be programmed into the UART. Also eliminated a lot of
11 * duplicated code in the console setup.
12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12
13 *
14 * Ported to new 2.5.x UART layer.
15 * David S. Miller <davem@davemloft.net>
16 */
17
18#include <linux/module.h>
19#include <linux/kernel.h>
20#include <linux/errno.h>
21#include <linux/tty.h>
22#include <linux/tty_flip.h>
23#include <linux/major.h>
24#include <linux/string.h>
25#include <linux/ptrace.h>
26#include <linux/ioport.h>
27#include <linux/circ_buf.h>
28#include <linux/serial.h>
29#include <linux/sysrq.h>
30#include <linux/console.h>
31#include <linux/spinlock.h>
32#include <linux/slab.h>
33#include <linux/delay.h>
34#include <linux/init.h>
35#include <linux/of_device.h>
36
37#include <asm/io.h>
38#include <asm/irq.h>
39#include <asm/prom.h>
40#include <asm/setup.h>
41
42#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
43#define SUPPORT_SYSRQ
44#endif
45
46#include <linux/serial_core.h>
47#include <linux/sunserialcore.h>
48
49#include "sunsab.h"
50
51struct uart_sunsab_port {
52 struct uart_port port; /* Generic UART port */
53 union sab82532_async_regs __iomem *regs; /* Chip registers */
54 unsigned long irqflags; /* IRQ state flags */
55 int dsr; /* Current DSR state */
56 unsigned int cec_timeout; /* Chip poll timeout... */
57 unsigned int tec_timeout; /* likewise */
58 unsigned char interrupt_mask0;/* ISR0 masking */
59 unsigned char interrupt_mask1;/* ISR1 masking */
60 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */
61 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */
62 unsigned int gis_shift;
63 int type; /* SAB82532 version */
64
65 /* Setting configuration bits while the transmitter is active
66 * can cause garbage characters to get emitted by the chip.
67 * Therefore, we cache such writes here and do the real register
68 * write the next time the transmitter becomes idle.
69 */
70 unsigned int cached_ebrg;
71 unsigned char cached_mode;
72 unsigned char cached_pvr;
73 unsigned char cached_dafo;
74};
75
76/*
77 * This assumes you have a 29.4912 MHz clock for your UART.
78 */
79#define SAB_BASE_BAUD ( 29491200 / 16 )
80
81static char *sab82532_version[16] = {
82 "V1.0", "V2.0", "V3.2", "V(0x03)",
83 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)",
84 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)",
85 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)"
86};
87
88#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */
89#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */
90
91#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */
92#define SAB82532_XMIT_FIFO_SIZE 32
93
94static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up)
95{
96 int timeout = up->tec_timeout;
97
98 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout)
99 udelay(1);
100}
101
102static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up)
103{
104 int timeout = up->cec_timeout;
105
106 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout)
107 udelay(1);
108}
109
110static struct tty_port *
111receive_chars(struct uart_sunsab_port *up,
112 union sab82532_irq_status *stat)
113{
114 struct tty_port *port = NULL;
115 unsigned char buf[32];
116 int saw_console_brk = 0;
117 int free_fifo = 0;
118 int count = 0;
119 int i;
120
121 if (up->port.state != NULL) /* Unopened serial console */
122 port = &up->port.state->port;
123
124 /* Read number of BYTES (Character + Status) available. */
125 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) {
126 count = SAB82532_RECV_FIFO_SIZE;
127 free_fifo++;
128 }
129
130 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) {
131 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1);
132 free_fifo++;
133 }
134
135 /* Issue a FIFO read command in case we where idle. */
136 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) {
137 sunsab_cec_wait(up);
138 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr);
139 return port;
140 }
141
142 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
143 free_fifo++;
144
145 /* Read the FIFO. */
146 for (i = 0; i < count; i++)
147 buf[i] = readb(&up->regs->r.rfifo[i]);
148
149 /* Issue Receive Message Complete command. */
150 if (free_fifo) {
151 sunsab_cec_wait(up);
152 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr);
153 }
154
155 /* Count may be zero for BRK, so we check for it here */
156 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) &&
157 (up->port.line == up->port.cons->index))
158 saw_console_brk = 1;
159
160 for (i = 0; i < count; i++) {
161 unsigned char ch = buf[i], flag;
162
163 flag = TTY_NORMAL;
164 up->port.icount.rx++;
165
166 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR |
167 SAB82532_ISR0_FERR |
168 SAB82532_ISR0_RFO)) ||
169 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) {
170 /*
171 * For statistics only
172 */
173 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
174 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR |
175 SAB82532_ISR0_FERR);
176 up->port.icount.brk++;
177 /*
178 * We do the SysRQ and SAK checking
179 * here because otherwise the break
180 * may get masked by ignore_status_mask
181 * or read_status_mask.
182 */
183 if (uart_handle_break(&up->port))
184 continue;
185 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
186 up->port.icount.parity++;
187 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
188 up->port.icount.frame++;
189 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
190 up->port.icount.overrun++;
191
192 /*
193 * Mask off conditions which should be ingored.
194 */
195 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff);
196 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff);
197
198 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) {
199 flag = TTY_BREAK;
200 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR)
201 flag = TTY_PARITY;
202 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR)
203 flag = TTY_FRAME;
204 }
205
206 if (uart_handle_sysrq_char(&up->port, ch) || !port)
207 continue;
208
209 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 &&
210 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0)
211 tty_insert_flip_char(port, ch, flag);
212 if (stat->sreg.isr0 & SAB82532_ISR0_RFO)
213 tty_insert_flip_char(port, 0, TTY_OVERRUN);
214 }
215
216 if (saw_console_brk)
217 sun_do_break();
218
219 return port;
220}
221
222static void sunsab_stop_tx(struct uart_port *);
223static void sunsab_tx_idle(struct uart_sunsab_port *);
224
225static void transmit_chars(struct uart_sunsab_port *up,
226 union sab82532_irq_status *stat)
227{
228 struct circ_buf *xmit = &up->port.state->xmit;
229 int i;
230
231 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) {
232 up->interrupt_mask1 |= SAB82532_IMR1_ALLS;
233 writeb(up->interrupt_mask1, &up->regs->w.imr1);
234 set_bit(SAB82532_ALLS, &up->irqflags);
235 }
236
237#if 0 /* bde@nwlink.com says this check causes problems */
238 if (!(stat->sreg.isr1 & SAB82532_ISR1_XPR))
239 return;
240#endif
241
242 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW))
243 return;
244
245 set_bit(SAB82532_XPR, &up->irqflags);
246 sunsab_tx_idle(up);
247
248 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
249 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
250 writeb(up->interrupt_mask1, &up->regs->w.imr1);
251 return;
252 }
253
254 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
255 writeb(up->interrupt_mask1, &up->regs->w.imr1);
256 clear_bit(SAB82532_ALLS, &up->irqflags);
257
258 /* Stuff 32 bytes into Transmit FIFO. */
259 clear_bit(SAB82532_XPR, &up->irqflags);
260 for (i = 0; i < up->port.fifosize; i++) {
261 writeb(xmit->buf[xmit->tail],
262 &up->regs->w.xfifo[i]);
263 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
264 up->port.icount.tx++;
265 if (uart_circ_empty(xmit))
266 break;
267 }
268
269 /* Issue a Transmit Frame command. */
270 sunsab_cec_wait(up);
271 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
272
273 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
274 uart_write_wakeup(&up->port);
275
276 if (uart_circ_empty(xmit))
277 sunsab_stop_tx(&up->port);
278}
279
280static void check_status(struct uart_sunsab_port *up,
281 union sab82532_irq_status *stat)
282{
283 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC)
284 uart_handle_dcd_change(&up->port,
285 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD));
286
287 if (stat->sreg.isr1 & SAB82532_ISR1_CSC)
288 uart_handle_cts_change(&up->port,
289 (readb(&up->regs->r.star) & SAB82532_STAR_CTS));
290
291 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) {
292 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1;
293 up->port.icount.dsr++;
294 }
295
296 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
297}
298
299static irqreturn_t sunsab_interrupt(int irq, void *dev_id)
300{
301 struct uart_sunsab_port *up = dev_id;
302 struct tty_port *port = NULL;
303 union sab82532_irq_status status;
304 unsigned long flags;
305 unsigned char gis;
306
307 spin_lock_irqsave(&up->port.lock, flags);
308
309 status.stat = 0;
310 gis = readb(&up->regs->r.gis) >> up->gis_shift;
311 if (gis & 1)
312 status.sreg.isr0 = readb(&up->regs->r.isr0);
313 if (gis & 2)
314 status.sreg.isr1 = readb(&up->regs->r.isr1);
315
316 if (status.stat) {
317 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
318 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) ||
319 (status.sreg.isr1 & SAB82532_ISR1_BRK))
320 port = receive_chars(up, &status);
321 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) ||
322 (status.sreg.isr1 & SAB82532_ISR1_CSC))
323 check_status(up, &status);
324 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR))
325 transmit_chars(up, &status);
326 }
327
328 spin_unlock_irqrestore(&up->port.lock, flags);
329
330 if (port)
331 tty_flip_buffer_push(port);
332
333 return IRQ_HANDLED;
334}
335
336/* port->lock is not held. */
337static unsigned int sunsab_tx_empty(struct uart_port *port)
338{
339 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
340 int ret;
341
342 /* Do not need a lock for a state test like this. */
343 if (test_bit(SAB82532_ALLS, &up->irqflags))
344 ret = TIOCSER_TEMT;
345 else
346 ret = 0;
347
348 return ret;
349}
350
351/* port->lock held by caller. */
352static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl)
353{
354 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
355
356 if (mctrl & TIOCM_RTS) {
357 up->cached_mode &= ~SAB82532_MODE_FRTS;
358 up->cached_mode |= SAB82532_MODE_RTS;
359 } else {
360 up->cached_mode |= (SAB82532_MODE_FRTS |
361 SAB82532_MODE_RTS);
362 }
363 if (mctrl & TIOCM_DTR) {
364 up->cached_pvr &= ~(up->pvr_dtr_bit);
365 } else {
366 up->cached_pvr |= up->pvr_dtr_bit;
367 }
368
369 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
370 if (test_bit(SAB82532_XPR, &up->irqflags))
371 sunsab_tx_idle(up);
372}
373
374/* port->lock is held by caller and interrupts are disabled. */
375static unsigned int sunsab_get_mctrl(struct uart_port *port)
376{
377 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
378 unsigned char val;
379 unsigned int result;
380
381 result = 0;
382
383 val = readb(&up->regs->r.pvr);
384 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR;
385
386 val = readb(&up->regs->r.vstr);
387 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR;
388
389 val = readb(&up->regs->r.star);
390 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0;
391
392 return result;
393}
394
395/* port->lock held by caller. */
396static void sunsab_stop_tx(struct uart_port *port)
397{
398 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
399
400 up->interrupt_mask1 |= SAB82532_IMR1_XPR;
401 writeb(up->interrupt_mask1, &up->regs->w.imr1);
402}
403
404/* port->lock held by caller. */
405static void sunsab_tx_idle(struct uart_sunsab_port *up)
406{
407 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) {
408 u8 tmp;
409
410 clear_bit(SAB82532_REGS_PENDING, &up->irqflags);
411 writeb(up->cached_mode, &up->regs->rw.mode);
412 writeb(up->cached_pvr, &up->regs->rw.pvr);
413 writeb(up->cached_dafo, &up->regs->w.dafo);
414
415 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr);
416 tmp = readb(&up->regs->rw.ccr2);
417 tmp &= ~0xc0;
418 tmp |= (up->cached_ebrg >> 2) & 0xc0;
419 writeb(tmp, &up->regs->rw.ccr2);
420 }
421}
422
423/* port->lock held by caller. */
424static void sunsab_start_tx(struct uart_port *port)
425{
426 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
427 struct circ_buf *xmit = &up->port.state->xmit;
428 int i;
429
430 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR);
431 writeb(up->interrupt_mask1, &up->regs->w.imr1);
432
433 if (!test_bit(SAB82532_XPR, &up->irqflags))
434 return;
435
436 clear_bit(SAB82532_ALLS, &up->irqflags);
437 clear_bit(SAB82532_XPR, &up->irqflags);
438
439 for (i = 0; i < up->port.fifosize; i++) {
440 writeb(xmit->buf[xmit->tail],
441 &up->regs->w.xfifo[i]);
442 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
443 up->port.icount.tx++;
444 if (uart_circ_empty(xmit))
445 break;
446 }
447
448 /* Issue a Transmit Frame command. */
449 sunsab_cec_wait(up);
450 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr);
451}
452
453/* port->lock is not held. */
454static void sunsab_send_xchar(struct uart_port *port, char ch)
455{
456 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
457 unsigned long flags;
458
459 spin_lock_irqsave(&up->port.lock, flags);
460
461 sunsab_tec_wait(up);
462 writeb(ch, &up->regs->w.tic);
463
464 spin_unlock_irqrestore(&up->port.lock, flags);
465}
466
467/* port->lock held by caller. */
468static void sunsab_stop_rx(struct uart_port *port)
469{
470 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
471
472 up->interrupt_mask0 |= SAB82532_IMR0_TCD;
473 writeb(up->interrupt_mask1, &up->regs->w.imr0);
474}
475
476/* port->lock held by caller. */
477static void sunsab_enable_ms(struct uart_port *port)
478{
479 /* For now we always receive these interrupts. */
480}
481
482/* port->lock is not held. */
483static void sunsab_break_ctl(struct uart_port *port, int break_state)
484{
485 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
486 unsigned long flags;
487 unsigned char val;
488
489 spin_lock_irqsave(&up->port.lock, flags);
490
491 val = up->cached_dafo;
492 if (break_state)
493 val |= SAB82532_DAFO_XBRK;
494 else
495 val &= ~SAB82532_DAFO_XBRK;
496 up->cached_dafo = val;
497
498 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
499 if (test_bit(SAB82532_XPR, &up->irqflags))
500 sunsab_tx_idle(up);
501
502 spin_unlock_irqrestore(&up->port.lock, flags);
503}
504
505/* port->lock is not held. */
506static int sunsab_startup(struct uart_port *port)
507{
508 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
509 unsigned long flags;
510 unsigned char tmp;
511 int err = request_irq(up->port.irq, sunsab_interrupt,
512 IRQF_SHARED, "sab", up);
513 if (err)
514 return err;
515
516 spin_lock_irqsave(&up->port.lock, flags);
517
518 /*
519 * Wait for any commands or immediate characters
520 */
521 sunsab_cec_wait(up);
522 sunsab_tec_wait(up);
523
524 /*
525 * Clear the FIFO buffers.
526 */
527 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr);
528 sunsab_cec_wait(up);
529 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr);
530
531 /*
532 * Clear the interrupt registers.
533 */
534 (void) readb(&up->regs->r.isr0);
535 (void) readb(&up->regs->r.isr1);
536
537 /*
538 * Now, initialize the UART
539 */
540 writeb(0, &up->regs->w.ccr0); /* power-down */
541 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ |
542 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0);
543 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1);
544 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL |
545 SAB82532_CCR2_TOE, &up->regs->w.ccr2);
546 writeb(0, &up->regs->w.ccr3);
547 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4);
548 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS |
549 SAB82532_MODE_RAC);
550 writeb(up->cached_mode, &up->regs->w.mode);
551 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc);
552
553 tmp = readb(&up->regs->rw.ccr0);
554 tmp |= SAB82532_CCR0_PU; /* power-up */
555 writeb(tmp, &up->regs->rw.ccr0);
556
557 /*
558 * Finally, enable interrupts
559 */
560 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
561 SAB82532_IMR0_PLLA);
562 writeb(up->interrupt_mask0, &up->regs->w.imr0);
563 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
564 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
565 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
566 SAB82532_IMR1_XPR);
567 writeb(up->interrupt_mask1, &up->regs->w.imr1);
568 set_bit(SAB82532_ALLS, &up->irqflags);
569 set_bit(SAB82532_XPR, &up->irqflags);
570
571 spin_unlock_irqrestore(&up->port.lock, flags);
572
573 return 0;
574}
575
576/* port->lock is not held. */
577static void sunsab_shutdown(struct uart_port *port)
578{
579 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
580 unsigned long flags;
581
582 spin_lock_irqsave(&up->port.lock, flags);
583
584 /* Disable Interrupts */
585 up->interrupt_mask0 = 0xff;
586 writeb(up->interrupt_mask0, &up->regs->w.imr0);
587 up->interrupt_mask1 = 0xff;
588 writeb(up->interrupt_mask1, &up->regs->w.imr1);
589
590 /* Disable break condition */
591 up->cached_dafo = readb(&up->regs->rw.dafo);
592 up->cached_dafo &= ~SAB82532_DAFO_XBRK;
593 writeb(up->cached_dafo, &up->regs->rw.dafo);
594
595 /* Disable Receiver */
596 up->cached_mode &= ~SAB82532_MODE_RAC;
597 writeb(up->cached_mode, &up->regs->rw.mode);
598
599 /*
600 * XXX FIXME
601 *
602 * If the chip is powered down here the system hangs/crashes during
603 * reboot or shutdown. This needs to be investigated further,
604 * similar behaviour occurs in 2.4 when the driver is configured
605 * as a module only. One hint may be that data is sometimes
606 * transmitted at 9600 baud during shutdown (regardless of the
607 * speed the chip was configured for when the port was open).
608 */
609#if 0
610 /* Power Down */
611 tmp = readb(&up->regs->rw.ccr0);
612 tmp &= ~SAB82532_CCR0_PU;
613 writeb(tmp, &up->regs->rw.ccr0);
614#endif
615
616 spin_unlock_irqrestore(&up->port.lock, flags);
617 free_irq(up->port.irq, up);
618}
619
620/*
621 * This is used to figure out the divisor speeds.
622 *
623 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)),
624 *
625 * with 0 <= N < 64 and 0 <= M < 16
626 */
627
628static void calc_ebrg(int baud, int *n_ret, int *m_ret)
629{
630 int n, m;
631
632 if (baud == 0) {
633 *n_ret = 0;
634 *m_ret = 0;
635 return;
636 }
637
638 /*
639 * We scale numbers by 10 so that we get better accuracy
640 * without having to use floating point. Here we increment m
641 * until n is within the valid range.
642 */
643 n = (SAB_BASE_BAUD * 10) / baud;
644 m = 0;
645 while (n >= 640) {
646 n = n / 2;
647 m++;
648 }
649 n = (n+5) / 10;
650 /*
651 * We try very hard to avoid speeds with M == 0 since they may
652 * not work correctly for XTAL frequences above 10 MHz.
653 */
654 if ((m == 0) && ((n & 1) == 0)) {
655 n = n / 2;
656 m++;
657 }
658 *n_ret = n - 1;
659 *m_ret = m;
660}
661
662/* Internal routine, port->lock is held and local interrupts are disabled. */
663static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag,
664 unsigned int iflag, unsigned int baud,
665 unsigned int quot)
666{
667 unsigned char dafo;
668 int bits, n, m;
669
670 /* Byte size and parity */
671 switch (cflag & CSIZE) {
672 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
673 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break;
674 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break;
675 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break;
676 /* Never happens, but GCC is too dumb to figure it out */
677 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break;
678 }
679
680 if (cflag & CSTOPB) {
681 dafo |= SAB82532_DAFO_STOP;
682 bits++;
683 }
684
685 if (cflag & PARENB) {
686 dafo |= SAB82532_DAFO_PARE;
687 bits++;
688 }
689
690 if (cflag & PARODD) {
691 dafo |= SAB82532_DAFO_PAR_ODD;
692 } else {
693 dafo |= SAB82532_DAFO_PAR_EVEN;
694 }
695 up->cached_dafo = dafo;
696
697 calc_ebrg(baud, &n, &m);
698
699 up->cached_ebrg = n | (m << 6);
700
701 up->tec_timeout = (10 * 1000000) / baud;
702 up->cec_timeout = up->tec_timeout >> 2;
703
704 /* CTS flow control flags */
705 /* We encode read_status_mask and ignore_status_mask like so:
706 *
707 * ---------------------
708 * | ... | ISR1 | ISR0 |
709 * ---------------------
710 * .. 15 8 7 0
711 */
712
713 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME |
714 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF |
715 SAB82532_ISR0_CDSC);
716 up->port.read_status_mask |= (SAB82532_ISR1_CSC |
717 SAB82532_ISR1_ALLS |
718 SAB82532_ISR1_XPR) << 8;
719 if (iflag & INPCK)
720 up->port.read_status_mask |= (SAB82532_ISR0_PERR |
721 SAB82532_ISR0_FERR);
722 if (iflag & (BRKINT | PARMRK))
723 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8);
724
725 /*
726 * Characteres to ignore
727 */
728 up->port.ignore_status_mask = 0;
729 if (iflag & IGNPAR)
730 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR |
731 SAB82532_ISR0_FERR);
732 if (iflag & IGNBRK) {
733 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8);
734 /*
735 * If we're ignoring parity and break indicators,
736 * ignore overruns too (for real raw support).
737 */
738 if (iflag & IGNPAR)
739 up->port.ignore_status_mask |= SAB82532_ISR0_RFO;
740 }
741
742 /*
743 * ignore all characters if CREAD is not set
744 */
745 if ((cflag & CREAD) == 0)
746 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF |
747 SAB82532_ISR0_TCD);
748
749 uart_update_timeout(&up->port, cflag,
750 (up->port.uartclk / (16 * quot)));
751
752 /* Now schedule a register update when the chip's
753 * transmitter is idle.
754 */
755 up->cached_mode |= SAB82532_MODE_RAC;
756 set_bit(SAB82532_REGS_PENDING, &up->irqflags);
757 if (test_bit(SAB82532_XPR, &up->irqflags))
758 sunsab_tx_idle(up);
759}
760
761/* port->lock is not held. */
762static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios,
763 struct ktermios *old)
764{
765 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port;
766 unsigned long flags;
767 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000);
768 unsigned int quot = uart_get_divisor(port, baud);
769
770 spin_lock_irqsave(&up->port.lock, flags);
771 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot);
772 spin_unlock_irqrestore(&up->port.lock, flags);
773}
774
775static const char *sunsab_type(struct uart_port *port)
776{
777 struct uart_sunsab_port *up = (void *)port;
778 static char buf[36];
779
780 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]);
781 return buf;
782}
783
784static void sunsab_release_port(struct uart_port *port)
785{
786}
787
788static int sunsab_request_port(struct uart_port *port)
789{
790 return 0;
791}
792
793static void sunsab_config_port(struct uart_port *port, int flags)
794{
795}
796
797static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser)
798{
799 return -EINVAL;
800}
801
802static struct uart_ops sunsab_pops = {
803 .tx_empty = sunsab_tx_empty,
804 .set_mctrl = sunsab_set_mctrl,
805 .get_mctrl = sunsab_get_mctrl,
806 .stop_tx = sunsab_stop_tx,
807 .start_tx = sunsab_start_tx,
808 .send_xchar = sunsab_send_xchar,
809 .stop_rx = sunsab_stop_rx,
810 .enable_ms = sunsab_enable_ms,
811 .break_ctl = sunsab_break_ctl,
812 .startup = sunsab_startup,
813 .shutdown = sunsab_shutdown,
814 .set_termios = sunsab_set_termios,
815 .type = sunsab_type,
816 .release_port = sunsab_release_port,
817 .request_port = sunsab_request_port,
818 .config_port = sunsab_config_port,
819 .verify_port = sunsab_verify_port,
820};
821
822static struct uart_driver sunsab_reg = {
823 .owner = THIS_MODULE,
824 .driver_name = "sunsab",
825 .dev_name = "ttyS",
826 .major = TTY_MAJOR,
827};
828
829static struct uart_sunsab_port *sunsab_ports;
830
831#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE
832
833static void sunsab_console_putchar(struct uart_port *port, int c)
834{
835 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port;
836
837 sunsab_tec_wait(up);
838 writeb(c, &up->regs->w.tic);
839}
840
841static void sunsab_console_write(struct console *con, const char *s, unsigned n)
842{
843 struct uart_sunsab_port *up = &sunsab_ports[con->index];
844 unsigned long flags;
845 int locked = 1;
846
847 if (up->port.sysrq || oops_in_progress)
848 locked = spin_trylock_irqsave(&up->port.lock, flags);
849 else
850 spin_lock_irqsave(&up->port.lock, flags);
851
852 uart_console_write(&up->port, s, n, sunsab_console_putchar);
853 sunsab_tec_wait(up);
854
855 if (locked)
856 spin_unlock_irqrestore(&up->port.lock, flags);
857}
858
859static int sunsab_console_setup(struct console *con, char *options)
860{
861 struct uart_sunsab_port *up = &sunsab_ports[con->index];
862 unsigned long flags;
863 unsigned int baud, quot;
864
865 /*
866 * The console framework calls us for each and every port
867 * registered. Defer the console setup until the requested
868 * port has been properly discovered. A bit of a hack,
869 * though...
870 */
871 if (up->port.type != PORT_SUNSAB)
872 return -1;
873
874 printk("Console: ttyS%d (SAB82532)\n",
875 (sunsab_reg.minor - 64) + con->index);
876
877 sunserial_console_termios(con, up->port.dev->of_node);
878
879 switch (con->cflag & CBAUD) {
880 case B150: baud = 150; break;
881 case B300: baud = 300; break;
882 case B600: baud = 600; break;
883 case B1200: baud = 1200; break;
884 case B2400: baud = 2400; break;
885 case B4800: baud = 4800; break;
886 default: case B9600: baud = 9600; break;
887 case B19200: baud = 19200; break;
888 case B38400: baud = 38400; break;
889 case B57600: baud = 57600; break;
890 case B115200: baud = 115200; break;
891 case B230400: baud = 230400; break;
892 case B460800: baud = 460800; break;
893 }
894
895 /*
896 * Temporary fix.
897 */
898 spin_lock_init(&up->port.lock);
899
900 /*
901 * Initialize the hardware
902 */
903 sunsab_startup(&up->port);
904
905 spin_lock_irqsave(&up->port.lock, flags);
906
907 /*
908 * Finally, enable interrupts
909 */
910 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR |
911 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC;
912 writeb(up->interrupt_mask0, &up->regs->w.imr0);
913 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS |
914 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN |
915 SAB82532_IMR1_CSC | SAB82532_IMR1_XON |
916 SAB82532_IMR1_XPR;
917 writeb(up->interrupt_mask1, &up->regs->w.imr1);
918
919 quot = uart_get_divisor(&up->port, baud);
920 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot);
921 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS);
922
923 spin_unlock_irqrestore(&up->port.lock, flags);
924
925 return 0;
926}
927
928static struct console sunsab_console = {
929 .name = "ttyS",
930 .write = sunsab_console_write,
931 .device = uart_console_device,
932 .setup = sunsab_console_setup,
933 .flags = CON_PRINTBUFFER,
934 .index = -1,
935 .data = &sunsab_reg,
936};
937
938static inline struct console *SUNSAB_CONSOLE(void)
939{
940 return &sunsab_console;
941}
942#else
943#define SUNSAB_CONSOLE() (NULL)
944#define sunsab_console_init() do { } while (0)
945#endif
946
947static int sunsab_init_one(struct uart_sunsab_port *up,
948 struct platform_device *op,
949 unsigned long offset,
950 int line)
951{
952 up->port.line = line;
953 up->port.dev = &op->dev;
954
955 up->port.mapbase = op->resource[0].start + offset;
956 up->port.membase = of_ioremap(&op->resource[0], offset,
957 sizeof(union sab82532_async_regs),
958 "sab");
959 if (!up->port.membase)
960 return -ENOMEM;
961 up->regs = (union sab82532_async_regs __iomem *) up->port.membase;
962
963 up->port.irq = op->archdata.irqs[0];
964
965 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE;
966 up->port.iotype = UPIO_MEM;
967
968 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc);
969
970 up->port.ops = &sunsab_pops;
971 up->port.type = PORT_SUNSAB;
972 up->port.uartclk = SAB_BASE_BAUD;
973
974 up->type = readb(&up->regs->r.vstr) & 0x0f;
975 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr);
976 writeb(0xff, &up->regs->w.pim);
977 if ((up->port.line & 0x1) == 0) {
978 up->pvr_dsr_bit = (1 << 0);
979 up->pvr_dtr_bit = (1 << 1);
980 up->gis_shift = 2;
981 } else {
982 up->pvr_dsr_bit = (1 << 3);
983 up->pvr_dtr_bit = (1 << 2);
984 up->gis_shift = 0;
985 }
986 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4);
987 writeb(up->cached_pvr, &up->regs->w.pvr);
988 up->cached_mode = readb(&up->regs->rw.mode);
989 up->cached_mode |= SAB82532_MODE_FRTS;
990 writeb(up->cached_mode, &up->regs->rw.mode);
991 up->cached_mode |= SAB82532_MODE_RTS;
992 writeb(up->cached_mode, &up->regs->rw.mode);
993
994 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT;
995 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT;
996
997 return 0;
998}
999
1000static int sab_probe(struct platform_device *op)
1001{
1002 static int inst;
1003 struct uart_sunsab_port *up;
1004 int err;
1005
1006 up = &sunsab_ports[inst * 2];
1007
1008 err = sunsab_init_one(&up[0], op,
1009 0,
1010 (inst * 2) + 0);
1011 if (err)
1012 goto out;
1013
1014 err = sunsab_init_one(&up[1], op,
1015 sizeof(union sab82532_async_regs),
1016 (inst * 2) + 1);
1017 if (err)
1018 goto out1;
1019
1020 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1021 &sunsab_reg, up[0].port.line,
1022 false);
1023
1024 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node,
1025 &sunsab_reg, up[1].port.line,
1026 false);
1027
1028 err = uart_add_one_port(&sunsab_reg, &up[0].port);
1029 if (err)
1030 goto out2;
1031
1032 err = uart_add_one_port(&sunsab_reg, &up[1].port);
1033 if (err)
1034 goto out3;
1035
1036 platform_set_drvdata(op, &up[0]);
1037
1038 inst++;
1039
1040 return 0;
1041
1042out3:
1043 uart_remove_one_port(&sunsab_reg, &up[0].port);
1044out2:
1045 of_iounmap(&op->resource[0],
1046 up[1].port.membase,
1047 sizeof(union sab82532_async_regs));
1048out1:
1049 of_iounmap(&op->resource[0],
1050 up[0].port.membase,
1051 sizeof(union sab82532_async_regs));
1052out:
1053 return err;
1054}
1055
1056static int sab_remove(struct platform_device *op)
1057{
1058 struct uart_sunsab_port *up = platform_get_drvdata(op);
1059
1060 uart_remove_one_port(&sunsab_reg, &up[1].port);
1061 uart_remove_one_port(&sunsab_reg, &up[0].port);
1062 of_iounmap(&op->resource[0],
1063 up[1].port.membase,
1064 sizeof(union sab82532_async_regs));
1065 of_iounmap(&op->resource[0],
1066 up[0].port.membase,
1067 sizeof(union sab82532_async_regs));
1068
1069 return 0;
1070}
1071
1072static const struct of_device_id sab_match[] = {
1073 {
1074 .name = "se",
1075 },
1076 {
1077 .name = "serial",
1078 .compatible = "sab82532",
1079 },
1080 {},
1081};
1082MODULE_DEVICE_TABLE(of, sab_match);
1083
1084static struct platform_driver sab_driver = {
1085 .driver = {
1086 .name = "sab",
1087 .owner = THIS_MODULE,
1088 .of_match_table = sab_match,
1089 },
1090 .probe = sab_probe,
1091 .remove = sab_remove,
1092};
1093
1094static int __init sunsab_init(void)
1095{
1096 struct device_node *dp;
1097 int err;
1098 int num_channels = 0;
1099
1100 for_each_node_by_name(dp, "se")
1101 num_channels += 2;
1102 for_each_node_by_name(dp, "serial") {
1103 if (of_device_is_compatible(dp, "sab82532"))
1104 num_channels += 2;
1105 }
1106
1107 if (num_channels) {
1108 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) *
1109 num_channels, GFP_KERNEL);
1110 if (!sunsab_ports)
1111 return -ENOMEM;
1112
1113 err = sunserial_register_minors(&sunsab_reg, num_channels);
1114 if (err) {
1115 kfree(sunsab_ports);
1116 sunsab_ports = NULL;
1117
1118 return err;
1119 }
1120 }
1121
1122 return platform_driver_register(&sab_driver);
1123}
1124
1125static void __exit sunsab_exit(void)
1126{
1127 platform_driver_unregister(&sab_driver);
1128 if (sunsab_reg.nr) {
1129 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr);
1130 }
1131
1132 kfree(sunsab_ports);
1133 sunsab_ports = NULL;
1134}
1135
1136module_init(sunsab_init);
1137module_exit(sunsab_exit);
1138
1139MODULE_AUTHOR("Eddie C. Dost and David S. Miller");
1140MODULE_DESCRIPTION("Sun SAB82532 serial port driver");
1141MODULE_LICENSE("GPL");