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1/*
2 * Driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
22#include <linux/hrtimer.h>
23#include <linux/module.h>
24#include <linux/io.h>
25#include <linux/ioport.h>
26#include <linux/irq.h>
27#include <linux/init.h>
28#include <linux/console.h>
29#include <linux/tty.h>
30#include <linux/tty_flip.h>
31#include <linux/serial_core.h>
32#include <linux/serial.h>
33#include <linux/clk.h>
34#include <linux/platform_device.h>
35#include <linux/delay.h>
36
37#include "msm_serial.h"
38
39struct msm_port {
40 struct uart_port uart;
41 char name[16];
42 struct clk *clk;
43 struct clk *pclk;
44 unsigned int imr;
45 unsigned int *gsbi_base;
46 int is_uartdm;
47 unsigned int old_snap_state;
48};
49
50static inline void wait_for_xmitr(struct uart_port *port, int bits)
51{
52 if (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY))
53 while ((msm_read(port, UART_ISR) & bits) != bits)
54 cpu_relax();
55}
56
57static void msm_stop_tx(struct uart_port *port)
58{
59 struct msm_port *msm_port = UART_TO_MSM(port);
60
61 msm_port->imr &= ~UART_IMR_TXLEV;
62 msm_write(port, msm_port->imr, UART_IMR);
63}
64
65static void msm_start_tx(struct uart_port *port)
66{
67 struct msm_port *msm_port = UART_TO_MSM(port);
68
69 msm_port->imr |= UART_IMR_TXLEV;
70 msm_write(port, msm_port->imr, UART_IMR);
71}
72
73static void msm_stop_rx(struct uart_port *port)
74{
75 struct msm_port *msm_port = UART_TO_MSM(port);
76
77 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
78 msm_write(port, msm_port->imr, UART_IMR);
79}
80
81static void msm_enable_ms(struct uart_port *port)
82{
83 struct msm_port *msm_port = UART_TO_MSM(port);
84
85 msm_port->imr |= UART_IMR_DELTA_CTS;
86 msm_write(port, msm_port->imr, UART_IMR);
87}
88
89static void handle_rx_dm(struct uart_port *port, unsigned int misr)
90{
91 struct tty_struct *tty = port->state->port.tty;
92 unsigned int sr;
93 int count = 0;
94 struct msm_port *msm_port = UART_TO_MSM(port);
95
96 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
97 port->icount.overrun++;
98 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
99 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
100 }
101
102 if (misr & UART_IMR_RXSTALE) {
103 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
104 msm_port->old_snap_state;
105 msm_port->old_snap_state = 0;
106 } else {
107 count = 4 * (msm_read(port, UART_RFWR));
108 msm_port->old_snap_state += count;
109 }
110
111 /* TODO: Precise error reporting */
112
113 port->icount.rx += count;
114
115 while (count > 0) {
116 unsigned int c;
117
118 sr = msm_read(port, UART_SR);
119 if ((sr & UART_SR_RX_READY) == 0) {
120 msm_port->old_snap_state -= count;
121 break;
122 }
123 c = msm_read(port, UARTDM_RF);
124 if (sr & UART_SR_RX_BREAK) {
125 port->icount.brk++;
126 if (uart_handle_break(port))
127 continue;
128 } else if (sr & UART_SR_PAR_FRAME_ERR)
129 port->icount.frame++;
130
131 /* TODO: handle sysrq */
132 tty_insert_flip_string(tty, (char *) &c,
133 (count > 4) ? 4 : count);
134 count -= 4;
135 }
136
137 tty_flip_buffer_push(tty);
138 if (misr & (UART_IMR_RXSTALE))
139 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
140 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
141 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
142}
143
144static void handle_rx(struct uart_port *port)
145{
146 struct tty_struct *tty = port->state->port.tty;
147 unsigned int sr;
148
149 /*
150 * Handle overrun. My understanding of the hardware is that overrun
151 * is not tied to the RX buffer, so we handle the case out of band.
152 */
153 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
154 port->icount.overrun++;
155 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
156 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
157 }
158
159 /* and now the main RX loop */
160 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
161 unsigned int c;
162 char flag = TTY_NORMAL;
163
164 c = msm_read(port, UART_RF);
165
166 if (sr & UART_SR_RX_BREAK) {
167 port->icount.brk++;
168 if (uart_handle_break(port))
169 continue;
170 } else if (sr & UART_SR_PAR_FRAME_ERR) {
171 port->icount.frame++;
172 } else {
173 port->icount.rx++;
174 }
175
176 /* Mask conditions we're ignorning. */
177 sr &= port->read_status_mask;
178
179 if (sr & UART_SR_RX_BREAK) {
180 flag = TTY_BREAK;
181 } else if (sr & UART_SR_PAR_FRAME_ERR) {
182 flag = TTY_FRAME;
183 }
184
185 if (!uart_handle_sysrq_char(port, c))
186 tty_insert_flip_char(tty, c, flag);
187 }
188
189 tty_flip_buffer_push(tty);
190}
191
192static void reset_dm_count(struct uart_port *port)
193{
194 wait_for_xmitr(port, UART_ISR_TX_READY);
195 msm_write(port, 1, UARTDM_NCF_TX);
196}
197
198static void handle_tx(struct uart_port *port)
199{
200 struct circ_buf *xmit = &port->state->xmit;
201 struct msm_port *msm_port = UART_TO_MSM(port);
202 int sent_tx;
203
204 if (port->x_char) {
205 if (msm_port->is_uartdm)
206 reset_dm_count(port);
207
208 msm_write(port, port->x_char,
209 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
210 port->icount.tx++;
211 port->x_char = 0;
212 }
213
214 if (msm_port->is_uartdm)
215 reset_dm_count(port);
216
217 while (msm_read(port, UART_SR) & UART_SR_TX_READY) {
218 if (uart_circ_empty(xmit)) {
219 /* disable tx interrupts */
220 msm_port->imr &= ~UART_IMR_TXLEV;
221 msm_write(port, msm_port->imr, UART_IMR);
222 break;
223 }
224 msm_write(port, xmit->buf[xmit->tail],
225 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
226
227 if (msm_port->is_uartdm)
228 reset_dm_count(port);
229
230 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
231 port->icount.tx++;
232 sent_tx = 1;
233 }
234
235 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
236 uart_write_wakeup(port);
237}
238
239static void handle_delta_cts(struct uart_port *port)
240{
241 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
242 port->icount.cts++;
243 wake_up_interruptible(&port->state->port.delta_msr_wait);
244}
245
246static irqreturn_t msm_irq(int irq, void *dev_id)
247{
248 struct uart_port *port = dev_id;
249 struct msm_port *msm_port = UART_TO_MSM(port);
250 unsigned int misr;
251
252 spin_lock(&port->lock);
253 misr = msm_read(port, UART_MISR);
254 msm_write(port, 0, UART_IMR); /* disable interrupt */
255
256 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
257 if (msm_port->is_uartdm)
258 handle_rx_dm(port, misr);
259 else
260 handle_rx(port);
261 }
262 if (misr & UART_IMR_TXLEV)
263 handle_tx(port);
264 if (misr & UART_IMR_DELTA_CTS)
265 handle_delta_cts(port);
266
267 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
268 spin_unlock(&port->lock);
269
270 return IRQ_HANDLED;
271}
272
273static unsigned int msm_tx_empty(struct uart_port *port)
274{
275 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
276}
277
278static unsigned int msm_get_mctrl(struct uart_port *port)
279{
280 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
281}
282
283
284static void msm_reset(struct uart_port *port)
285{
286 /* reset everything */
287 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
288 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
289 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
290 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
291 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
292 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
293}
294
295void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
296{
297 unsigned int mr;
298 mr = msm_read(port, UART_MR1);
299
300 if (!(mctrl & TIOCM_RTS)) {
301 mr &= ~UART_MR1_RX_RDY_CTL;
302 msm_write(port, mr, UART_MR1);
303 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
304 } else {
305 mr |= UART_MR1_RX_RDY_CTL;
306 msm_write(port, mr, UART_MR1);
307 }
308}
309
310static void msm_break_ctl(struct uart_port *port, int break_ctl)
311{
312 if (break_ctl)
313 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
314 else
315 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
316}
317
318static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
319{
320 unsigned int baud_code, rxstale, watermark;
321 struct msm_port *msm_port = UART_TO_MSM(port);
322
323 switch (baud) {
324 case 300:
325 baud_code = UART_CSR_300;
326 rxstale = 1;
327 break;
328 case 600:
329 baud_code = UART_CSR_600;
330 rxstale = 1;
331 break;
332 case 1200:
333 baud_code = UART_CSR_1200;
334 rxstale = 1;
335 break;
336 case 2400:
337 baud_code = UART_CSR_2400;
338 rxstale = 1;
339 break;
340 case 4800:
341 baud_code = UART_CSR_4800;
342 rxstale = 1;
343 break;
344 case 9600:
345 baud_code = UART_CSR_9600;
346 rxstale = 2;
347 break;
348 case 14400:
349 baud_code = UART_CSR_14400;
350 rxstale = 3;
351 break;
352 case 19200:
353 baud_code = UART_CSR_19200;
354 rxstale = 4;
355 break;
356 case 28800:
357 baud_code = UART_CSR_28800;
358 rxstale = 6;
359 break;
360 case 38400:
361 baud_code = UART_CSR_38400;
362 rxstale = 8;
363 break;
364 case 57600:
365 baud_code = UART_CSR_57600;
366 rxstale = 16;
367 break;
368 case 115200:
369 default:
370 baud_code = UART_CSR_115200;
371 baud = 115200;
372 rxstale = 31;
373 break;
374 }
375
376 if (msm_port->is_uartdm)
377 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
378
379 msm_write(port, baud_code, UART_CSR);
380
381 /* RX stale watermark */
382 watermark = UART_IPR_STALE_LSB & rxstale;
383 watermark |= UART_IPR_RXSTALE_LAST;
384 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
385 msm_write(port, watermark, UART_IPR);
386
387 /* set RX watermark */
388 watermark = (port->fifosize * 3) / 4;
389 msm_write(port, watermark, UART_RFWR);
390
391 /* set TX watermark */
392 msm_write(port, 10, UART_TFWR);
393
394 if (msm_port->is_uartdm) {
395 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
396 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
397 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
398 }
399
400 return baud;
401}
402
403
404static void msm_init_clock(struct uart_port *port)
405{
406 struct msm_port *msm_port = UART_TO_MSM(port);
407
408 clk_enable(msm_port->clk);
409 if (!IS_ERR(msm_port->pclk))
410 clk_enable(msm_port->pclk);
411 msm_serial_set_mnd_regs(port);
412}
413
414static int msm_startup(struct uart_port *port)
415{
416 struct msm_port *msm_port = UART_TO_MSM(port);
417 unsigned int data, rfr_level;
418 int ret;
419
420 snprintf(msm_port->name, sizeof(msm_port->name),
421 "msm_serial%d", port->line);
422
423 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
424 msm_port->name, port);
425 if (unlikely(ret))
426 return ret;
427
428 msm_init_clock(port);
429
430 if (likely(port->fifosize > 12))
431 rfr_level = port->fifosize - 12;
432 else
433 rfr_level = port->fifosize;
434
435 /* set automatic RFR level */
436 data = msm_read(port, UART_MR1);
437 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
438 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
439 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
440 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
441 msm_write(port, data, UART_MR1);
442
443 /* make sure that RXSTALE count is non-zero */
444 data = msm_read(port, UART_IPR);
445 if (unlikely(!data)) {
446 data |= UART_IPR_RXSTALE_LAST;
447 data |= UART_IPR_STALE_LSB;
448 msm_write(port, data, UART_IPR);
449 }
450
451 data = 0;
452 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
453 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
454 msm_reset(port);
455 data = UART_CR_TX_ENABLE;
456 }
457
458 data |= UART_CR_RX_ENABLE;
459 msm_write(port, data, UART_CR); /* enable TX & RX */
460
461 /* Make sure IPR is not 0 to start with*/
462 if (msm_port->is_uartdm)
463 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
464
465 /* turn on RX and CTS interrupts */
466 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
467 UART_IMR_CURRENT_CTS;
468
469 if (msm_port->is_uartdm) {
470 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
471 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
472 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
473 }
474
475 msm_write(port, msm_port->imr, UART_IMR);
476 return 0;
477}
478
479static void msm_shutdown(struct uart_port *port)
480{
481 struct msm_port *msm_port = UART_TO_MSM(port);
482
483 msm_port->imr = 0;
484 msm_write(port, 0, UART_IMR); /* disable interrupts */
485
486 clk_disable(msm_port->clk);
487
488 free_irq(port->irq, port);
489}
490
491static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
492 struct ktermios *old)
493{
494 unsigned long flags;
495 unsigned int baud, mr;
496
497 spin_lock_irqsave(&port->lock, flags);
498
499 /* calculate and set baud rate */
500 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
501 baud = msm_set_baud_rate(port, baud);
502 if (tty_termios_baud_rate(termios))
503 tty_termios_encode_baud_rate(termios, baud, baud);
504
505 /* calculate parity */
506 mr = msm_read(port, UART_MR2);
507 mr &= ~UART_MR2_PARITY_MODE;
508 if (termios->c_cflag & PARENB) {
509 if (termios->c_cflag & PARODD)
510 mr |= UART_MR2_PARITY_MODE_ODD;
511 else if (termios->c_cflag & CMSPAR)
512 mr |= UART_MR2_PARITY_MODE_SPACE;
513 else
514 mr |= UART_MR2_PARITY_MODE_EVEN;
515 }
516
517 /* calculate bits per char */
518 mr &= ~UART_MR2_BITS_PER_CHAR;
519 switch (termios->c_cflag & CSIZE) {
520 case CS5:
521 mr |= UART_MR2_BITS_PER_CHAR_5;
522 break;
523 case CS6:
524 mr |= UART_MR2_BITS_PER_CHAR_6;
525 break;
526 case CS7:
527 mr |= UART_MR2_BITS_PER_CHAR_7;
528 break;
529 case CS8:
530 default:
531 mr |= UART_MR2_BITS_PER_CHAR_8;
532 break;
533 }
534
535 /* calculate stop bits */
536 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
537 if (termios->c_cflag & CSTOPB)
538 mr |= UART_MR2_STOP_BIT_LEN_TWO;
539 else
540 mr |= UART_MR2_STOP_BIT_LEN_ONE;
541
542 /* set parity, bits per char, and stop bit */
543 msm_write(port, mr, UART_MR2);
544
545 /* calculate and set hardware flow control */
546 mr = msm_read(port, UART_MR1);
547 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
548 if (termios->c_cflag & CRTSCTS) {
549 mr |= UART_MR1_CTS_CTL;
550 mr |= UART_MR1_RX_RDY_CTL;
551 }
552 msm_write(port, mr, UART_MR1);
553
554 /* Configure status bits to ignore based on termio flags. */
555 port->read_status_mask = 0;
556 if (termios->c_iflag & INPCK)
557 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
558 if (termios->c_iflag & (BRKINT | PARMRK))
559 port->read_status_mask |= UART_SR_RX_BREAK;
560
561 uart_update_timeout(port, termios->c_cflag, baud);
562
563 spin_unlock_irqrestore(&port->lock, flags);
564}
565
566static const char *msm_type(struct uart_port *port)
567{
568 return "MSM";
569}
570
571static void msm_release_port(struct uart_port *port)
572{
573 struct platform_device *pdev = to_platform_device(port->dev);
574 struct msm_port *msm_port = UART_TO_MSM(port);
575 struct resource *uart_resource;
576 struct resource *gsbi_resource;
577 resource_size_t size;
578
579 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
580 if (unlikely(!uart_resource))
581 return;
582 size = resource_size(uart_resource);
583
584 release_mem_region(port->mapbase, size);
585 iounmap(port->membase);
586 port->membase = NULL;
587
588 if (msm_port->gsbi_base) {
589 iowrite32(GSBI_PROTOCOL_IDLE, msm_port->gsbi_base +
590 GSBI_CONTROL);
591
592 gsbi_resource = platform_get_resource_byname(pdev,
593 IORESOURCE_MEM,
594 "gsbi_resource");
595
596 if (unlikely(!gsbi_resource))
597 return;
598
599 size = resource_size(gsbi_resource);
600 release_mem_region(gsbi_resource->start, size);
601 iounmap(msm_port->gsbi_base);
602 msm_port->gsbi_base = NULL;
603 }
604}
605
606static int msm_request_port(struct uart_port *port)
607{
608 struct msm_port *msm_port = UART_TO_MSM(port);
609 struct platform_device *pdev = to_platform_device(port->dev);
610 struct resource *uart_resource;
611 struct resource *gsbi_resource;
612 resource_size_t size;
613 int ret;
614
615 uart_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
616 "uart_resource");
617 if (unlikely(!uart_resource))
618 return -ENXIO;
619
620 size = resource_size(uart_resource);
621
622 if (!request_mem_region(port->mapbase, size, "msm_serial"))
623 return -EBUSY;
624
625 port->membase = ioremap(port->mapbase, size);
626 if (!port->membase) {
627 ret = -EBUSY;
628 goto fail_release_port;
629 }
630
631 gsbi_resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
632 "gsbi_resource");
633 /* Is this a GSBI-based port? */
634 if (gsbi_resource) {
635 size = resource_size(gsbi_resource);
636
637 if (!request_mem_region(gsbi_resource->start, size,
638 "msm_serial")) {
639 ret = -EBUSY;
640 goto fail_release_port;
641 }
642
643 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
644 if (!msm_port->gsbi_base) {
645 ret = -EBUSY;
646 goto fail_release_gsbi;
647 }
648 }
649
650 return 0;
651
652fail_release_gsbi:
653 release_mem_region(gsbi_resource->start, size);
654fail_release_port:
655 release_mem_region(port->mapbase, size);
656 return ret;
657}
658
659static void msm_config_port(struct uart_port *port, int flags)
660{
661 struct msm_port *msm_port = UART_TO_MSM(port);
662 int ret;
663 if (flags & UART_CONFIG_TYPE) {
664 port->type = PORT_MSM;
665 ret = msm_request_port(port);
666 if (ret)
667 return;
668 }
669
670 if (msm_port->is_uartdm)
671 iowrite32(GSBI_PROTOCOL_UART, msm_port->gsbi_base +
672 GSBI_CONTROL);
673}
674
675static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
676{
677 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
678 return -EINVAL;
679 if (unlikely(port->irq != ser->irq))
680 return -EINVAL;
681 return 0;
682}
683
684static void msm_power(struct uart_port *port, unsigned int state,
685 unsigned int oldstate)
686{
687 struct msm_port *msm_port = UART_TO_MSM(port);
688
689 switch (state) {
690 case 0:
691 clk_enable(msm_port->clk);
692 if (!IS_ERR(msm_port->pclk))
693 clk_enable(msm_port->pclk);
694 break;
695 case 3:
696 clk_disable(msm_port->clk);
697 if (!IS_ERR(msm_port->pclk))
698 clk_disable(msm_port->pclk);
699 break;
700 default:
701 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
702 }
703}
704
705static struct uart_ops msm_uart_pops = {
706 .tx_empty = msm_tx_empty,
707 .set_mctrl = msm_set_mctrl,
708 .get_mctrl = msm_get_mctrl,
709 .stop_tx = msm_stop_tx,
710 .start_tx = msm_start_tx,
711 .stop_rx = msm_stop_rx,
712 .enable_ms = msm_enable_ms,
713 .break_ctl = msm_break_ctl,
714 .startup = msm_startup,
715 .shutdown = msm_shutdown,
716 .set_termios = msm_set_termios,
717 .type = msm_type,
718 .release_port = msm_release_port,
719 .request_port = msm_request_port,
720 .config_port = msm_config_port,
721 .verify_port = msm_verify_port,
722 .pm = msm_power,
723};
724
725static struct msm_port msm_uart_ports[] = {
726 {
727 .uart = {
728 .iotype = UPIO_MEM,
729 .ops = &msm_uart_pops,
730 .flags = UPF_BOOT_AUTOCONF,
731 .fifosize = 64,
732 .line = 0,
733 },
734 },
735 {
736 .uart = {
737 .iotype = UPIO_MEM,
738 .ops = &msm_uart_pops,
739 .flags = UPF_BOOT_AUTOCONF,
740 .fifosize = 64,
741 .line = 1,
742 },
743 },
744 {
745 .uart = {
746 .iotype = UPIO_MEM,
747 .ops = &msm_uart_pops,
748 .flags = UPF_BOOT_AUTOCONF,
749 .fifosize = 64,
750 .line = 2,
751 },
752 },
753};
754
755#define UART_NR ARRAY_SIZE(msm_uart_ports)
756
757static inline struct uart_port *get_port_from_line(unsigned int line)
758{
759 return &msm_uart_ports[line].uart;
760}
761
762#ifdef CONFIG_SERIAL_MSM_CONSOLE
763
764static void msm_console_putchar(struct uart_port *port, int c)
765{
766 struct msm_port *msm_port = UART_TO_MSM(port);
767
768 if (msm_port->is_uartdm)
769 reset_dm_count(port);
770
771 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
772 ;
773 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
774}
775
776static void msm_console_write(struct console *co, const char *s,
777 unsigned int count)
778{
779 struct uart_port *port;
780 struct msm_port *msm_port;
781
782 BUG_ON(co->index < 0 || co->index >= UART_NR);
783
784 port = get_port_from_line(co->index);
785 msm_port = UART_TO_MSM(port);
786
787 spin_lock(&port->lock);
788 uart_console_write(port, s, count, msm_console_putchar);
789 spin_unlock(&port->lock);
790}
791
792static int __init msm_console_setup(struct console *co, char *options)
793{
794 struct uart_port *port;
795 struct msm_port *msm_port;
796 int baud, flow, bits, parity;
797
798 if (unlikely(co->index >= UART_NR || co->index < 0))
799 return -ENXIO;
800
801 port = get_port_from_line(co->index);
802 msm_port = UART_TO_MSM(port);
803
804 if (unlikely(!port->membase))
805 return -ENXIO;
806
807 port->cons = co;
808
809 msm_init_clock(port);
810
811 if (options)
812 uart_parse_options(options, &baud, &parity, &bits, &flow);
813
814 bits = 8;
815 parity = 'n';
816 flow = 'n';
817 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
818 UART_MR2); /* 8N1 */
819
820 if (baud < 300 || baud > 115200)
821 baud = 115200;
822 msm_set_baud_rate(port, baud);
823
824 msm_reset(port);
825
826 if (msm_port->is_uartdm) {
827 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
828 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
829 }
830
831 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
832
833 return uart_set_options(port, co, baud, parity, bits, flow);
834}
835
836static struct uart_driver msm_uart_driver;
837
838static struct console msm_console = {
839 .name = "ttyMSM",
840 .write = msm_console_write,
841 .device = uart_console_device,
842 .setup = msm_console_setup,
843 .flags = CON_PRINTBUFFER,
844 .index = -1,
845 .data = &msm_uart_driver,
846};
847
848#define MSM_CONSOLE (&msm_console)
849
850#else
851#define MSM_CONSOLE NULL
852#endif
853
854static struct uart_driver msm_uart_driver = {
855 .owner = THIS_MODULE,
856 .driver_name = "msm_serial",
857 .dev_name = "ttyMSM",
858 .nr = UART_NR,
859 .cons = MSM_CONSOLE,
860};
861
862static int __init msm_serial_probe(struct platform_device *pdev)
863{
864 struct msm_port *msm_port;
865 struct resource *resource;
866 struct uart_port *port;
867 int irq;
868
869 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
870 return -ENXIO;
871
872 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
873
874 port = get_port_from_line(pdev->id);
875 port->dev = &pdev->dev;
876 msm_port = UART_TO_MSM(port);
877
878 if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsbi_resource"))
879 msm_port->is_uartdm = 1;
880 else
881 msm_port->is_uartdm = 0;
882
883 if (msm_port->is_uartdm) {
884 msm_port->clk = clk_get(&pdev->dev, "gsbi_uart_clk");
885 msm_port->pclk = clk_get(&pdev->dev, "gsbi_pclk");
886 } else {
887 msm_port->clk = clk_get(&pdev->dev, "uart_clk");
888 msm_port->pclk = ERR_PTR(-ENOENT);
889 }
890
891 if (unlikely(IS_ERR(msm_port->clk) || (IS_ERR(msm_port->pclk) &&
892 msm_port->is_uartdm)))
893 return PTR_ERR(msm_port->clk);
894
895 if (msm_port->is_uartdm)
896 clk_set_rate(msm_port->clk, 7372800);
897
898 port->uartclk = clk_get_rate(msm_port->clk);
899 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
900
901
902 resource = platform_get_resource_byname(pdev, IORESOURCE_MEM,
903 "uart_resource");
904 if (unlikely(!resource))
905 return -ENXIO;
906 port->mapbase = resource->start;
907
908 irq = platform_get_irq(pdev, 0);
909 if (unlikely(irq < 0))
910 return -ENXIO;
911 port->irq = irq;
912
913 platform_set_drvdata(pdev, port);
914
915 return uart_add_one_port(&msm_uart_driver, port);
916}
917
918static int __devexit msm_serial_remove(struct platform_device *pdev)
919{
920 struct msm_port *msm_port = platform_get_drvdata(pdev);
921
922 clk_put(msm_port->clk);
923
924 return 0;
925}
926
927static struct platform_driver msm_platform_driver = {
928 .remove = msm_serial_remove,
929 .driver = {
930 .name = "msm_serial",
931 .owner = THIS_MODULE,
932 },
933};
934
935static int __init msm_serial_init(void)
936{
937 int ret;
938
939 ret = uart_register_driver(&msm_uart_driver);
940 if (unlikely(ret))
941 return ret;
942
943 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
944 if (unlikely(ret))
945 uart_unregister_driver(&msm_uart_driver);
946
947 printk(KERN_INFO "msm_serial: driver initialized\n");
948
949 return ret;
950}
951
952static void __exit msm_serial_exit(void)
953{
954#ifdef CONFIG_SERIAL_MSM_CONSOLE
955 unregister_console(&msm_console);
956#endif
957 platform_driver_unregister(&msm_platform_driver);
958 uart_unregister_driver(&msm_uart_driver);
959}
960
961module_init(msm_serial_init);
962module_exit(msm_serial_exit);
963
964MODULE_AUTHOR("Robert Love <rlove@google.com>");
965MODULE_DESCRIPTION("Driver for msm7x serial device");
966MODULE_LICENSE("GPL");
1/*
2 * Driver for msm7k serial device and console
3 *
4 * Copyright (C) 2007 Google, Inc.
5 * Author: Robert Love <rlove@google.com>
6 * Copyright (c) 2011, Code Aurora Forum. All rights reserved.
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#if defined(CONFIG_SERIAL_MSM_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
19# define SUPPORT_SYSRQ
20#endif
21
22#include <linux/atomic.h>
23#include <linux/hrtimer.h>
24#include <linux/module.h>
25#include <linux/io.h>
26#include <linux/ioport.h>
27#include <linux/irq.h>
28#include <linux/init.h>
29#include <linux/console.h>
30#include <linux/tty.h>
31#include <linux/tty_flip.h>
32#include <linux/serial_core.h>
33#include <linux/serial.h>
34#include <linux/clk.h>
35#include <linux/platform_device.h>
36#include <linux/delay.h>
37#include <linux/of.h>
38#include <linux/of_device.h>
39
40#include "msm_serial.h"
41
42enum {
43 UARTDM_1P1 = 1,
44 UARTDM_1P2,
45 UARTDM_1P3,
46 UARTDM_1P4,
47};
48
49struct msm_port {
50 struct uart_port uart;
51 char name[16];
52 struct clk *clk;
53 struct clk *pclk;
54 unsigned int imr;
55 void __iomem *gsbi_base;
56 int is_uartdm;
57 unsigned int old_snap_state;
58};
59
60static inline void wait_for_xmitr(struct uart_port *port)
61{
62 while (!(msm_read(port, UART_SR) & UART_SR_TX_EMPTY)) {
63 if (msm_read(port, UART_ISR) & UART_ISR_TX_READY)
64 break;
65 udelay(1);
66 }
67 msm_write(port, UART_CR_CMD_RESET_TX_READY, UART_CR);
68}
69
70static void msm_stop_tx(struct uart_port *port)
71{
72 struct msm_port *msm_port = UART_TO_MSM(port);
73
74 msm_port->imr &= ~UART_IMR_TXLEV;
75 msm_write(port, msm_port->imr, UART_IMR);
76}
77
78static void msm_start_tx(struct uart_port *port)
79{
80 struct msm_port *msm_port = UART_TO_MSM(port);
81
82 msm_port->imr |= UART_IMR_TXLEV;
83 msm_write(port, msm_port->imr, UART_IMR);
84}
85
86static void msm_stop_rx(struct uart_port *port)
87{
88 struct msm_port *msm_port = UART_TO_MSM(port);
89
90 msm_port->imr &= ~(UART_IMR_RXLEV | UART_IMR_RXSTALE);
91 msm_write(port, msm_port->imr, UART_IMR);
92}
93
94static void msm_enable_ms(struct uart_port *port)
95{
96 struct msm_port *msm_port = UART_TO_MSM(port);
97
98 msm_port->imr |= UART_IMR_DELTA_CTS;
99 msm_write(port, msm_port->imr, UART_IMR);
100}
101
102static void handle_rx_dm(struct uart_port *port, unsigned int misr)
103{
104 struct tty_port *tport = &port->state->port;
105 unsigned int sr;
106 int count = 0;
107 struct msm_port *msm_port = UART_TO_MSM(port);
108
109 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
110 port->icount.overrun++;
111 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
112 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
113 }
114
115 if (misr & UART_IMR_RXSTALE) {
116 count = msm_read(port, UARTDM_RX_TOTAL_SNAP) -
117 msm_port->old_snap_state;
118 msm_port->old_snap_state = 0;
119 } else {
120 count = 4 * (msm_read(port, UART_RFWR));
121 msm_port->old_snap_state += count;
122 }
123
124 /* TODO: Precise error reporting */
125
126 port->icount.rx += count;
127
128 while (count > 0) {
129 unsigned int c;
130
131 sr = msm_read(port, UART_SR);
132 if ((sr & UART_SR_RX_READY) == 0) {
133 msm_port->old_snap_state -= count;
134 break;
135 }
136 c = msm_read(port, UARTDM_RF);
137 if (sr & UART_SR_RX_BREAK) {
138 port->icount.brk++;
139 if (uart_handle_break(port))
140 continue;
141 } else if (sr & UART_SR_PAR_FRAME_ERR)
142 port->icount.frame++;
143
144 /* TODO: handle sysrq */
145 tty_insert_flip_string(tport, (char *)&c,
146 (count > 4) ? 4 : count);
147 count -= 4;
148 }
149
150 spin_unlock(&port->lock);
151 tty_flip_buffer_push(tport);
152 spin_lock(&port->lock);
153
154 if (misr & (UART_IMR_RXSTALE))
155 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
156 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
157 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
158}
159
160static void handle_rx(struct uart_port *port)
161{
162 struct tty_port *tport = &port->state->port;
163 unsigned int sr;
164
165 /*
166 * Handle overrun. My understanding of the hardware is that overrun
167 * is not tied to the RX buffer, so we handle the case out of band.
168 */
169 if ((msm_read(port, UART_SR) & UART_SR_OVERRUN)) {
170 port->icount.overrun++;
171 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
172 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
173 }
174
175 /* and now the main RX loop */
176 while ((sr = msm_read(port, UART_SR)) & UART_SR_RX_READY) {
177 unsigned int c;
178 char flag = TTY_NORMAL;
179
180 c = msm_read(port, UART_RF);
181
182 if (sr & UART_SR_RX_BREAK) {
183 port->icount.brk++;
184 if (uart_handle_break(port))
185 continue;
186 } else if (sr & UART_SR_PAR_FRAME_ERR) {
187 port->icount.frame++;
188 } else {
189 port->icount.rx++;
190 }
191
192 /* Mask conditions we're ignorning. */
193 sr &= port->read_status_mask;
194
195 if (sr & UART_SR_RX_BREAK) {
196 flag = TTY_BREAK;
197 } else if (sr & UART_SR_PAR_FRAME_ERR) {
198 flag = TTY_FRAME;
199 }
200
201 if (!uart_handle_sysrq_char(port, c))
202 tty_insert_flip_char(tport, c, flag);
203 }
204
205 spin_unlock(&port->lock);
206 tty_flip_buffer_push(tport);
207 spin_lock(&port->lock);
208}
209
210static void reset_dm_count(struct uart_port *port, int count)
211{
212 wait_for_xmitr(port);
213 msm_write(port, count, UARTDM_NCF_TX);
214 msm_read(port, UARTDM_NCF_TX);
215}
216
217static void handle_tx(struct uart_port *port)
218{
219 struct circ_buf *xmit = &port->state->xmit;
220 struct msm_port *msm_port = UART_TO_MSM(port);
221 unsigned int tx_count, num_chars;
222 unsigned int tf_pointer = 0;
223
224 tx_count = uart_circ_chars_pending(xmit);
225 tx_count = min3(tx_count, (unsigned int)UART_XMIT_SIZE - xmit->tail,
226 port->fifosize);
227
228 if (port->x_char) {
229 if (msm_port->is_uartdm)
230 reset_dm_count(port, tx_count + 1);
231
232 msm_write(port, port->x_char,
233 msm_port->is_uartdm ? UARTDM_TF : UART_TF);
234 port->icount.tx++;
235 port->x_char = 0;
236 } else if (tx_count && msm_port->is_uartdm) {
237 reset_dm_count(port, tx_count);
238 }
239
240 while (tf_pointer < tx_count) {
241 int i;
242 char buf[4] = { 0 };
243 unsigned int *bf = (unsigned int *)&buf;
244
245 if (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
246 break;
247
248 if (msm_port->is_uartdm)
249 num_chars = min(tx_count - tf_pointer,
250 (unsigned int)sizeof(buf));
251 else
252 num_chars = 1;
253
254 for (i = 0; i < num_chars; i++) {
255 buf[i] = xmit->buf[xmit->tail + i];
256 port->icount.tx++;
257 }
258
259 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
260 xmit->tail = (xmit->tail + num_chars) & (UART_XMIT_SIZE - 1);
261 tf_pointer += num_chars;
262 }
263
264 /* disable tx interrupts if nothing more to send */
265 if (uart_circ_empty(xmit))
266 msm_stop_tx(port);
267
268 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
269 uart_write_wakeup(port);
270}
271
272static void handle_delta_cts(struct uart_port *port)
273{
274 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
275 port->icount.cts++;
276 wake_up_interruptible(&port->state->port.delta_msr_wait);
277}
278
279static irqreturn_t msm_irq(int irq, void *dev_id)
280{
281 struct uart_port *port = dev_id;
282 struct msm_port *msm_port = UART_TO_MSM(port);
283 unsigned int misr;
284
285 spin_lock(&port->lock);
286 misr = msm_read(port, UART_MISR);
287 msm_write(port, 0, UART_IMR); /* disable interrupt */
288
289 if (misr & (UART_IMR_RXLEV | UART_IMR_RXSTALE)) {
290 if (msm_port->is_uartdm)
291 handle_rx_dm(port, misr);
292 else
293 handle_rx(port);
294 }
295 if (misr & UART_IMR_TXLEV)
296 handle_tx(port);
297 if (misr & UART_IMR_DELTA_CTS)
298 handle_delta_cts(port);
299
300 msm_write(port, msm_port->imr, UART_IMR); /* restore interrupt */
301 spin_unlock(&port->lock);
302
303 return IRQ_HANDLED;
304}
305
306static unsigned int msm_tx_empty(struct uart_port *port)
307{
308 return (msm_read(port, UART_SR) & UART_SR_TX_EMPTY) ? TIOCSER_TEMT : 0;
309}
310
311static unsigned int msm_get_mctrl(struct uart_port *port)
312{
313 return TIOCM_CAR | TIOCM_CTS | TIOCM_DSR | TIOCM_RTS;
314}
315
316
317static void msm_reset(struct uart_port *port)
318{
319 struct msm_port *msm_port = UART_TO_MSM(port);
320
321 /* reset everything */
322 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
323 msm_write(port, UART_CR_CMD_RESET_TX, UART_CR);
324 msm_write(port, UART_CR_CMD_RESET_ERR, UART_CR);
325 msm_write(port, UART_CR_CMD_RESET_BREAK_INT, UART_CR);
326 msm_write(port, UART_CR_CMD_RESET_CTS, UART_CR);
327 msm_write(port, UART_CR_CMD_SET_RFR, UART_CR);
328
329 /* Disable DM modes */
330 if (msm_port->is_uartdm)
331 msm_write(port, 0, UARTDM_DMEN);
332}
333
334static void msm_set_mctrl(struct uart_port *port, unsigned int mctrl)
335{
336 unsigned int mr;
337 mr = msm_read(port, UART_MR1);
338
339 if (!(mctrl & TIOCM_RTS)) {
340 mr &= ~UART_MR1_RX_RDY_CTL;
341 msm_write(port, mr, UART_MR1);
342 msm_write(port, UART_CR_CMD_RESET_RFR, UART_CR);
343 } else {
344 mr |= UART_MR1_RX_RDY_CTL;
345 msm_write(port, mr, UART_MR1);
346 }
347}
348
349static void msm_break_ctl(struct uart_port *port, int break_ctl)
350{
351 if (break_ctl)
352 msm_write(port, UART_CR_CMD_START_BREAK, UART_CR);
353 else
354 msm_write(port, UART_CR_CMD_STOP_BREAK, UART_CR);
355}
356
357struct msm_baud_map {
358 u16 divisor;
359 u8 code;
360 u8 rxstale;
361};
362
363static const struct msm_baud_map *
364msm_find_best_baud(struct uart_port *port, unsigned int baud)
365{
366 unsigned int i, divisor;
367 const struct msm_baud_map *entry;
368 static const struct msm_baud_map table[] = {
369 { 1536, 0x00, 1 },
370 { 768, 0x11, 1 },
371 { 384, 0x22, 1 },
372 { 192, 0x33, 1 },
373 { 96, 0x44, 1 },
374 { 48, 0x55, 1 },
375 { 32, 0x66, 1 },
376 { 24, 0x77, 1 },
377 { 16, 0x88, 1 },
378 { 12, 0x99, 6 },
379 { 8, 0xaa, 6 },
380 { 6, 0xbb, 6 },
381 { 4, 0xcc, 6 },
382 { 3, 0xdd, 8 },
383 { 2, 0xee, 16 },
384 { 1, 0xff, 31 },
385 };
386
387 divisor = uart_get_divisor(port, baud);
388
389 for (i = 0, entry = table; i < ARRAY_SIZE(table); i++, entry++)
390 if (entry->divisor <= divisor)
391 break;
392
393 return entry; /* Default to smallest divider */
394}
395
396static int msm_set_baud_rate(struct uart_port *port, unsigned int baud)
397{
398 unsigned int rxstale, watermark;
399 struct msm_port *msm_port = UART_TO_MSM(port);
400 const struct msm_baud_map *entry;
401
402 entry = msm_find_best_baud(port, baud);
403
404 if (msm_port->is_uartdm)
405 msm_write(port, UART_CR_CMD_RESET_RX, UART_CR);
406
407 msm_write(port, entry->code, UART_CSR);
408
409 /* RX stale watermark */
410 rxstale = entry->rxstale;
411 watermark = UART_IPR_STALE_LSB & rxstale;
412 watermark |= UART_IPR_RXSTALE_LAST;
413 watermark |= UART_IPR_STALE_TIMEOUT_MSB & (rxstale << 2);
414 msm_write(port, watermark, UART_IPR);
415
416 /* set RX watermark */
417 watermark = (port->fifosize * 3) / 4;
418 msm_write(port, watermark, UART_RFWR);
419
420 /* set TX watermark */
421 msm_write(port, 10, UART_TFWR);
422
423 if (msm_port->is_uartdm) {
424 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
425 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
426 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
427 }
428
429 return baud;
430}
431
432
433static void msm_init_clock(struct uart_port *port)
434{
435 struct msm_port *msm_port = UART_TO_MSM(port);
436
437 clk_prepare_enable(msm_port->clk);
438 clk_prepare_enable(msm_port->pclk);
439 msm_serial_set_mnd_regs(port);
440}
441
442static int msm_startup(struct uart_port *port)
443{
444 struct msm_port *msm_port = UART_TO_MSM(port);
445 unsigned int data, rfr_level;
446 int ret;
447
448 snprintf(msm_port->name, sizeof(msm_port->name),
449 "msm_serial%d", port->line);
450
451 ret = request_irq(port->irq, msm_irq, IRQF_TRIGGER_HIGH,
452 msm_port->name, port);
453 if (unlikely(ret))
454 return ret;
455
456 msm_init_clock(port);
457
458 if (likely(port->fifosize > 12))
459 rfr_level = port->fifosize - 12;
460 else
461 rfr_level = port->fifosize;
462
463 /* set automatic RFR level */
464 data = msm_read(port, UART_MR1);
465 data &= ~UART_MR1_AUTO_RFR_LEVEL1;
466 data &= ~UART_MR1_AUTO_RFR_LEVEL0;
467 data |= UART_MR1_AUTO_RFR_LEVEL1 & (rfr_level << 2);
468 data |= UART_MR1_AUTO_RFR_LEVEL0 & rfr_level;
469 msm_write(port, data, UART_MR1);
470
471 /* make sure that RXSTALE count is non-zero */
472 data = msm_read(port, UART_IPR);
473 if (unlikely(!data)) {
474 data |= UART_IPR_RXSTALE_LAST;
475 data |= UART_IPR_STALE_LSB;
476 msm_write(port, data, UART_IPR);
477 }
478
479 data = 0;
480 if (!port->cons || (port->cons && !(port->cons->flags & CON_ENABLED))) {
481 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
482 msm_reset(port);
483 data = UART_CR_TX_ENABLE;
484 }
485
486 data |= UART_CR_RX_ENABLE;
487 msm_write(port, data, UART_CR); /* enable TX & RX */
488
489 /* Make sure IPR is not 0 to start with*/
490 if (msm_port->is_uartdm)
491 msm_write(port, UART_IPR_STALE_LSB, UART_IPR);
492
493 /* turn on RX and CTS interrupts */
494 msm_port->imr = UART_IMR_RXLEV | UART_IMR_RXSTALE |
495 UART_IMR_CURRENT_CTS;
496
497 if (msm_port->is_uartdm) {
498 msm_write(port, 0xFFFFFF, UARTDM_DMRX);
499 msm_write(port, UART_CR_CMD_RESET_STALE_INT, UART_CR);
500 msm_write(port, UART_CR_CMD_STALE_EVENT_ENABLE, UART_CR);
501 }
502
503 msm_write(port, msm_port->imr, UART_IMR);
504 return 0;
505}
506
507static void msm_shutdown(struct uart_port *port)
508{
509 struct msm_port *msm_port = UART_TO_MSM(port);
510
511 msm_port->imr = 0;
512 msm_write(port, 0, UART_IMR); /* disable interrupts */
513
514 clk_disable_unprepare(msm_port->clk);
515
516 free_irq(port->irq, port);
517}
518
519static void msm_set_termios(struct uart_port *port, struct ktermios *termios,
520 struct ktermios *old)
521{
522 unsigned long flags;
523 unsigned int baud, mr;
524
525 spin_lock_irqsave(&port->lock, flags);
526
527 /* calculate and set baud rate */
528 baud = uart_get_baud_rate(port, termios, old, 300, 115200);
529 baud = msm_set_baud_rate(port, baud);
530 if (tty_termios_baud_rate(termios))
531 tty_termios_encode_baud_rate(termios, baud, baud);
532
533 /* calculate parity */
534 mr = msm_read(port, UART_MR2);
535 mr &= ~UART_MR2_PARITY_MODE;
536 if (termios->c_cflag & PARENB) {
537 if (termios->c_cflag & PARODD)
538 mr |= UART_MR2_PARITY_MODE_ODD;
539 else if (termios->c_cflag & CMSPAR)
540 mr |= UART_MR2_PARITY_MODE_SPACE;
541 else
542 mr |= UART_MR2_PARITY_MODE_EVEN;
543 }
544
545 /* calculate bits per char */
546 mr &= ~UART_MR2_BITS_PER_CHAR;
547 switch (termios->c_cflag & CSIZE) {
548 case CS5:
549 mr |= UART_MR2_BITS_PER_CHAR_5;
550 break;
551 case CS6:
552 mr |= UART_MR2_BITS_PER_CHAR_6;
553 break;
554 case CS7:
555 mr |= UART_MR2_BITS_PER_CHAR_7;
556 break;
557 case CS8:
558 default:
559 mr |= UART_MR2_BITS_PER_CHAR_8;
560 break;
561 }
562
563 /* calculate stop bits */
564 mr &= ~(UART_MR2_STOP_BIT_LEN_ONE | UART_MR2_STOP_BIT_LEN_TWO);
565 if (termios->c_cflag & CSTOPB)
566 mr |= UART_MR2_STOP_BIT_LEN_TWO;
567 else
568 mr |= UART_MR2_STOP_BIT_LEN_ONE;
569
570 /* set parity, bits per char, and stop bit */
571 msm_write(port, mr, UART_MR2);
572
573 /* calculate and set hardware flow control */
574 mr = msm_read(port, UART_MR1);
575 mr &= ~(UART_MR1_CTS_CTL | UART_MR1_RX_RDY_CTL);
576 if (termios->c_cflag & CRTSCTS) {
577 mr |= UART_MR1_CTS_CTL;
578 mr |= UART_MR1_RX_RDY_CTL;
579 }
580 msm_write(port, mr, UART_MR1);
581
582 /* Configure status bits to ignore based on termio flags. */
583 port->read_status_mask = 0;
584 if (termios->c_iflag & INPCK)
585 port->read_status_mask |= UART_SR_PAR_FRAME_ERR;
586 if (termios->c_iflag & (BRKINT | PARMRK))
587 port->read_status_mask |= UART_SR_RX_BREAK;
588
589 uart_update_timeout(port, termios->c_cflag, baud);
590
591 spin_unlock_irqrestore(&port->lock, flags);
592}
593
594static const char *msm_type(struct uart_port *port)
595{
596 return "MSM";
597}
598
599static void msm_release_port(struct uart_port *port)
600{
601 struct platform_device *pdev = to_platform_device(port->dev);
602 struct msm_port *msm_port = UART_TO_MSM(port);
603 struct resource *uart_resource;
604 struct resource *gsbi_resource;
605 resource_size_t size;
606
607 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
608 if (unlikely(!uart_resource))
609 return;
610 size = resource_size(uart_resource);
611
612 release_mem_region(port->mapbase, size);
613 iounmap(port->membase);
614 port->membase = NULL;
615
616 if (msm_port->gsbi_base) {
617 writel_relaxed(GSBI_PROTOCOL_IDLE,
618 msm_port->gsbi_base + GSBI_CONTROL);
619
620 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
621 if (unlikely(!gsbi_resource))
622 return;
623
624 size = resource_size(gsbi_resource);
625 release_mem_region(gsbi_resource->start, size);
626 iounmap(msm_port->gsbi_base);
627 msm_port->gsbi_base = NULL;
628 }
629}
630
631static int msm_request_port(struct uart_port *port)
632{
633 struct msm_port *msm_port = UART_TO_MSM(port);
634 struct platform_device *pdev = to_platform_device(port->dev);
635 struct resource *uart_resource;
636 struct resource *gsbi_resource;
637 resource_size_t size;
638 int ret;
639
640 uart_resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
641 if (unlikely(!uart_resource))
642 return -ENXIO;
643
644 size = resource_size(uart_resource);
645
646 if (!request_mem_region(port->mapbase, size, "msm_serial"))
647 return -EBUSY;
648
649 port->membase = ioremap(port->mapbase, size);
650 if (!port->membase) {
651 ret = -EBUSY;
652 goto fail_release_port;
653 }
654
655 gsbi_resource = platform_get_resource(pdev, IORESOURCE_MEM, 1);
656 /* Is this a GSBI-based port? */
657 if (gsbi_resource) {
658 size = resource_size(gsbi_resource);
659
660 if (!request_mem_region(gsbi_resource->start, size,
661 "msm_serial")) {
662 ret = -EBUSY;
663 goto fail_release_port_membase;
664 }
665
666 msm_port->gsbi_base = ioremap(gsbi_resource->start, size);
667 if (!msm_port->gsbi_base) {
668 ret = -EBUSY;
669 goto fail_release_gsbi;
670 }
671 }
672
673 return 0;
674
675fail_release_gsbi:
676 release_mem_region(gsbi_resource->start, size);
677fail_release_port_membase:
678 iounmap(port->membase);
679fail_release_port:
680 release_mem_region(port->mapbase, size);
681 return ret;
682}
683
684static void msm_config_port(struct uart_port *port, int flags)
685{
686 struct msm_port *msm_port = UART_TO_MSM(port);
687 int ret;
688 if (flags & UART_CONFIG_TYPE) {
689 port->type = PORT_MSM;
690 ret = msm_request_port(port);
691 if (ret)
692 return;
693 }
694 if (msm_port->gsbi_base)
695 writel_relaxed(GSBI_PROTOCOL_UART,
696 msm_port->gsbi_base + GSBI_CONTROL);
697}
698
699static int msm_verify_port(struct uart_port *port, struct serial_struct *ser)
700{
701 if (unlikely(ser->type != PORT_UNKNOWN && ser->type != PORT_MSM))
702 return -EINVAL;
703 if (unlikely(port->irq != ser->irq))
704 return -EINVAL;
705 return 0;
706}
707
708static void msm_power(struct uart_port *port, unsigned int state,
709 unsigned int oldstate)
710{
711 struct msm_port *msm_port = UART_TO_MSM(port);
712
713 switch (state) {
714 case 0:
715 clk_prepare_enable(msm_port->clk);
716 clk_prepare_enable(msm_port->pclk);
717 break;
718 case 3:
719 clk_disable_unprepare(msm_port->clk);
720 clk_disable_unprepare(msm_port->pclk);
721 break;
722 default:
723 printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
724 }
725}
726
727#ifdef CONFIG_CONSOLE_POLL
728static int msm_poll_init(struct uart_port *port)
729{
730 struct msm_port *msm_port = UART_TO_MSM(port);
731
732 /* Enable single character mode on RX FIFO */
733 if (msm_port->is_uartdm >= UARTDM_1P4)
734 msm_write(port, UARTDM_DMEN_RX_SC_ENABLE, UARTDM_DMEN);
735
736 return 0;
737}
738
739static int msm_poll_get_char_single(struct uart_port *port)
740{
741 struct msm_port *msm_port = UART_TO_MSM(port);
742 unsigned int rf_reg = msm_port->is_uartdm ? UARTDM_RF : UART_RF;
743
744 if (!(msm_read(port, UART_SR) & UART_SR_RX_READY))
745 return NO_POLL_CHAR;
746 else
747 return msm_read(port, rf_reg) & 0xff;
748}
749
750static int msm_poll_get_char_dm_1p3(struct uart_port *port)
751{
752 int c;
753 static u32 slop;
754 static int count;
755 unsigned char *sp = (unsigned char *)&slop;
756
757 /* Check if a previous read had more than one char */
758 if (count) {
759 c = sp[sizeof(slop) - count];
760 count--;
761 /* Or if FIFO is empty */
762 } else if (!(msm_read(port, UART_SR) & UART_SR_RX_READY)) {
763 /*
764 * If RX packing buffer has less than a word, force stale to
765 * push contents into RX FIFO
766 */
767 count = msm_read(port, UARTDM_RXFS);
768 count = (count >> UARTDM_RXFS_BUF_SHIFT) & UARTDM_RXFS_BUF_MASK;
769 if (count) {
770 msm_write(port, UART_CR_CMD_FORCE_STALE, UART_CR);
771 slop = msm_read(port, UARTDM_RF);
772 c = sp[0];
773 count--;
774 } else {
775 c = NO_POLL_CHAR;
776 }
777 /* FIFO has a word */
778 } else {
779 slop = msm_read(port, UARTDM_RF);
780 c = sp[0];
781 count = sizeof(slop) - 1;
782 }
783
784 return c;
785}
786
787static int msm_poll_get_char(struct uart_port *port)
788{
789 u32 imr;
790 int c;
791 struct msm_port *msm_port = UART_TO_MSM(port);
792
793 /* Disable all interrupts */
794 imr = msm_read(port, UART_IMR);
795 msm_write(port, 0, UART_IMR);
796
797 if (msm_port->is_uartdm == UARTDM_1P3)
798 c = msm_poll_get_char_dm_1p3(port);
799 else
800 c = msm_poll_get_char_single(port);
801
802 /* Enable interrupts */
803 msm_write(port, imr, UART_IMR);
804
805 return c;
806}
807
808static void msm_poll_put_char(struct uart_port *port, unsigned char c)
809{
810 u32 imr;
811 struct msm_port *msm_port = UART_TO_MSM(port);
812
813 /* Disable all interrupts */
814 imr = msm_read(port, UART_IMR);
815 msm_write(port, 0, UART_IMR);
816
817 if (msm_port->is_uartdm)
818 reset_dm_count(port, 1);
819
820 /* Wait until FIFO is empty */
821 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
822 cpu_relax();
823
824 /* Write a character */
825 msm_write(port, c, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
826
827 /* Wait until FIFO is empty */
828 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
829 cpu_relax();
830
831 /* Enable interrupts */
832 msm_write(port, imr, UART_IMR);
833
834 return;
835}
836#endif
837
838static struct uart_ops msm_uart_pops = {
839 .tx_empty = msm_tx_empty,
840 .set_mctrl = msm_set_mctrl,
841 .get_mctrl = msm_get_mctrl,
842 .stop_tx = msm_stop_tx,
843 .start_tx = msm_start_tx,
844 .stop_rx = msm_stop_rx,
845 .enable_ms = msm_enable_ms,
846 .break_ctl = msm_break_ctl,
847 .startup = msm_startup,
848 .shutdown = msm_shutdown,
849 .set_termios = msm_set_termios,
850 .type = msm_type,
851 .release_port = msm_release_port,
852 .request_port = msm_request_port,
853 .config_port = msm_config_port,
854 .verify_port = msm_verify_port,
855 .pm = msm_power,
856#ifdef CONFIG_CONSOLE_POLL
857 .poll_init = msm_poll_init,
858 .poll_get_char = msm_poll_get_char,
859 .poll_put_char = msm_poll_put_char,
860#endif
861};
862
863static struct msm_port msm_uart_ports[] = {
864 {
865 .uart = {
866 .iotype = UPIO_MEM,
867 .ops = &msm_uart_pops,
868 .flags = UPF_BOOT_AUTOCONF,
869 .fifosize = 64,
870 .line = 0,
871 },
872 },
873 {
874 .uart = {
875 .iotype = UPIO_MEM,
876 .ops = &msm_uart_pops,
877 .flags = UPF_BOOT_AUTOCONF,
878 .fifosize = 64,
879 .line = 1,
880 },
881 },
882 {
883 .uart = {
884 .iotype = UPIO_MEM,
885 .ops = &msm_uart_pops,
886 .flags = UPF_BOOT_AUTOCONF,
887 .fifosize = 64,
888 .line = 2,
889 },
890 },
891};
892
893#define UART_NR ARRAY_SIZE(msm_uart_ports)
894
895static inline struct uart_port *get_port_from_line(unsigned int line)
896{
897 return &msm_uart_ports[line].uart;
898}
899
900#ifdef CONFIG_SERIAL_MSM_CONSOLE
901static void msm_console_write(struct console *co, const char *s,
902 unsigned int count)
903{
904 int i;
905 struct uart_port *port;
906 struct msm_port *msm_port;
907 int num_newlines = 0;
908 bool replaced = false;
909
910 BUG_ON(co->index < 0 || co->index >= UART_NR);
911
912 port = get_port_from_line(co->index);
913 msm_port = UART_TO_MSM(port);
914
915 /* Account for newlines that will get a carriage return added */
916 for (i = 0; i < count; i++)
917 if (s[i] == '\n')
918 num_newlines++;
919 count += num_newlines;
920
921 spin_lock(&port->lock);
922 if (msm_port->is_uartdm)
923 reset_dm_count(port, count);
924
925 i = 0;
926 while (i < count) {
927 int j;
928 unsigned int num_chars;
929 char buf[4] = { 0 };
930 unsigned int *bf = (unsigned int *)&buf;
931
932 if (msm_port->is_uartdm)
933 num_chars = min(count - i, (unsigned int)sizeof(buf));
934 else
935 num_chars = 1;
936
937 for (j = 0; j < num_chars; j++) {
938 char c = *s;
939
940 if (c == '\n' && !replaced) {
941 buf[j] = '\r';
942 j++;
943 replaced = true;
944 }
945 if (j < num_chars) {
946 buf[j] = c;
947 s++;
948 replaced = false;
949 }
950 }
951
952 while (!(msm_read(port, UART_SR) & UART_SR_TX_READY))
953 cpu_relax();
954
955 msm_write(port, *bf, msm_port->is_uartdm ? UARTDM_TF : UART_TF);
956 i += num_chars;
957 }
958 spin_unlock(&port->lock);
959}
960
961static int __init msm_console_setup(struct console *co, char *options)
962{
963 struct uart_port *port;
964 struct msm_port *msm_port;
965 int baud, flow, bits, parity;
966
967 if (unlikely(co->index >= UART_NR || co->index < 0))
968 return -ENXIO;
969
970 port = get_port_from_line(co->index);
971 msm_port = UART_TO_MSM(port);
972
973 if (unlikely(!port->membase))
974 return -ENXIO;
975
976 msm_init_clock(port);
977
978 if (options)
979 uart_parse_options(options, &baud, &parity, &bits, &flow);
980
981 bits = 8;
982 parity = 'n';
983 flow = 'n';
984 msm_write(port, UART_MR2_BITS_PER_CHAR_8 | UART_MR2_STOP_BIT_LEN_ONE,
985 UART_MR2); /* 8N1 */
986
987 if (baud < 300 || baud > 115200)
988 baud = 115200;
989 msm_set_baud_rate(port, baud);
990
991 msm_reset(port);
992
993 if (msm_port->is_uartdm) {
994 msm_write(port, UART_CR_CMD_PROTECTION_EN, UART_CR);
995 msm_write(port, UART_CR_TX_ENABLE, UART_CR);
996 }
997
998 printk(KERN_INFO "msm_serial: console setup on port #%d\n", port->line);
999
1000 return uart_set_options(port, co, baud, parity, bits, flow);
1001}
1002
1003static struct uart_driver msm_uart_driver;
1004
1005static struct console msm_console = {
1006 .name = "ttyMSM",
1007 .write = msm_console_write,
1008 .device = uart_console_device,
1009 .setup = msm_console_setup,
1010 .flags = CON_PRINTBUFFER,
1011 .index = -1,
1012 .data = &msm_uart_driver,
1013};
1014
1015#define MSM_CONSOLE (&msm_console)
1016
1017#else
1018#define MSM_CONSOLE NULL
1019#endif
1020
1021static struct uart_driver msm_uart_driver = {
1022 .owner = THIS_MODULE,
1023 .driver_name = "msm_serial",
1024 .dev_name = "ttyMSM",
1025 .nr = UART_NR,
1026 .cons = MSM_CONSOLE,
1027};
1028
1029static atomic_t msm_uart_next_id = ATOMIC_INIT(0);
1030
1031static const struct of_device_id msm_uartdm_table[] = {
1032 { .compatible = "qcom,msm-uartdm-v1.1", .data = (void *)UARTDM_1P1 },
1033 { .compatible = "qcom,msm-uartdm-v1.2", .data = (void *)UARTDM_1P2 },
1034 { .compatible = "qcom,msm-uartdm-v1.3", .data = (void *)UARTDM_1P3 },
1035 { .compatible = "qcom,msm-uartdm-v1.4", .data = (void *)UARTDM_1P4 },
1036 { }
1037};
1038
1039static int __init msm_serial_probe(struct platform_device *pdev)
1040{
1041 struct msm_port *msm_port;
1042 struct resource *resource;
1043 struct uart_port *port;
1044 const struct of_device_id *id;
1045 int irq;
1046
1047 if (pdev->id == -1)
1048 pdev->id = atomic_inc_return(&msm_uart_next_id) - 1;
1049
1050 if (unlikely(pdev->id < 0 || pdev->id >= UART_NR))
1051 return -ENXIO;
1052
1053 printk(KERN_INFO "msm_serial: detected port #%d\n", pdev->id);
1054
1055 port = get_port_from_line(pdev->id);
1056 port->dev = &pdev->dev;
1057 msm_port = UART_TO_MSM(port);
1058
1059 id = of_match_device(msm_uartdm_table, &pdev->dev);
1060 if (id)
1061 msm_port->is_uartdm = (unsigned long)id->data;
1062 else
1063 msm_port->is_uartdm = 0;
1064
1065 msm_port->clk = devm_clk_get(&pdev->dev, "core");
1066 if (IS_ERR(msm_port->clk))
1067 return PTR_ERR(msm_port->clk);
1068
1069 if (msm_port->is_uartdm) {
1070 msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
1071 if (IS_ERR(msm_port->pclk))
1072 return PTR_ERR(msm_port->pclk);
1073
1074 clk_set_rate(msm_port->clk, 1843200);
1075 }
1076
1077 port->uartclk = clk_get_rate(msm_port->clk);
1078 printk(KERN_INFO "uartclk = %d\n", port->uartclk);
1079
1080
1081 resource = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1082 if (unlikely(!resource))
1083 return -ENXIO;
1084 port->mapbase = resource->start;
1085
1086 irq = platform_get_irq(pdev, 0);
1087 if (unlikely(irq < 0))
1088 return -ENXIO;
1089 port->irq = irq;
1090
1091 platform_set_drvdata(pdev, port);
1092
1093 return uart_add_one_port(&msm_uart_driver, port);
1094}
1095
1096static int msm_serial_remove(struct platform_device *pdev)
1097{
1098 struct uart_port *port = platform_get_drvdata(pdev);
1099
1100 uart_remove_one_port(&msm_uart_driver, port);
1101
1102 return 0;
1103}
1104
1105static struct of_device_id msm_match_table[] = {
1106 { .compatible = "qcom,msm-uart" },
1107 { .compatible = "qcom,msm-uartdm" },
1108 {}
1109};
1110
1111static struct platform_driver msm_platform_driver = {
1112 .remove = msm_serial_remove,
1113 .driver = {
1114 .name = "msm_serial",
1115 .owner = THIS_MODULE,
1116 .of_match_table = msm_match_table,
1117 },
1118};
1119
1120static int __init msm_serial_init(void)
1121{
1122 int ret;
1123
1124 ret = uart_register_driver(&msm_uart_driver);
1125 if (unlikely(ret))
1126 return ret;
1127
1128 ret = platform_driver_probe(&msm_platform_driver, msm_serial_probe);
1129 if (unlikely(ret))
1130 uart_unregister_driver(&msm_uart_driver);
1131
1132 printk(KERN_INFO "msm_serial: driver initialized\n");
1133
1134 return ret;
1135}
1136
1137static void __exit msm_serial_exit(void)
1138{
1139#ifdef CONFIG_SERIAL_MSM_CONSOLE
1140 unregister_console(&msm_console);
1141#endif
1142 platform_driver_unregister(&msm_platform_driver);
1143 uart_unregister_driver(&msm_uart_driver);
1144}
1145
1146module_init(msm_serial_init);
1147module_exit(msm_serial_exit);
1148
1149MODULE_AUTHOR("Robert Love <rlove@google.com>");
1150MODULE_DESCRIPTION("Driver for msm7x serial device");
1151MODULE_LICENSE("GPL");