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1/*
2 * drivers/spi/spi-fsl-dspi.c
3 *
4 * Copyright 2013 Freescale Semiconductor, Inc.
5 *
6 * Freescale DSPI driver
7 * This file contains a driver for the Freescale DSPI
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 */
15
16#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/interrupt.h>
19#include <linux/errno.h>
20#include <linux/platform_device.h>
21#include <linux/regmap.h>
22#include <linux/sched.h>
23#include <linux/delay.h>
24#include <linux/io.h>
25#include <linux/clk.h>
26#include <linux/err.h>
27#include <linux/spi/spi.h>
28#include <linux/spi/spi_bitbang.h>
29#include <linux/pm_runtime.h>
30#include <linux/of.h>
31#include <linux/of_device.h>
32
33#define DRIVER_NAME "fsl-dspi"
34
35#define TRAN_STATE_RX_VOID 0x01
36#define TRAN_STATE_TX_VOID 0x02
37#define TRAN_STATE_WORD_ODD_NUM 0x04
38
39#define DSPI_FIFO_SIZE 4
40
41#define SPI_MCR 0x00
42#define SPI_MCR_MASTER (1 << 31)
43#define SPI_MCR_PCSIS (0x3F << 16)
44#define SPI_MCR_CLR_TXF (1 << 11)
45#define SPI_MCR_CLR_RXF (1 << 10)
46
47#define SPI_TCR 0x08
48
49#define SPI_CTAR(x) (0x0c + (x * 4))
50#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27)
51#define SPI_CTAR_CPOL(x) ((x) << 26)
52#define SPI_CTAR_CPHA(x) ((x) << 25)
53#define SPI_CTAR_LSBFE(x) ((x) << 24)
54#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22)
55#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20)
56#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18)
57#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16)
58#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12)
59#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8)
60#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4)
61#define SPI_CTAR_BR(x) ((x) & 0x0000000f)
62
63#define SPI_CTAR0_SLAVE 0x0c
64
65#define SPI_SR 0x2c
66#define SPI_SR_EOQF 0x10000000
67
68#define SPI_RSER 0x30
69#define SPI_RSER_EOQFE 0x10000000
70
71#define SPI_PUSHR 0x34
72#define SPI_PUSHR_CONT (1 << 31)
73#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28)
74#define SPI_PUSHR_EOQ (1 << 27)
75#define SPI_PUSHR_CTCNT (1 << 26)
76#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16)
77#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff)
78
79#define SPI_PUSHR_SLAVE 0x34
80
81#define SPI_POPR 0x38
82#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff)
83
84#define SPI_TXFR0 0x3c
85#define SPI_TXFR1 0x40
86#define SPI_TXFR2 0x44
87#define SPI_TXFR3 0x48
88#define SPI_RXFR0 0x7c
89#define SPI_RXFR1 0x80
90#define SPI_RXFR2 0x84
91#define SPI_RXFR3 0x88
92
93#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1)
94#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf)
95#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf)
96#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7)
97
98#define SPI_CS_INIT 0x01
99#define SPI_CS_ASSERT 0x02
100#define SPI_CS_DROP 0x04
101
102struct chip_data {
103 u32 mcr_val;
104 u32 ctar_val;
105 u16 void_write_data;
106};
107
108struct fsl_dspi {
109 struct spi_bitbang bitbang;
110 struct platform_device *pdev;
111
112 struct regmap *regmap;
113 int irq;
114 struct clk *clk;
115
116 struct spi_transfer *cur_transfer;
117 struct chip_data *cur_chip;
118 size_t len;
119 void *tx;
120 void *tx_end;
121 void *rx;
122 void *rx_end;
123 char dataflags;
124 u8 cs;
125 u16 void_write_data;
126
127 wait_queue_head_t waitq;
128 u32 waitflags;
129};
130
131static inline int is_double_byte_mode(struct fsl_dspi *dspi)
132{
133 unsigned int val;
134
135 regmap_read(dspi->regmap, SPI_CTAR(dspi->cs), &val);
136
137 return ((val & SPI_FRAME_BITS_MASK) == SPI_FRAME_BITS(8)) ? 0 : 1;
138}
139
140static void hz_to_spi_baud(char *pbr, char *br, int speed_hz,
141 unsigned long clkrate)
142{
143 /* Valid baud rate pre-scaler values */
144 int pbr_tbl[4] = {2, 3, 5, 7};
145 int brs[16] = { 2, 4, 6, 8,
146 16, 32, 64, 128,
147 256, 512, 1024, 2048,
148 4096, 8192, 16384, 32768 };
149 int temp, i = 0, j = 0;
150
151 temp = clkrate / 2 / speed_hz;
152
153 for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++)
154 for (j = 0; j < ARRAY_SIZE(brs); j++) {
155 if (pbr_tbl[i] * brs[j] >= temp) {
156 *pbr = i;
157 *br = j;
158 return;
159 }
160 }
161
162 pr_warn("Can not find valid baud rate,speed_hz is %d,clkrate is %ld\
163 ,we use the max prescaler value.\n", speed_hz, clkrate);
164 *pbr = ARRAY_SIZE(pbr_tbl) - 1;
165 *br = ARRAY_SIZE(brs) - 1;
166}
167
168static int dspi_transfer_write(struct fsl_dspi *dspi)
169{
170 int tx_count = 0;
171 int tx_word;
172 u16 d16;
173 u8 d8;
174 u32 dspi_pushr = 0;
175 int first = 1;
176
177 tx_word = is_double_byte_mode(dspi);
178
179 /* If we are in word mode, but only have a single byte to transfer
180 * then switch to byte mode temporarily. Will switch back at the
181 * end of the transfer.
182 */
183 if (tx_word && (dspi->len == 1)) {
184 dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM;
185 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
186 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(8));
187 tx_word = 0;
188 }
189
190 while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) {
191 if (tx_word) {
192 if (dspi->len == 1)
193 break;
194
195 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
196 d16 = *(u16 *)dspi->tx;
197 dspi->tx += 2;
198 } else {
199 d16 = dspi->void_write_data;
200 }
201
202 dspi_pushr = SPI_PUSHR_TXDATA(d16) |
203 SPI_PUSHR_PCS(dspi->cs) |
204 SPI_PUSHR_CTAS(dspi->cs) |
205 SPI_PUSHR_CONT;
206
207 dspi->len -= 2;
208 } else {
209 if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) {
210
211 d8 = *(u8 *)dspi->tx;
212 dspi->tx++;
213 } else {
214 d8 = (u8)dspi->void_write_data;
215 }
216
217 dspi_pushr = SPI_PUSHR_TXDATA(d8) |
218 SPI_PUSHR_PCS(dspi->cs) |
219 SPI_PUSHR_CTAS(dspi->cs) |
220 SPI_PUSHR_CONT;
221
222 dspi->len--;
223 }
224
225 if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) {
226 /* last transfer in the transfer */
227 dspi_pushr |= SPI_PUSHR_EOQ;
228 } else if (tx_word && (dspi->len == 1))
229 dspi_pushr |= SPI_PUSHR_EOQ;
230
231 if (first) {
232 first = 0;
233 dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */
234 }
235
236 regmap_write(dspi->regmap, SPI_PUSHR, dspi_pushr);
237
238 tx_count++;
239 }
240
241 return tx_count * (tx_word + 1);
242}
243
244static int dspi_transfer_read(struct fsl_dspi *dspi)
245{
246 int rx_count = 0;
247 int rx_word = is_double_byte_mode(dspi);
248 u16 d;
249 while ((dspi->rx < dspi->rx_end)
250 && (rx_count < DSPI_FIFO_SIZE)) {
251 if (rx_word) {
252 unsigned int val;
253
254 if ((dspi->rx_end - dspi->rx) == 1)
255 break;
256
257 regmap_read(dspi->regmap, SPI_POPR, &val);
258 d = SPI_POPR_RXDATA(val);
259
260 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
261 *(u16 *)dspi->rx = d;
262 dspi->rx += 2;
263
264 } else {
265 unsigned int val;
266
267 regmap_read(dspi->regmap, SPI_POPR, &val);
268 d = SPI_POPR_RXDATA(val);
269 if (!(dspi->dataflags & TRAN_STATE_RX_VOID))
270 *(u8 *)dspi->rx = d;
271 dspi->rx++;
272 }
273 rx_count++;
274 }
275
276 return rx_count;
277}
278
279static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t)
280{
281 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
282 dspi->cur_transfer = t;
283 dspi->cur_chip = spi_get_ctldata(spi);
284 dspi->cs = spi->chip_select;
285 dspi->void_write_data = dspi->cur_chip->void_write_data;
286
287 dspi->dataflags = 0;
288 dspi->tx = (void *)t->tx_buf;
289 dspi->tx_end = dspi->tx + t->len;
290 dspi->rx = t->rx_buf;
291 dspi->rx_end = dspi->rx + t->len;
292 dspi->len = t->len;
293
294 if (!dspi->rx)
295 dspi->dataflags |= TRAN_STATE_RX_VOID;
296
297 if (!dspi->tx)
298 dspi->dataflags |= TRAN_STATE_TX_VOID;
299
300 regmap_write(dspi->regmap, SPI_MCR, dspi->cur_chip->mcr_val);
301 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs), dspi->cur_chip->ctar_val);
302 regmap_write(dspi->regmap, SPI_RSER, SPI_RSER_EOQFE);
303
304 if (t->speed_hz)
305 regmap_write(dspi->regmap, SPI_CTAR(dspi->cs),
306 dspi->cur_chip->ctar_val);
307
308 dspi_transfer_write(dspi);
309
310 if (wait_event_interruptible(dspi->waitq, dspi->waitflags))
311 dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n");
312 dspi->waitflags = 0;
313
314 return t->len - dspi->len;
315}
316
317static void dspi_chipselect(struct spi_device *spi, int value)
318{
319 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
320 unsigned int pushr;
321
322 regmap_read(dspi->regmap, SPI_PUSHR, &pushr);
323
324 switch (value) {
325 case BITBANG_CS_ACTIVE:
326 pushr |= SPI_PUSHR_CONT;
327 break;
328 case BITBANG_CS_INACTIVE:
329 pushr &= ~SPI_PUSHR_CONT;
330 break;
331 }
332
333 regmap_write(dspi->regmap, SPI_PUSHR, pushr);
334}
335
336static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
337{
338 struct chip_data *chip;
339 struct fsl_dspi *dspi = spi_master_get_devdata(spi->master);
340 unsigned char br = 0, pbr = 0, fmsz = 0;
341
342 /* Only alloc on first setup */
343 chip = spi_get_ctldata(spi);
344 if (chip == NULL) {
345 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
346 GFP_KERNEL);
347 if (!chip)
348 return -ENOMEM;
349 }
350
351 chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS |
352 SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF;
353 if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) {
354 fmsz = spi->bits_per_word - 1;
355 } else {
356 pr_err("Invalid wordsize\n");
357 return -ENODEV;
358 }
359
360 chip->void_write_data = 0;
361
362 hz_to_spi_baud(&pbr, &br,
363 spi->max_speed_hz, clk_get_rate(dspi->clk));
364
365 chip->ctar_val = SPI_CTAR_FMSZ(fmsz)
366 | SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0)
367 | SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0)
368 | SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0)
369 | SPI_CTAR_PBR(pbr)
370 | SPI_CTAR_BR(br);
371
372 spi_set_ctldata(spi, chip);
373
374 return 0;
375}
376
377static int dspi_setup(struct spi_device *spi)
378{
379 if (!spi->max_speed_hz)
380 return -EINVAL;
381
382 return dspi_setup_transfer(spi, NULL);
383}
384
385static irqreturn_t dspi_interrupt(int irq, void *dev_id)
386{
387 struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id;
388
389 regmap_write(dspi->regmap, SPI_SR, SPI_SR_EOQF);
390
391 dspi_transfer_read(dspi);
392
393 if (!dspi->len) {
394 if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM)
395 regmap_update_bits(dspi->regmap, SPI_CTAR(dspi->cs),
396 SPI_FRAME_BITS_MASK, SPI_FRAME_BITS(16));
397
398 dspi->waitflags = 1;
399 wake_up_interruptible(&dspi->waitq);
400 } else {
401 dspi_transfer_write(dspi);
402
403 return IRQ_HANDLED;
404 }
405
406 return IRQ_HANDLED;
407}
408
409static struct of_device_id fsl_dspi_dt_ids[] = {
410 { .compatible = "fsl,vf610-dspi", .data = NULL, },
411 { /* sentinel */ }
412};
413MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids);
414
415#ifdef CONFIG_PM_SLEEP
416static int dspi_suspend(struct device *dev)
417{
418 struct spi_master *master = dev_get_drvdata(dev);
419 struct fsl_dspi *dspi = spi_master_get_devdata(master);
420
421 spi_master_suspend(master);
422 clk_disable_unprepare(dspi->clk);
423
424 return 0;
425}
426
427static int dspi_resume(struct device *dev)
428{
429 struct spi_master *master = dev_get_drvdata(dev);
430 struct fsl_dspi *dspi = spi_master_get_devdata(master);
431
432 clk_prepare_enable(dspi->clk);
433 spi_master_resume(master);
434
435 return 0;
436}
437#endif /* CONFIG_PM_SLEEP */
438
439static SIMPLE_DEV_PM_OPS(dspi_pm, dspi_suspend, dspi_resume);
440
441static struct regmap_config dspi_regmap_config = {
442 .reg_bits = 32,
443 .val_bits = 32,
444 .reg_stride = 4,
445 .max_register = 0x88,
446};
447
448static int dspi_probe(struct platform_device *pdev)
449{
450 struct device_node *np = pdev->dev.of_node;
451 struct spi_master *master;
452 struct fsl_dspi *dspi;
453 struct resource *res;
454 void __iomem *base;
455 int ret = 0, cs_num, bus_num;
456
457 master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi));
458 if (!master)
459 return -ENOMEM;
460
461 dspi = spi_master_get_devdata(master);
462 dspi->pdev = pdev;
463 dspi->bitbang.master = master;
464 dspi->bitbang.chipselect = dspi_chipselect;
465 dspi->bitbang.setup_transfer = dspi_setup_transfer;
466 dspi->bitbang.txrx_bufs = dspi_txrx_transfer;
467 dspi->bitbang.master->setup = dspi_setup;
468 dspi->bitbang.master->dev.of_node = pdev->dev.of_node;
469
470 master->mode_bits = SPI_CPOL | SPI_CPHA;
471 master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) |
472 SPI_BPW_MASK(16);
473
474 ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num);
475 if (ret < 0) {
476 dev_err(&pdev->dev, "can't get spi-num-chipselects\n");
477 goto out_master_put;
478 }
479 master->num_chipselect = cs_num;
480
481 ret = of_property_read_u32(np, "bus-num", &bus_num);
482 if (ret < 0) {
483 dev_err(&pdev->dev, "can't get bus-num\n");
484 goto out_master_put;
485 }
486 master->bus_num = bus_num;
487
488 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
489 base = devm_ioremap_resource(&pdev->dev, res);
490 if (IS_ERR(base)) {
491 ret = PTR_ERR(base);
492 goto out_master_put;
493 }
494
495 dspi_regmap_config.lock_arg = dspi;
496 dspi_regmap_config.val_format_endian =
497 of_property_read_bool(np, "big-endian")
498 ? REGMAP_ENDIAN_BIG : REGMAP_ENDIAN_DEFAULT;
499 dspi->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dspi", base,
500 &dspi_regmap_config);
501 if (IS_ERR(dspi->regmap)) {
502 dev_err(&pdev->dev, "failed to init regmap: %ld\n",
503 PTR_ERR(dspi->regmap));
504 return PTR_ERR(dspi->regmap);
505 }
506
507 dspi->irq = platform_get_irq(pdev, 0);
508 if (dspi->irq < 0) {
509 dev_err(&pdev->dev, "can't get platform irq\n");
510 ret = dspi->irq;
511 goto out_master_put;
512 }
513
514 ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0,
515 pdev->name, dspi);
516 if (ret < 0) {
517 dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n");
518 goto out_master_put;
519 }
520
521 dspi->clk = devm_clk_get(&pdev->dev, "dspi");
522 if (IS_ERR(dspi->clk)) {
523 ret = PTR_ERR(dspi->clk);
524 dev_err(&pdev->dev, "unable to get clock\n");
525 goto out_master_put;
526 }
527 clk_prepare_enable(dspi->clk);
528
529 init_waitqueue_head(&dspi->waitq);
530 platform_set_drvdata(pdev, master);
531
532 ret = spi_bitbang_start(&dspi->bitbang);
533 if (ret != 0) {
534 dev_err(&pdev->dev, "Problem registering DSPI master\n");
535 goto out_clk_put;
536 }
537
538 pr_info(KERN_INFO "Freescale DSPI master initialized\n");
539 return ret;
540
541out_clk_put:
542 clk_disable_unprepare(dspi->clk);
543out_master_put:
544 spi_master_put(master);
545
546 return ret;
547}
548
549static int dspi_remove(struct platform_device *pdev)
550{
551 struct spi_master *master = platform_get_drvdata(pdev);
552 struct fsl_dspi *dspi = spi_master_get_devdata(master);
553
554 /* Disconnect from the SPI framework */
555 spi_bitbang_stop(&dspi->bitbang);
556 clk_disable_unprepare(dspi->clk);
557 spi_master_put(dspi->bitbang.master);
558
559 return 0;
560}
561
562static struct platform_driver fsl_dspi_driver = {
563 .driver.name = DRIVER_NAME,
564 .driver.of_match_table = fsl_dspi_dt_ids,
565 .driver.owner = THIS_MODULE,
566 .driver.pm = &dspi_pm,
567 .probe = dspi_probe,
568 .remove = dspi_remove,
569};
570module_platform_driver(fsl_dspi_driver);
571
572MODULE_DESCRIPTION("Freescale DSPI Controller Driver");
573MODULE_LICENSE("GPL");
574MODULE_ALIAS("platform:" DRIVER_NAME);