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1/*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/highmem.h>
23#include <linux/delay.h>
24#include <linux/slab.h>
25#include <linux/spi/spi.h>
26
27#include "spi-dw.h"
28
29#ifdef CONFIG_DEBUG_FS
30#include <linux/debugfs.h>
31#endif
32
33#define START_STATE ((void *)0)
34#define RUNNING_STATE ((void *)1)
35#define DONE_STATE ((void *)2)
36#define ERROR_STATE ((void *)-1)
37
38#define QUEUE_RUNNING 0
39#define QUEUE_STOPPED 1
40
41#define MRST_SPI_DEASSERT 0
42#define MRST_SPI_ASSERT 1
43
44/* Slave spi_dev related */
45struct chip_data {
46 u16 cr0;
47 u8 cs; /* chip select pin */
48 u8 n_bytes; /* current is a 1/2/4 byte op */
49 u8 tmode; /* TR/TO/RO/EEPROM */
50 u8 type; /* SPI/SSP/MicroWire */
51
52 u8 poll_mode; /* 1 means use poll mode */
53
54 u32 dma_width;
55 u32 rx_threshold;
56 u32 tx_threshold;
57 u8 enable_dma;
58 u8 bits_per_word;
59 u16 clk_div; /* baud rate divider */
60 u32 speed_hz; /* baud rate */
61 void (*cs_control)(u32 command);
62};
63
64#ifdef CONFIG_DEBUG_FS
65static int spi_show_regs_open(struct inode *inode, struct file *file)
66{
67 file->private_data = inode->i_private;
68 return 0;
69}
70
71#define SPI_REGS_BUFSIZE 1024
72static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
73 size_t count, loff_t *ppos)
74{
75 struct dw_spi *dws;
76 char *buf;
77 u32 len = 0;
78 ssize_t ret;
79
80 dws = file->private_data;
81
82 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
83 if (!buf)
84 return 0;
85
86 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
87 "MRST SPI0 registers:\n");
88 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
89 "=================================\n");
90 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
91 "CTRL0: \t\t0x%08x\n", dw_readl(dws, ctrl0));
92 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
93 "CTRL1: \t\t0x%08x\n", dw_readl(dws, ctrl1));
94 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
95 "SSIENR: \t0x%08x\n", dw_readl(dws, ssienr));
96 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
97 "SER: \t\t0x%08x\n", dw_readl(dws, ser));
98 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
99 "BAUDR: \t\t0x%08x\n", dw_readl(dws, baudr));
100 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
101 "TXFTLR: \t0x%08x\n", dw_readl(dws, txfltr));
102 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
103 "RXFTLR: \t0x%08x\n", dw_readl(dws, rxfltr));
104 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
105 "TXFLR: \t\t0x%08x\n", dw_readl(dws, txflr));
106 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
107 "RXFLR: \t\t0x%08x\n", dw_readl(dws, rxflr));
108 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
109 "SR: \t\t0x%08x\n", dw_readl(dws, sr));
110 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
111 "IMR: \t\t0x%08x\n", dw_readl(dws, imr));
112 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
113 "ISR: \t\t0x%08x\n", dw_readl(dws, isr));
114 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
115 "DMACR: \t\t0x%08x\n", dw_readl(dws, dmacr));
116 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
117 "DMATDLR: \t0x%08x\n", dw_readl(dws, dmatdlr));
118 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
119 "DMARDLR: \t0x%08x\n", dw_readl(dws, dmardlr));
120 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
121 "=================================\n");
122
123 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
124 kfree(buf);
125 return ret;
126}
127
128static const struct file_operations mrst_spi_regs_ops = {
129 .owner = THIS_MODULE,
130 .open = spi_show_regs_open,
131 .read = spi_show_regs,
132 .llseek = default_llseek,
133};
134
135static int mrst_spi_debugfs_init(struct dw_spi *dws)
136{
137 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
138 if (!dws->debugfs)
139 return -ENOMEM;
140
141 debugfs_create_file("registers", S_IFREG | S_IRUGO,
142 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
143 return 0;
144}
145
146static void mrst_spi_debugfs_remove(struct dw_spi *dws)
147{
148 if (dws->debugfs)
149 debugfs_remove_recursive(dws->debugfs);
150}
151
152#else
153static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
154{
155 return 0;
156}
157
158static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
159{
160}
161#endif /* CONFIG_DEBUG_FS */
162
163/* Return the max entries we can fill into tx fifo */
164static inline u32 tx_max(struct dw_spi *dws)
165{
166 u32 tx_left, tx_room, rxtx_gap;
167
168 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
169 tx_room = dws->fifo_len - dw_readw(dws, txflr);
170
171 /*
172 * Another concern is about the tx/rx mismatch, we
173 * though to use (dws->fifo_len - rxflr - txflr) as
174 * one maximum value for tx, but it doesn't cover the
175 * data which is out of tx/rx fifo and inside the
176 * shift registers. So a control from sw point of
177 * view is taken.
178 */
179 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
180 / dws->n_bytes;
181
182 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
183}
184
185/* Return the max entries we should read out of rx fifo */
186static inline u32 rx_max(struct dw_spi *dws)
187{
188 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
189
190 return min(rx_left, (u32)dw_readw(dws, rxflr));
191}
192
193static void dw_writer(struct dw_spi *dws)
194{
195 u32 max = tx_max(dws);
196 u16 txw = 0;
197
198 while (max--) {
199 /* Set the tx word if the transfer's original "tx" is not null */
200 if (dws->tx_end - dws->len) {
201 if (dws->n_bytes == 1)
202 txw = *(u8 *)(dws->tx);
203 else
204 txw = *(u16 *)(dws->tx);
205 }
206 dw_writew(dws, dr, txw);
207 dws->tx += dws->n_bytes;
208 }
209}
210
211static void dw_reader(struct dw_spi *dws)
212{
213 u32 max = rx_max(dws);
214 u16 rxw;
215
216 while (max--) {
217 rxw = dw_readw(dws, dr);
218 /* Care rx only if the transfer's original "rx" is not null */
219 if (dws->rx_end - dws->len) {
220 if (dws->n_bytes == 1)
221 *(u8 *)(dws->rx) = rxw;
222 else
223 *(u16 *)(dws->rx) = rxw;
224 }
225 dws->rx += dws->n_bytes;
226 }
227}
228
229static void *next_transfer(struct dw_spi *dws)
230{
231 struct spi_message *msg = dws->cur_msg;
232 struct spi_transfer *trans = dws->cur_transfer;
233
234 /* Move to next transfer */
235 if (trans->transfer_list.next != &msg->transfers) {
236 dws->cur_transfer =
237 list_entry(trans->transfer_list.next,
238 struct spi_transfer,
239 transfer_list);
240 return RUNNING_STATE;
241 } else
242 return DONE_STATE;
243}
244
245/*
246 * Note: first step is the protocol driver prepares
247 * a dma-capable memory, and this func just need translate
248 * the virt addr to physical
249 */
250static int map_dma_buffers(struct dw_spi *dws)
251{
252 if (!dws->cur_msg->is_dma_mapped
253 || !dws->dma_inited
254 || !dws->cur_chip->enable_dma
255 || !dws->dma_ops)
256 return 0;
257
258 if (dws->cur_transfer->tx_dma)
259 dws->tx_dma = dws->cur_transfer->tx_dma;
260
261 if (dws->cur_transfer->rx_dma)
262 dws->rx_dma = dws->cur_transfer->rx_dma;
263
264 return 1;
265}
266
267/* Caller already set message->status; dma and pio irqs are blocked */
268static void giveback(struct dw_spi *dws)
269{
270 struct spi_transfer *last_transfer;
271 unsigned long flags;
272 struct spi_message *msg;
273
274 spin_lock_irqsave(&dws->lock, flags);
275 msg = dws->cur_msg;
276 dws->cur_msg = NULL;
277 dws->cur_transfer = NULL;
278 dws->prev_chip = dws->cur_chip;
279 dws->cur_chip = NULL;
280 dws->dma_mapped = 0;
281 queue_work(dws->workqueue, &dws->pump_messages);
282 spin_unlock_irqrestore(&dws->lock, flags);
283
284 last_transfer = list_entry(msg->transfers.prev,
285 struct spi_transfer,
286 transfer_list);
287
288 if (!last_transfer->cs_change && dws->cs_control)
289 dws->cs_control(MRST_SPI_DEASSERT);
290
291 msg->state = NULL;
292 if (msg->complete)
293 msg->complete(msg->context);
294}
295
296static void int_error_stop(struct dw_spi *dws, const char *msg)
297{
298 /* Stop the hw */
299 spi_enable_chip(dws, 0);
300
301 dev_err(&dws->master->dev, "%s\n", msg);
302 dws->cur_msg->state = ERROR_STATE;
303 tasklet_schedule(&dws->pump_transfers);
304}
305
306void dw_spi_xfer_done(struct dw_spi *dws)
307{
308 /* Update total byte transferred return count actual bytes read */
309 dws->cur_msg->actual_length += dws->len;
310
311 /* Move to next transfer */
312 dws->cur_msg->state = next_transfer(dws);
313
314 /* Handle end of message */
315 if (dws->cur_msg->state == DONE_STATE) {
316 dws->cur_msg->status = 0;
317 giveback(dws);
318 } else
319 tasklet_schedule(&dws->pump_transfers);
320}
321EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
322
323static irqreturn_t interrupt_transfer(struct dw_spi *dws)
324{
325 u16 irq_status = dw_readw(dws, isr);
326
327 /* Error handling */
328 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
329 dw_readw(dws, txoicr);
330 dw_readw(dws, rxoicr);
331 dw_readw(dws, rxuicr);
332 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
333 return IRQ_HANDLED;
334 }
335
336 dw_reader(dws);
337 if (dws->rx_end == dws->rx) {
338 spi_mask_intr(dws, SPI_INT_TXEI);
339 dw_spi_xfer_done(dws);
340 return IRQ_HANDLED;
341 }
342 if (irq_status & SPI_INT_TXEI) {
343 spi_mask_intr(dws, SPI_INT_TXEI);
344 dw_writer(dws);
345 /* Enable TX irq always, it will be disabled when RX finished */
346 spi_umask_intr(dws, SPI_INT_TXEI);
347 }
348
349 return IRQ_HANDLED;
350}
351
352static irqreturn_t dw_spi_irq(int irq, void *dev_id)
353{
354 struct dw_spi *dws = dev_id;
355 u16 irq_status = dw_readw(dws, isr) & 0x3f;
356
357 if (!irq_status)
358 return IRQ_NONE;
359
360 if (!dws->cur_msg) {
361 spi_mask_intr(dws, SPI_INT_TXEI);
362 return IRQ_HANDLED;
363 }
364
365 return dws->transfer_handler(dws);
366}
367
368/* Must be called inside pump_transfers() */
369static void poll_transfer(struct dw_spi *dws)
370{
371 do {
372 dw_writer(dws);
373 dw_reader(dws);
374 cpu_relax();
375 } while (dws->rx_end > dws->rx);
376
377 dw_spi_xfer_done(dws);
378}
379
380static void pump_transfers(unsigned long data)
381{
382 struct dw_spi *dws = (struct dw_spi *)data;
383 struct spi_message *message = NULL;
384 struct spi_transfer *transfer = NULL;
385 struct spi_transfer *previous = NULL;
386 struct spi_device *spi = NULL;
387 struct chip_data *chip = NULL;
388 u8 bits = 0;
389 u8 imask = 0;
390 u8 cs_change = 0;
391 u16 txint_level = 0;
392 u16 clk_div = 0;
393 u32 speed = 0;
394 u32 cr0 = 0;
395
396 /* Get current state information */
397 message = dws->cur_msg;
398 transfer = dws->cur_transfer;
399 chip = dws->cur_chip;
400 spi = message->spi;
401
402 if (unlikely(!chip->clk_div))
403 chip->clk_div = dws->max_freq / chip->speed_hz;
404
405 if (message->state == ERROR_STATE) {
406 message->status = -EIO;
407 goto early_exit;
408 }
409
410 /* Handle end of message */
411 if (message->state == DONE_STATE) {
412 message->status = 0;
413 goto early_exit;
414 }
415
416 /* Delay if requested at end of transfer*/
417 if (message->state == RUNNING_STATE) {
418 previous = list_entry(transfer->transfer_list.prev,
419 struct spi_transfer,
420 transfer_list);
421 if (previous->delay_usecs)
422 udelay(previous->delay_usecs);
423 }
424
425 dws->n_bytes = chip->n_bytes;
426 dws->dma_width = chip->dma_width;
427 dws->cs_control = chip->cs_control;
428
429 dws->rx_dma = transfer->rx_dma;
430 dws->tx_dma = transfer->tx_dma;
431 dws->tx = (void *)transfer->tx_buf;
432 dws->tx_end = dws->tx + transfer->len;
433 dws->rx = transfer->rx_buf;
434 dws->rx_end = dws->rx + transfer->len;
435 dws->cs_change = transfer->cs_change;
436 dws->len = dws->cur_transfer->len;
437 if (chip != dws->prev_chip)
438 cs_change = 1;
439
440 cr0 = chip->cr0;
441
442 /* Handle per transfer options for bpw and speed */
443 if (transfer->speed_hz) {
444 speed = chip->speed_hz;
445
446 if (transfer->speed_hz != speed) {
447 speed = transfer->speed_hz;
448 if (speed > dws->max_freq) {
449 printk(KERN_ERR "MRST SPI0: unsupported"
450 "freq: %dHz\n", speed);
451 message->status = -EIO;
452 goto early_exit;
453 }
454
455 /* clk_div doesn't support odd number */
456 clk_div = dws->max_freq / speed;
457 clk_div = (clk_div + 1) & 0xfffe;
458
459 chip->speed_hz = speed;
460 chip->clk_div = clk_div;
461 }
462 }
463 if (transfer->bits_per_word) {
464 bits = transfer->bits_per_word;
465
466 switch (bits) {
467 case 8:
468 case 16:
469 dws->n_bytes = dws->dma_width = bits >> 3;
470 break;
471 default:
472 printk(KERN_ERR "MRST SPI0: unsupported bits:"
473 "%db\n", bits);
474 message->status = -EIO;
475 goto early_exit;
476 }
477
478 cr0 = (bits - 1)
479 | (chip->type << SPI_FRF_OFFSET)
480 | (spi->mode << SPI_MODE_OFFSET)
481 | (chip->tmode << SPI_TMOD_OFFSET);
482 }
483 message->state = RUNNING_STATE;
484
485 /*
486 * Adjust transfer mode if necessary. Requires platform dependent
487 * chipselect mechanism.
488 */
489 if (dws->cs_control) {
490 if (dws->rx && dws->tx)
491 chip->tmode = SPI_TMOD_TR;
492 else if (dws->rx)
493 chip->tmode = SPI_TMOD_RO;
494 else
495 chip->tmode = SPI_TMOD_TO;
496
497 cr0 &= ~SPI_TMOD_MASK;
498 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
499 }
500
501 /* Check if current transfer is a DMA transaction */
502 dws->dma_mapped = map_dma_buffers(dws);
503
504 /*
505 * Interrupt mode
506 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
507 */
508 if (!dws->dma_mapped && !chip->poll_mode) {
509 int templen = dws->len / dws->n_bytes;
510 txint_level = dws->fifo_len / 2;
511 txint_level = (templen > txint_level) ? txint_level : templen;
512
513 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
514 dws->transfer_handler = interrupt_transfer;
515 }
516
517 /*
518 * Reprogram registers only if
519 * 1. chip select changes
520 * 2. clk_div is changed
521 * 3. control value changes
522 */
523 if (dw_readw(dws, ctrl0) != cr0 || cs_change || clk_div || imask) {
524 spi_enable_chip(dws, 0);
525
526 if (dw_readw(dws, ctrl0) != cr0)
527 dw_writew(dws, ctrl0, cr0);
528
529 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
530 spi_chip_sel(dws, spi->chip_select);
531
532 /* Set the interrupt mask, for poll mode just disable all int */
533 spi_mask_intr(dws, 0xff);
534 if (imask)
535 spi_umask_intr(dws, imask);
536 if (txint_level)
537 dw_writew(dws, txfltr, txint_level);
538
539 spi_enable_chip(dws, 1);
540 if (cs_change)
541 dws->prev_chip = chip;
542 }
543
544 if (dws->dma_mapped)
545 dws->dma_ops->dma_transfer(dws, cs_change);
546
547 if (chip->poll_mode)
548 poll_transfer(dws);
549
550 return;
551
552early_exit:
553 giveback(dws);
554 return;
555}
556
557static void pump_messages(struct work_struct *work)
558{
559 struct dw_spi *dws =
560 container_of(work, struct dw_spi, pump_messages);
561 unsigned long flags;
562
563 /* Lock queue and check for queue work */
564 spin_lock_irqsave(&dws->lock, flags);
565 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
566 dws->busy = 0;
567 spin_unlock_irqrestore(&dws->lock, flags);
568 return;
569 }
570
571 /* Make sure we are not already running a message */
572 if (dws->cur_msg) {
573 spin_unlock_irqrestore(&dws->lock, flags);
574 return;
575 }
576
577 /* Extract head of queue */
578 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
579 list_del_init(&dws->cur_msg->queue);
580
581 /* Initial message state*/
582 dws->cur_msg->state = START_STATE;
583 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
584 struct spi_transfer,
585 transfer_list);
586 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
587
588 /* Mark as busy and launch transfers */
589 tasklet_schedule(&dws->pump_transfers);
590
591 dws->busy = 1;
592 spin_unlock_irqrestore(&dws->lock, flags);
593}
594
595/* spi_device use this to queue in their spi_msg */
596static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
597{
598 struct dw_spi *dws = spi_master_get_devdata(spi->master);
599 unsigned long flags;
600
601 spin_lock_irqsave(&dws->lock, flags);
602
603 if (dws->run == QUEUE_STOPPED) {
604 spin_unlock_irqrestore(&dws->lock, flags);
605 return -ESHUTDOWN;
606 }
607
608 msg->actual_length = 0;
609 msg->status = -EINPROGRESS;
610 msg->state = START_STATE;
611
612 list_add_tail(&msg->queue, &dws->queue);
613
614 if (dws->run == QUEUE_RUNNING && !dws->busy) {
615
616 if (dws->cur_transfer || dws->cur_msg)
617 queue_work(dws->workqueue,
618 &dws->pump_messages);
619 else {
620 /* If no other data transaction in air, just go */
621 spin_unlock_irqrestore(&dws->lock, flags);
622 pump_messages(&dws->pump_messages);
623 return 0;
624 }
625 }
626
627 spin_unlock_irqrestore(&dws->lock, flags);
628 return 0;
629}
630
631/* This may be called twice for each spi dev */
632static int dw_spi_setup(struct spi_device *spi)
633{
634 struct dw_spi_chip *chip_info = NULL;
635 struct chip_data *chip;
636
637 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
638 return -EINVAL;
639
640 /* Only alloc on first setup */
641 chip = spi_get_ctldata(spi);
642 if (!chip) {
643 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
644 if (!chip)
645 return -ENOMEM;
646 }
647
648 /*
649 * Protocol drivers may change the chip settings, so...
650 * if chip_info exists, use it
651 */
652 chip_info = spi->controller_data;
653
654 /* chip_info doesn't always exist */
655 if (chip_info) {
656 if (chip_info->cs_control)
657 chip->cs_control = chip_info->cs_control;
658
659 chip->poll_mode = chip_info->poll_mode;
660 chip->type = chip_info->type;
661
662 chip->rx_threshold = 0;
663 chip->tx_threshold = 0;
664
665 chip->enable_dma = chip_info->enable_dma;
666 }
667
668 if (spi->bits_per_word <= 8) {
669 chip->n_bytes = 1;
670 chip->dma_width = 1;
671 } else if (spi->bits_per_word <= 16) {
672 chip->n_bytes = 2;
673 chip->dma_width = 2;
674 } else {
675 /* Never take >16b case for MRST SPIC */
676 dev_err(&spi->dev, "invalid wordsize\n");
677 return -EINVAL;
678 }
679 chip->bits_per_word = spi->bits_per_word;
680
681 if (!spi->max_speed_hz) {
682 dev_err(&spi->dev, "No max speed HZ parameter\n");
683 return -EINVAL;
684 }
685 chip->speed_hz = spi->max_speed_hz;
686
687 chip->tmode = 0; /* Tx & Rx */
688 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
689 chip->cr0 = (chip->bits_per_word - 1)
690 | (chip->type << SPI_FRF_OFFSET)
691 | (spi->mode << SPI_MODE_OFFSET)
692 | (chip->tmode << SPI_TMOD_OFFSET);
693
694 spi_set_ctldata(spi, chip);
695 return 0;
696}
697
698static void dw_spi_cleanup(struct spi_device *spi)
699{
700 struct chip_data *chip = spi_get_ctldata(spi);
701 kfree(chip);
702}
703
704static int __devinit init_queue(struct dw_spi *dws)
705{
706 INIT_LIST_HEAD(&dws->queue);
707 spin_lock_init(&dws->lock);
708
709 dws->run = QUEUE_STOPPED;
710 dws->busy = 0;
711
712 tasklet_init(&dws->pump_transfers,
713 pump_transfers, (unsigned long)dws);
714
715 INIT_WORK(&dws->pump_messages, pump_messages);
716 dws->workqueue = create_singlethread_workqueue(
717 dev_name(dws->master->dev.parent));
718 if (dws->workqueue == NULL)
719 return -EBUSY;
720
721 return 0;
722}
723
724static int start_queue(struct dw_spi *dws)
725{
726 unsigned long flags;
727
728 spin_lock_irqsave(&dws->lock, flags);
729
730 if (dws->run == QUEUE_RUNNING || dws->busy) {
731 spin_unlock_irqrestore(&dws->lock, flags);
732 return -EBUSY;
733 }
734
735 dws->run = QUEUE_RUNNING;
736 dws->cur_msg = NULL;
737 dws->cur_transfer = NULL;
738 dws->cur_chip = NULL;
739 dws->prev_chip = NULL;
740 spin_unlock_irqrestore(&dws->lock, flags);
741
742 queue_work(dws->workqueue, &dws->pump_messages);
743
744 return 0;
745}
746
747static int stop_queue(struct dw_spi *dws)
748{
749 unsigned long flags;
750 unsigned limit = 50;
751 int status = 0;
752
753 spin_lock_irqsave(&dws->lock, flags);
754 dws->run = QUEUE_STOPPED;
755 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
756 spin_unlock_irqrestore(&dws->lock, flags);
757 msleep(10);
758 spin_lock_irqsave(&dws->lock, flags);
759 }
760
761 if (!list_empty(&dws->queue) || dws->busy)
762 status = -EBUSY;
763 spin_unlock_irqrestore(&dws->lock, flags);
764
765 return status;
766}
767
768static int destroy_queue(struct dw_spi *dws)
769{
770 int status;
771
772 status = stop_queue(dws);
773 if (status != 0)
774 return status;
775 destroy_workqueue(dws->workqueue);
776 return 0;
777}
778
779/* Restart the controller, disable all interrupts, clean rx fifo */
780static void spi_hw_init(struct dw_spi *dws)
781{
782 spi_enable_chip(dws, 0);
783 spi_mask_intr(dws, 0xff);
784 spi_enable_chip(dws, 1);
785
786 /*
787 * Try to detect the FIFO depth if not set by interface driver,
788 * the depth could be from 2 to 256 from HW spec
789 */
790 if (!dws->fifo_len) {
791 u32 fifo;
792 for (fifo = 2; fifo <= 257; fifo++) {
793 dw_writew(dws, txfltr, fifo);
794 if (fifo != dw_readw(dws, txfltr))
795 break;
796 }
797
798 dws->fifo_len = (fifo == 257) ? 0 : fifo;
799 dw_writew(dws, txfltr, 0);
800 }
801}
802
803int __devinit dw_spi_add_host(struct dw_spi *dws)
804{
805 struct spi_master *master;
806 int ret;
807
808 BUG_ON(dws == NULL);
809
810 master = spi_alloc_master(dws->parent_dev, 0);
811 if (!master) {
812 ret = -ENOMEM;
813 goto exit;
814 }
815
816 dws->master = master;
817 dws->type = SSI_MOTO_SPI;
818 dws->prev_chip = NULL;
819 dws->dma_inited = 0;
820 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
821 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
822 dws->bus_num);
823
824 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED,
825 dws->name, dws);
826 if (ret < 0) {
827 dev_err(&master->dev, "can not get IRQ\n");
828 goto err_free_master;
829 }
830
831 master->mode_bits = SPI_CPOL | SPI_CPHA;
832 master->bus_num = dws->bus_num;
833 master->num_chipselect = dws->num_cs;
834 master->cleanup = dw_spi_cleanup;
835 master->setup = dw_spi_setup;
836 master->transfer = dw_spi_transfer;
837
838 /* Basic HW init */
839 spi_hw_init(dws);
840
841 if (dws->dma_ops && dws->dma_ops->dma_init) {
842 ret = dws->dma_ops->dma_init(dws);
843 if (ret) {
844 dev_warn(&master->dev, "DMA init failed\n");
845 dws->dma_inited = 0;
846 }
847 }
848
849 /* Initial and start queue */
850 ret = init_queue(dws);
851 if (ret) {
852 dev_err(&master->dev, "problem initializing queue\n");
853 goto err_diable_hw;
854 }
855 ret = start_queue(dws);
856 if (ret) {
857 dev_err(&master->dev, "problem starting queue\n");
858 goto err_diable_hw;
859 }
860
861 spi_master_set_devdata(master, dws);
862 ret = spi_register_master(master);
863 if (ret) {
864 dev_err(&master->dev, "problem registering spi master\n");
865 goto err_queue_alloc;
866 }
867
868 mrst_spi_debugfs_init(dws);
869 return 0;
870
871err_queue_alloc:
872 destroy_queue(dws);
873 if (dws->dma_ops && dws->dma_ops->dma_exit)
874 dws->dma_ops->dma_exit(dws);
875err_diable_hw:
876 spi_enable_chip(dws, 0);
877 free_irq(dws->irq, dws);
878err_free_master:
879 spi_master_put(master);
880exit:
881 return ret;
882}
883EXPORT_SYMBOL_GPL(dw_spi_add_host);
884
885void __devexit dw_spi_remove_host(struct dw_spi *dws)
886{
887 int status = 0;
888
889 if (!dws)
890 return;
891 mrst_spi_debugfs_remove(dws);
892
893 /* Remove the queue */
894 status = destroy_queue(dws);
895 if (status != 0)
896 dev_err(&dws->master->dev, "dw_spi_remove: workqueue will not "
897 "complete, message memory not freed\n");
898
899 if (dws->dma_ops && dws->dma_ops->dma_exit)
900 dws->dma_ops->dma_exit(dws);
901 spi_enable_chip(dws, 0);
902 /* Disable clk */
903 spi_set_clk(dws, 0);
904 free_irq(dws->irq, dws);
905
906 /* Disconnect from the SPI framework */
907 spi_unregister_master(dws->master);
908}
909EXPORT_SYMBOL_GPL(dw_spi_remove_host);
910
911int dw_spi_suspend_host(struct dw_spi *dws)
912{
913 int ret = 0;
914
915 ret = stop_queue(dws);
916 if (ret)
917 return ret;
918 spi_enable_chip(dws, 0);
919 spi_set_clk(dws, 0);
920 return ret;
921}
922EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
923
924int dw_spi_resume_host(struct dw_spi *dws)
925{
926 int ret;
927
928 spi_hw_init(dws);
929 ret = start_queue(dws);
930 if (ret)
931 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
932 return ret;
933}
934EXPORT_SYMBOL_GPL(dw_spi_resume_host);
935
936MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
937MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
938MODULE_LICENSE("GPL v2");
1/*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program; if not, write to the Free Software Foundation, Inc.,
17 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18 */
19
20#include <linux/dma-mapping.h>
21#include <linux/interrupt.h>
22#include <linux/module.h>
23#include <linux/highmem.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/spi/spi.h>
27
28#include "spi-dw.h"
29
30#ifdef CONFIG_DEBUG_FS
31#include <linux/debugfs.h>
32#endif
33
34#define START_STATE ((void *)0)
35#define RUNNING_STATE ((void *)1)
36#define DONE_STATE ((void *)2)
37#define ERROR_STATE ((void *)-1)
38
39#define QUEUE_RUNNING 0
40#define QUEUE_STOPPED 1
41
42#define MRST_SPI_DEASSERT 0
43#define MRST_SPI_ASSERT 1
44
45/* Slave spi_dev related */
46struct chip_data {
47 u16 cr0;
48 u8 cs; /* chip select pin */
49 u8 n_bytes; /* current is a 1/2/4 byte op */
50 u8 tmode; /* TR/TO/RO/EEPROM */
51 u8 type; /* SPI/SSP/MicroWire */
52
53 u8 poll_mode; /* 1 means use poll mode */
54
55 u32 dma_width;
56 u32 rx_threshold;
57 u32 tx_threshold;
58 u8 enable_dma;
59 u8 bits_per_word;
60 u16 clk_div; /* baud rate divider */
61 u32 speed_hz; /* baud rate */
62 void (*cs_control)(u32 command);
63};
64
65#ifdef CONFIG_DEBUG_FS
66#define SPI_REGS_BUFSIZE 1024
67static ssize_t spi_show_regs(struct file *file, char __user *user_buf,
68 size_t count, loff_t *ppos)
69{
70 struct dw_spi *dws;
71 char *buf;
72 u32 len = 0;
73 ssize_t ret;
74
75 dws = file->private_data;
76
77 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
78 if (!buf)
79 return 0;
80
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "MRST SPI0 registers:\n");
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "=================================\n");
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
93 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
94 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
95 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
96 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
97 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
98 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
99 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
100 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
101 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
102 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
103 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
104 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
105 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
106 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
107 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
108 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
109 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
110 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
111 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
112 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
113 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
114 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
115 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
116 "=================================\n");
117
118 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
119 kfree(buf);
120 return ret;
121}
122
123static const struct file_operations mrst_spi_regs_ops = {
124 .owner = THIS_MODULE,
125 .open = simple_open,
126 .read = spi_show_regs,
127 .llseek = default_llseek,
128};
129
130static int mrst_spi_debugfs_init(struct dw_spi *dws)
131{
132 dws->debugfs = debugfs_create_dir("mrst_spi", NULL);
133 if (!dws->debugfs)
134 return -ENOMEM;
135
136 debugfs_create_file("registers", S_IFREG | S_IRUGO,
137 dws->debugfs, (void *)dws, &mrst_spi_regs_ops);
138 return 0;
139}
140
141static void mrst_spi_debugfs_remove(struct dw_spi *dws)
142{
143 if (dws->debugfs)
144 debugfs_remove_recursive(dws->debugfs);
145}
146
147#else
148static inline int mrst_spi_debugfs_init(struct dw_spi *dws)
149{
150 return 0;
151}
152
153static inline void mrst_spi_debugfs_remove(struct dw_spi *dws)
154{
155}
156#endif /* CONFIG_DEBUG_FS */
157
158/* Return the max entries we can fill into tx fifo */
159static inline u32 tx_max(struct dw_spi *dws)
160{
161 u32 tx_left, tx_room, rxtx_gap;
162
163 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
164 tx_room = dws->fifo_len - dw_readw(dws, DW_SPI_TXFLR);
165
166 /*
167 * Another concern is about the tx/rx mismatch, we
168 * though to use (dws->fifo_len - rxflr - txflr) as
169 * one maximum value for tx, but it doesn't cover the
170 * data which is out of tx/rx fifo and inside the
171 * shift registers. So a control from sw point of
172 * view is taken.
173 */
174 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
175 / dws->n_bytes;
176
177 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
178}
179
180/* Return the max entries we should read out of rx fifo */
181static inline u32 rx_max(struct dw_spi *dws)
182{
183 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
184
185 return min(rx_left, (u32)dw_readw(dws, DW_SPI_RXFLR));
186}
187
188static void dw_writer(struct dw_spi *dws)
189{
190 u32 max = tx_max(dws);
191 u16 txw = 0;
192
193 while (max--) {
194 /* Set the tx word if the transfer's original "tx" is not null */
195 if (dws->tx_end - dws->len) {
196 if (dws->n_bytes == 1)
197 txw = *(u8 *)(dws->tx);
198 else
199 txw = *(u16 *)(dws->tx);
200 }
201 dw_writew(dws, DW_SPI_DR, txw);
202 dws->tx += dws->n_bytes;
203 }
204}
205
206static void dw_reader(struct dw_spi *dws)
207{
208 u32 max = rx_max(dws);
209 u16 rxw;
210
211 while (max--) {
212 rxw = dw_readw(dws, DW_SPI_DR);
213 /* Care rx only if the transfer's original "rx" is not null */
214 if (dws->rx_end - dws->len) {
215 if (dws->n_bytes == 1)
216 *(u8 *)(dws->rx) = rxw;
217 else
218 *(u16 *)(dws->rx) = rxw;
219 }
220 dws->rx += dws->n_bytes;
221 }
222}
223
224static void *next_transfer(struct dw_spi *dws)
225{
226 struct spi_message *msg = dws->cur_msg;
227 struct spi_transfer *trans = dws->cur_transfer;
228
229 /* Move to next transfer */
230 if (trans->transfer_list.next != &msg->transfers) {
231 dws->cur_transfer =
232 list_entry(trans->transfer_list.next,
233 struct spi_transfer,
234 transfer_list);
235 return RUNNING_STATE;
236 } else
237 return DONE_STATE;
238}
239
240/*
241 * Note: first step is the protocol driver prepares
242 * a dma-capable memory, and this func just need translate
243 * the virt addr to physical
244 */
245static int map_dma_buffers(struct dw_spi *dws)
246{
247 if (!dws->cur_msg->is_dma_mapped
248 || !dws->dma_inited
249 || !dws->cur_chip->enable_dma
250 || !dws->dma_ops)
251 return 0;
252
253 if (dws->cur_transfer->tx_dma)
254 dws->tx_dma = dws->cur_transfer->tx_dma;
255
256 if (dws->cur_transfer->rx_dma)
257 dws->rx_dma = dws->cur_transfer->rx_dma;
258
259 return 1;
260}
261
262/* Caller already set message->status; dma and pio irqs are blocked */
263static void giveback(struct dw_spi *dws)
264{
265 struct spi_transfer *last_transfer;
266 unsigned long flags;
267 struct spi_message *msg;
268
269 spin_lock_irqsave(&dws->lock, flags);
270 msg = dws->cur_msg;
271 dws->cur_msg = NULL;
272 dws->cur_transfer = NULL;
273 dws->prev_chip = dws->cur_chip;
274 dws->cur_chip = NULL;
275 dws->dma_mapped = 0;
276 queue_work(dws->workqueue, &dws->pump_messages);
277 spin_unlock_irqrestore(&dws->lock, flags);
278
279 last_transfer = list_last_entry(&msg->transfers, struct spi_transfer,
280 transfer_list);
281
282 if (!last_transfer->cs_change && dws->cs_control)
283 dws->cs_control(MRST_SPI_DEASSERT);
284
285 msg->state = NULL;
286 if (msg->complete)
287 msg->complete(msg->context);
288}
289
290static void int_error_stop(struct dw_spi *dws, const char *msg)
291{
292 /* Stop the hw */
293 spi_enable_chip(dws, 0);
294
295 dev_err(&dws->master->dev, "%s\n", msg);
296 dws->cur_msg->state = ERROR_STATE;
297 tasklet_schedule(&dws->pump_transfers);
298}
299
300void dw_spi_xfer_done(struct dw_spi *dws)
301{
302 /* Update total byte transferred return count actual bytes read */
303 dws->cur_msg->actual_length += dws->len;
304
305 /* Move to next transfer */
306 dws->cur_msg->state = next_transfer(dws);
307
308 /* Handle end of message */
309 if (dws->cur_msg->state == DONE_STATE) {
310 dws->cur_msg->status = 0;
311 giveback(dws);
312 } else
313 tasklet_schedule(&dws->pump_transfers);
314}
315EXPORT_SYMBOL_GPL(dw_spi_xfer_done);
316
317static irqreturn_t interrupt_transfer(struct dw_spi *dws)
318{
319 u16 irq_status = dw_readw(dws, DW_SPI_ISR);
320
321 /* Error handling */
322 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
323 dw_readw(dws, DW_SPI_TXOICR);
324 dw_readw(dws, DW_SPI_RXOICR);
325 dw_readw(dws, DW_SPI_RXUICR);
326 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
327 return IRQ_HANDLED;
328 }
329
330 dw_reader(dws);
331 if (dws->rx_end == dws->rx) {
332 spi_mask_intr(dws, SPI_INT_TXEI);
333 dw_spi_xfer_done(dws);
334 return IRQ_HANDLED;
335 }
336 if (irq_status & SPI_INT_TXEI) {
337 spi_mask_intr(dws, SPI_INT_TXEI);
338 dw_writer(dws);
339 /* Enable TX irq always, it will be disabled when RX finished */
340 spi_umask_intr(dws, SPI_INT_TXEI);
341 }
342
343 return IRQ_HANDLED;
344}
345
346static irqreturn_t dw_spi_irq(int irq, void *dev_id)
347{
348 struct dw_spi *dws = dev_id;
349 u16 irq_status = dw_readw(dws, DW_SPI_ISR) & 0x3f;
350
351 if (!irq_status)
352 return IRQ_NONE;
353
354 if (!dws->cur_msg) {
355 spi_mask_intr(dws, SPI_INT_TXEI);
356 return IRQ_HANDLED;
357 }
358
359 return dws->transfer_handler(dws);
360}
361
362/* Must be called inside pump_transfers() */
363static void poll_transfer(struct dw_spi *dws)
364{
365 do {
366 dw_writer(dws);
367 dw_reader(dws);
368 cpu_relax();
369 } while (dws->rx_end > dws->rx);
370
371 dw_spi_xfer_done(dws);
372}
373
374static void pump_transfers(unsigned long data)
375{
376 struct dw_spi *dws = (struct dw_spi *)data;
377 struct spi_message *message = NULL;
378 struct spi_transfer *transfer = NULL;
379 struct spi_transfer *previous = NULL;
380 struct spi_device *spi = NULL;
381 struct chip_data *chip = NULL;
382 u8 bits = 0;
383 u8 imask = 0;
384 u8 cs_change = 0;
385 u16 txint_level = 0;
386 u16 clk_div = 0;
387 u32 speed = 0;
388 u32 cr0 = 0;
389
390 /* Get current state information */
391 message = dws->cur_msg;
392 transfer = dws->cur_transfer;
393 chip = dws->cur_chip;
394 spi = message->spi;
395
396 if (unlikely(!chip->clk_div))
397 chip->clk_div = dws->max_freq / chip->speed_hz;
398
399 if (message->state == ERROR_STATE) {
400 message->status = -EIO;
401 goto early_exit;
402 }
403
404 /* Handle end of message */
405 if (message->state == DONE_STATE) {
406 message->status = 0;
407 goto early_exit;
408 }
409
410 /* Delay if requested at end of transfer*/
411 if (message->state == RUNNING_STATE) {
412 previous = list_entry(transfer->transfer_list.prev,
413 struct spi_transfer,
414 transfer_list);
415 if (previous->delay_usecs)
416 udelay(previous->delay_usecs);
417 }
418
419 dws->n_bytes = chip->n_bytes;
420 dws->dma_width = chip->dma_width;
421 dws->cs_control = chip->cs_control;
422
423 dws->rx_dma = transfer->rx_dma;
424 dws->tx_dma = transfer->tx_dma;
425 dws->tx = (void *)transfer->tx_buf;
426 dws->tx_end = dws->tx + transfer->len;
427 dws->rx = transfer->rx_buf;
428 dws->rx_end = dws->rx + transfer->len;
429 dws->len = dws->cur_transfer->len;
430 if (chip != dws->prev_chip)
431 cs_change = 1;
432
433 cr0 = chip->cr0;
434
435 /* Handle per transfer options for bpw and speed */
436 if (transfer->speed_hz) {
437 speed = chip->speed_hz;
438
439 if (transfer->speed_hz != speed) {
440 speed = transfer->speed_hz;
441
442 /* clk_div doesn't support odd number */
443 clk_div = dws->max_freq / speed;
444 clk_div = (clk_div + 1) & 0xfffe;
445
446 chip->speed_hz = speed;
447 chip->clk_div = clk_div;
448 }
449 }
450 if (transfer->bits_per_word) {
451 bits = transfer->bits_per_word;
452 dws->n_bytes = dws->dma_width = bits >> 3;
453 cr0 = (bits - 1)
454 | (chip->type << SPI_FRF_OFFSET)
455 | (spi->mode << SPI_MODE_OFFSET)
456 | (chip->tmode << SPI_TMOD_OFFSET);
457 }
458 message->state = RUNNING_STATE;
459
460 /*
461 * Adjust transfer mode if necessary. Requires platform dependent
462 * chipselect mechanism.
463 */
464 if (dws->cs_control) {
465 if (dws->rx && dws->tx)
466 chip->tmode = SPI_TMOD_TR;
467 else if (dws->rx)
468 chip->tmode = SPI_TMOD_RO;
469 else
470 chip->tmode = SPI_TMOD_TO;
471
472 cr0 &= ~SPI_TMOD_MASK;
473 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
474 }
475
476 /* Check if current transfer is a DMA transaction */
477 dws->dma_mapped = map_dma_buffers(dws);
478
479 /*
480 * Interrupt mode
481 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
482 */
483 if (!dws->dma_mapped && !chip->poll_mode) {
484 int templen = dws->len / dws->n_bytes;
485 txint_level = dws->fifo_len / 2;
486 txint_level = (templen > txint_level) ? txint_level : templen;
487
488 imask |= SPI_INT_TXEI | SPI_INT_TXOI | SPI_INT_RXUI | SPI_INT_RXOI;
489 dws->transfer_handler = interrupt_transfer;
490 }
491
492 /*
493 * Reprogram registers only if
494 * 1. chip select changes
495 * 2. clk_div is changed
496 * 3. control value changes
497 */
498 if (dw_readw(dws, DW_SPI_CTRL0) != cr0 || cs_change || clk_div || imask) {
499 spi_enable_chip(dws, 0);
500
501 if (dw_readw(dws, DW_SPI_CTRL0) != cr0)
502 dw_writew(dws, DW_SPI_CTRL0, cr0);
503
504 spi_set_clk(dws, clk_div ? clk_div : chip->clk_div);
505 spi_chip_sel(dws, spi->chip_select);
506
507 /* Set the interrupt mask, for poll mode just disable all int */
508 spi_mask_intr(dws, 0xff);
509 if (imask)
510 spi_umask_intr(dws, imask);
511 if (txint_level)
512 dw_writew(dws, DW_SPI_TXFLTR, txint_level);
513
514 spi_enable_chip(dws, 1);
515 if (cs_change)
516 dws->prev_chip = chip;
517 }
518
519 if (dws->dma_mapped)
520 dws->dma_ops->dma_transfer(dws, cs_change);
521
522 if (chip->poll_mode)
523 poll_transfer(dws);
524
525 return;
526
527early_exit:
528 giveback(dws);
529 return;
530}
531
532static void pump_messages(struct work_struct *work)
533{
534 struct dw_spi *dws =
535 container_of(work, struct dw_spi, pump_messages);
536 unsigned long flags;
537
538 /* Lock queue and check for queue work */
539 spin_lock_irqsave(&dws->lock, flags);
540 if (list_empty(&dws->queue) || dws->run == QUEUE_STOPPED) {
541 dws->busy = 0;
542 spin_unlock_irqrestore(&dws->lock, flags);
543 return;
544 }
545
546 /* Make sure we are not already running a message */
547 if (dws->cur_msg) {
548 spin_unlock_irqrestore(&dws->lock, flags);
549 return;
550 }
551
552 /* Extract head of queue */
553 dws->cur_msg = list_entry(dws->queue.next, struct spi_message, queue);
554 list_del_init(&dws->cur_msg->queue);
555
556 /* Initial message state*/
557 dws->cur_msg->state = START_STATE;
558 dws->cur_transfer = list_entry(dws->cur_msg->transfers.next,
559 struct spi_transfer,
560 transfer_list);
561 dws->cur_chip = spi_get_ctldata(dws->cur_msg->spi);
562
563 /* Mark as busy and launch transfers */
564 tasklet_schedule(&dws->pump_transfers);
565
566 dws->busy = 1;
567 spin_unlock_irqrestore(&dws->lock, flags);
568}
569
570/* spi_device use this to queue in their spi_msg */
571static int dw_spi_transfer(struct spi_device *spi, struct spi_message *msg)
572{
573 struct dw_spi *dws = spi_master_get_devdata(spi->master);
574 unsigned long flags;
575
576 spin_lock_irqsave(&dws->lock, flags);
577
578 if (dws->run == QUEUE_STOPPED) {
579 spin_unlock_irqrestore(&dws->lock, flags);
580 return -ESHUTDOWN;
581 }
582
583 msg->actual_length = 0;
584 msg->status = -EINPROGRESS;
585 msg->state = START_STATE;
586
587 list_add_tail(&msg->queue, &dws->queue);
588
589 if (dws->run == QUEUE_RUNNING && !dws->busy) {
590
591 if (dws->cur_transfer || dws->cur_msg)
592 queue_work(dws->workqueue,
593 &dws->pump_messages);
594 else {
595 /* If no other data transaction in air, just go */
596 spin_unlock_irqrestore(&dws->lock, flags);
597 pump_messages(&dws->pump_messages);
598 return 0;
599 }
600 }
601
602 spin_unlock_irqrestore(&dws->lock, flags);
603 return 0;
604}
605
606/* This may be called twice for each spi dev */
607static int dw_spi_setup(struct spi_device *spi)
608{
609 struct dw_spi_chip *chip_info = NULL;
610 struct chip_data *chip;
611
612 /* Only alloc on first setup */
613 chip = spi_get_ctldata(spi);
614 if (!chip) {
615 chip = devm_kzalloc(&spi->dev, sizeof(struct chip_data),
616 GFP_KERNEL);
617 if (!chip)
618 return -ENOMEM;
619 spi_set_ctldata(spi, chip);
620 }
621
622 /*
623 * Protocol drivers may change the chip settings, so...
624 * if chip_info exists, use it
625 */
626 chip_info = spi->controller_data;
627
628 /* chip_info doesn't always exist */
629 if (chip_info) {
630 if (chip_info->cs_control)
631 chip->cs_control = chip_info->cs_control;
632
633 chip->poll_mode = chip_info->poll_mode;
634 chip->type = chip_info->type;
635
636 chip->rx_threshold = 0;
637 chip->tx_threshold = 0;
638
639 chip->enable_dma = chip_info->enable_dma;
640 }
641
642 if (spi->bits_per_word == 8) {
643 chip->n_bytes = 1;
644 chip->dma_width = 1;
645 } else if (spi->bits_per_word == 16) {
646 chip->n_bytes = 2;
647 chip->dma_width = 2;
648 }
649 chip->bits_per_word = spi->bits_per_word;
650
651 if (!spi->max_speed_hz) {
652 dev_err(&spi->dev, "No max speed HZ parameter\n");
653 return -EINVAL;
654 }
655 chip->speed_hz = spi->max_speed_hz;
656
657 chip->tmode = 0; /* Tx & Rx */
658 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
659 chip->cr0 = (chip->bits_per_word - 1)
660 | (chip->type << SPI_FRF_OFFSET)
661 | (spi->mode << SPI_MODE_OFFSET)
662 | (chip->tmode << SPI_TMOD_OFFSET);
663
664 return 0;
665}
666
667static int init_queue(struct dw_spi *dws)
668{
669 INIT_LIST_HEAD(&dws->queue);
670 spin_lock_init(&dws->lock);
671
672 dws->run = QUEUE_STOPPED;
673 dws->busy = 0;
674
675 tasklet_init(&dws->pump_transfers,
676 pump_transfers, (unsigned long)dws);
677
678 INIT_WORK(&dws->pump_messages, pump_messages);
679 dws->workqueue = create_singlethread_workqueue(
680 dev_name(dws->master->dev.parent));
681 if (dws->workqueue == NULL)
682 return -EBUSY;
683
684 return 0;
685}
686
687static int start_queue(struct dw_spi *dws)
688{
689 unsigned long flags;
690
691 spin_lock_irqsave(&dws->lock, flags);
692
693 if (dws->run == QUEUE_RUNNING || dws->busy) {
694 spin_unlock_irqrestore(&dws->lock, flags);
695 return -EBUSY;
696 }
697
698 dws->run = QUEUE_RUNNING;
699 dws->cur_msg = NULL;
700 dws->cur_transfer = NULL;
701 dws->cur_chip = NULL;
702 dws->prev_chip = NULL;
703 spin_unlock_irqrestore(&dws->lock, flags);
704
705 queue_work(dws->workqueue, &dws->pump_messages);
706
707 return 0;
708}
709
710static int stop_queue(struct dw_spi *dws)
711{
712 unsigned long flags;
713 unsigned limit = 50;
714 int status = 0;
715
716 spin_lock_irqsave(&dws->lock, flags);
717 dws->run = QUEUE_STOPPED;
718 while ((!list_empty(&dws->queue) || dws->busy) && limit--) {
719 spin_unlock_irqrestore(&dws->lock, flags);
720 msleep(10);
721 spin_lock_irqsave(&dws->lock, flags);
722 }
723
724 if (!list_empty(&dws->queue) || dws->busy)
725 status = -EBUSY;
726 spin_unlock_irqrestore(&dws->lock, flags);
727
728 return status;
729}
730
731static int destroy_queue(struct dw_spi *dws)
732{
733 int status;
734
735 status = stop_queue(dws);
736 if (status != 0)
737 return status;
738 destroy_workqueue(dws->workqueue);
739 return 0;
740}
741
742/* Restart the controller, disable all interrupts, clean rx fifo */
743static void spi_hw_init(struct dw_spi *dws)
744{
745 spi_enable_chip(dws, 0);
746 spi_mask_intr(dws, 0xff);
747 spi_enable_chip(dws, 1);
748
749 /*
750 * Try to detect the FIFO depth if not set by interface driver,
751 * the depth could be from 2 to 256 from HW spec
752 */
753 if (!dws->fifo_len) {
754 u32 fifo;
755 for (fifo = 2; fifo <= 257; fifo++) {
756 dw_writew(dws, DW_SPI_TXFLTR, fifo);
757 if (fifo != dw_readw(dws, DW_SPI_TXFLTR))
758 break;
759 }
760
761 dws->fifo_len = (fifo == 257) ? 0 : fifo;
762 dw_writew(dws, DW_SPI_TXFLTR, 0);
763 }
764}
765
766int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
767{
768 struct spi_master *master;
769 int ret;
770
771 BUG_ON(dws == NULL);
772
773 master = spi_alloc_master(dev, 0);
774 if (!master)
775 return -ENOMEM;
776
777 dws->master = master;
778 dws->type = SSI_MOTO_SPI;
779 dws->prev_chip = NULL;
780 dws->dma_inited = 0;
781 dws->dma_addr = (dma_addr_t)(dws->paddr + 0x60);
782 snprintf(dws->name, sizeof(dws->name), "dw_spi%d",
783 dws->bus_num);
784
785 ret = devm_request_irq(dev, dws->irq, dw_spi_irq, IRQF_SHARED,
786 dws->name, dws);
787 if (ret < 0) {
788 dev_err(&master->dev, "can not get IRQ\n");
789 goto err_free_master;
790 }
791
792 master->mode_bits = SPI_CPOL | SPI_CPHA;
793 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
794 master->bus_num = dws->bus_num;
795 master->num_chipselect = dws->num_cs;
796 master->setup = dw_spi_setup;
797 master->transfer = dw_spi_transfer;
798 master->max_speed_hz = dws->max_freq;
799
800 /* Basic HW init */
801 spi_hw_init(dws);
802
803 if (dws->dma_ops && dws->dma_ops->dma_init) {
804 ret = dws->dma_ops->dma_init(dws);
805 if (ret) {
806 dev_warn(&master->dev, "DMA init failed\n");
807 dws->dma_inited = 0;
808 }
809 }
810
811 /* Initial and start queue */
812 ret = init_queue(dws);
813 if (ret) {
814 dev_err(&master->dev, "problem initializing queue\n");
815 goto err_diable_hw;
816 }
817 ret = start_queue(dws);
818 if (ret) {
819 dev_err(&master->dev, "problem starting queue\n");
820 goto err_diable_hw;
821 }
822
823 spi_master_set_devdata(master, dws);
824 ret = devm_spi_register_master(dev, master);
825 if (ret) {
826 dev_err(&master->dev, "problem registering spi master\n");
827 goto err_queue_alloc;
828 }
829
830 mrst_spi_debugfs_init(dws);
831 return 0;
832
833err_queue_alloc:
834 destroy_queue(dws);
835 if (dws->dma_ops && dws->dma_ops->dma_exit)
836 dws->dma_ops->dma_exit(dws);
837err_diable_hw:
838 spi_enable_chip(dws, 0);
839err_free_master:
840 spi_master_put(master);
841 return ret;
842}
843EXPORT_SYMBOL_GPL(dw_spi_add_host);
844
845void dw_spi_remove_host(struct dw_spi *dws)
846{
847 int status = 0;
848
849 if (!dws)
850 return;
851 mrst_spi_debugfs_remove(dws);
852
853 /* Remove the queue */
854 status = destroy_queue(dws);
855 if (status != 0)
856 dev_err(&dws->master->dev,
857 "dw_spi_remove: workqueue will not complete, message memory not freed\n");
858
859 if (dws->dma_ops && dws->dma_ops->dma_exit)
860 dws->dma_ops->dma_exit(dws);
861 spi_enable_chip(dws, 0);
862 /* Disable clk */
863 spi_set_clk(dws, 0);
864}
865EXPORT_SYMBOL_GPL(dw_spi_remove_host);
866
867int dw_spi_suspend_host(struct dw_spi *dws)
868{
869 int ret = 0;
870
871 ret = stop_queue(dws);
872 if (ret)
873 return ret;
874 spi_enable_chip(dws, 0);
875 spi_set_clk(dws, 0);
876 return ret;
877}
878EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
879
880int dw_spi_resume_host(struct dw_spi *dws)
881{
882 int ret;
883
884 spi_hw_init(dws);
885 ret = start_queue(dws);
886 if (ret)
887 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
888 return ret;
889}
890EXPORT_SYMBOL_GPL(dw_spi_resume_host);
891
892MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
893MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
894MODULE_LICENSE("GPL v2");