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1/*
2 * ECAP PWM driver
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/module.h>
22#include <linux/platform_device.h>
23#include <linux/io.h>
24#include <linux/err.h>
25#include <linux/clk.h>
26#include <linux/pm_runtime.h>
27#include <linux/pwm.h>
28#include <linux/of_device.h>
29
30#include "pwm-tipwmss.h"
31
32/* ECAP registers and bits definitions */
33#define CAP1 0x08
34#define CAP2 0x0C
35#define CAP3 0x10
36#define CAP4 0x14
37#define ECCTL2 0x2A
38#define ECCTL2_APWM_POL_LOW BIT(10)
39#define ECCTL2_APWM_MODE BIT(9)
40#define ECCTL2_SYNC_SEL_DISA (BIT(7) | BIT(6))
41#define ECCTL2_TSCTR_FREERUN BIT(4)
42
43struct ecap_context {
44 u32 cap3;
45 u32 cap4;
46 u16 ecctl2;
47};
48
49struct ecap_pwm_chip {
50 struct pwm_chip chip;
51 unsigned int clk_rate;
52 void __iomem *mmio_base;
53 struct ecap_context ctx;
54};
55
56static inline struct ecap_pwm_chip *to_ecap_pwm_chip(struct pwm_chip *chip)
57{
58 return container_of(chip, struct ecap_pwm_chip, chip);
59}
60
61/*
62 * period_ns = 10^9 * period_cycles / PWM_CLK_RATE
63 * duty_ns = 10^9 * duty_cycles / PWM_CLK_RATE
64 */
65static int ecap_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
66 int duty_ns, int period_ns)
67{
68 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
69 unsigned long long c;
70 unsigned long period_cycles, duty_cycles;
71 unsigned int reg_val;
72
73 if (period_ns > NSEC_PER_SEC)
74 return -ERANGE;
75
76 c = pc->clk_rate;
77 c = c * period_ns;
78 do_div(c, NSEC_PER_SEC);
79 period_cycles = (unsigned long)c;
80
81 if (period_cycles < 1) {
82 period_cycles = 1;
83 duty_cycles = 1;
84 } else {
85 c = pc->clk_rate;
86 c = c * duty_ns;
87 do_div(c, NSEC_PER_SEC);
88 duty_cycles = (unsigned long)c;
89 }
90
91 pm_runtime_get_sync(pc->chip.dev);
92
93 reg_val = readw(pc->mmio_base + ECCTL2);
94
95 /* Configure APWM mode & disable sync option */
96 reg_val |= ECCTL2_APWM_MODE | ECCTL2_SYNC_SEL_DISA;
97
98 writew(reg_val, pc->mmio_base + ECCTL2);
99
100 if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
101 /* Update active registers if not running */
102 writel(duty_cycles, pc->mmio_base + CAP2);
103 writel(period_cycles, pc->mmio_base + CAP1);
104 } else {
105 /*
106 * Update shadow registers to configure period and
107 * compare values. This helps current PWM period to
108 * complete on reconfiguring
109 */
110 writel(duty_cycles, pc->mmio_base + CAP4);
111 writel(period_cycles, pc->mmio_base + CAP3);
112 }
113
114 if (!test_bit(PWMF_ENABLED, &pwm->flags)) {
115 reg_val = readw(pc->mmio_base + ECCTL2);
116 /* Disable APWM mode to put APWM output Low */
117 reg_val &= ~ECCTL2_APWM_MODE;
118 writew(reg_val, pc->mmio_base + ECCTL2);
119 }
120
121 pm_runtime_put_sync(pc->chip.dev);
122 return 0;
123}
124
125static int ecap_pwm_set_polarity(struct pwm_chip *chip, struct pwm_device *pwm,
126 enum pwm_polarity polarity)
127{
128 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
129 unsigned short reg_val;
130
131 pm_runtime_get_sync(pc->chip.dev);
132 reg_val = readw(pc->mmio_base + ECCTL2);
133 if (polarity == PWM_POLARITY_INVERSED)
134 /* Duty cycle defines LOW period of PWM */
135 reg_val |= ECCTL2_APWM_POL_LOW;
136 else
137 /* Duty cycle defines HIGH period of PWM */
138 reg_val &= ~ECCTL2_APWM_POL_LOW;
139
140 writew(reg_val, pc->mmio_base + ECCTL2);
141 pm_runtime_put_sync(pc->chip.dev);
142 return 0;
143}
144
145static int ecap_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
146{
147 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
148 unsigned int reg_val;
149
150 /* Leave clock enabled on enabling PWM */
151 pm_runtime_get_sync(pc->chip.dev);
152
153 /*
154 * Enable 'Free run Time stamp counter mode' to start counter
155 * and 'APWM mode' to enable APWM output
156 */
157 reg_val = readw(pc->mmio_base + ECCTL2);
158 reg_val |= ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE;
159 writew(reg_val, pc->mmio_base + ECCTL2);
160 return 0;
161}
162
163static void ecap_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
164{
165 struct ecap_pwm_chip *pc = to_ecap_pwm_chip(chip);
166 unsigned int reg_val;
167
168 /*
169 * Disable 'Free run Time stamp counter mode' to stop counter
170 * and 'APWM mode' to put APWM output to low
171 */
172 reg_val = readw(pc->mmio_base + ECCTL2);
173 reg_val &= ~(ECCTL2_TSCTR_FREERUN | ECCTL2_APWM_MODE);
174 writew(reg_val, pc->mmio_base + ECCTL2);
175
176 /* Disable clock on PWM disable */
177 pm_runtime_put_sync(pc->chip.dev);
178}
179
180static void ecap_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
181{
182 if (test_bit(PWMF_ENABLED, &pwm->flags)) {
183 dev_warn(chip->dev, "Removing PWM device without disabling\n");
184 pm_runtime_put_sync(chip->dev);
185 }
186}
187
188static const struct pwm_ops ecap_pwm_ops = {
189 .free = ecap_pwm_free,
190 .config = ecap_pwm_config,
191 .set_polarity = ecap_pwm_set_polarity,
192 .enable = ecap_pwm_enable,
193 .disable = ecap_pwm_disable,
194 .owner = THIS_MODULE,
195};
196
197static const struct of_device_id ecap_of_match[] = {
198 { .compatible = "ti,am33xx-ecap" },
199 {},
200};
201MODULE_DEVICE_TABLE(of, ecap_of_match);
202
203static int ecap_pwm_probe(struct platform_device *pdev)
204{
205 int ret;
206 struct resource *r;
207 struct clk *clk;
208 struct ecap_pwm_chip *pc;
209 u16 status;
210
211 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
212 if (!pc) {
213 dev_err(&pdev->dev, "failed to allocate memory\n");
214 return -ENOMEM;
215 }
216
217 clk = devm_clk_get(&pdev->dev, "fck");
218 if (IS_ERR(clk)) {
219 dev_err(&pdev->dev, "failed to get clock\n");
220 return PTR_ERR(clk);
221 }
222
223 pc->clk_rate = clk_get_rate(clk);
224 if (!pc->clk_rate) {
225 dev_err(&pdev->dev, "failed to get clock rate\n");
226 return -EINVAL;
227 }
228
229 pc->chip.dev = &pdev->dev;
230 pc->chip.ops = &ecap_pwm_ops;
231 pc->chip.of_xlate = of_pwm_xlate_with_flags;
232 pc->chip.of_pwm_n_cells = 3;
233 pc->chip.base = -1;
234 pc->chip.npwm = 1;
235
236 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
237 pc->mmio_base = devm_ioremap_resource(&pdev->dev, r);
238 if (IS_ERR(pc->mmio_base))
239 return PTR_ERR(pc->mmio_base);
240
241 ret = pwmchip_add(&pc->chip);
242 if (ret < 0) {
243 dev_err(&pdev->dev, "pwmchip_add() failed: %d\n", ret);
244 return ret;
245 }
246
247 pm_runtime_enable(&pdev->dev);
248 pm_runtime_get_sync(&pdev->dev);
249
250 status = pwmss_submodule_state_change(pdev->dev.parent,
251 PWMSS_ECAPCLK_EN);
252 if (!(status & PWMSS_ECAPCLK_EN_ACK)) {
253 dev_err(&pdev->dev, "PWMSS config space clock enable failed\n");
254 ret = -EINVAL;
255 goto pwmss_clk_failure;
256 }
257
258 pm_runtime_put_sync(&pdev->dev);
259
260 platform_set_drvdata(pdev, pc);
261 return 0;
262
263pwmss_clk_failure:
264 pm_runtime_put_sync(&pdev->dev);
265 pm_runtime_disable(&pdev->dev);
266 pwmchip_remove(&pc->chip);
267 return ret;
268}
269
270static int ecap_pwm_remove(struct platform_device *pdev)
271{
272 struct ecap_pwm_chip *pc = platform_get_drvdata(pdev);
273
274 pm_runtime_get_sync(&pdev->dev);
275 /*
276 * Due to hardware misbehaviour, acknowledge of the stop_req
277 * is missing. Hence checking of the status bit skipped.
278 */
279 pwmss_submodule_state_change(pdev->dev.parent, PWMSS_ECAPCLK_STOP_REQ);
280 pm_runtime_put_sync(&pdev->dev);
281
282 pm_runtime_disable(&pdev->dev);
283 return pwmchip_remove(&pc->chip);
284}
285
286#ifdef CONFIG_PM_SLEEP
287static void ecap_pwm_save_context(struct ecap_pwm_chip *pc)
288{
289 pm_runtime_get_sync(pc->chip.dev);
290 pc->ctx.ecctl2 = readw(pc->mmio_base + ECCTL2);
291 pc->ctx.cap4 = readl(pc->mmio_base + CAP4);
292 pc->ctx.cap3 = readl(pc->mmio_base + CAP3);
293 pm_runtime_put_sync(pc->chip.dev);
294}
295
296static void ecap_pwm_restore_context(struct ecap_pwm_chip *pc)
297{
298 writel(pc->ctx.cap3, pc->mmio_base + CAP3);
299 writel(pc->ctx.cap4, pc->mmio_base + CAP4);
300 writew(pc->ctx.ecctl2, pc->mmio_base + ECCTL2);
301}
302
303static int ecap_pwm_suspend(struct device *dev)
304{
305 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
306 struct pwm_device *pwm = pc->chip.pwms;
307
308 ecap_pwm_save_context(pc);
309
310 /* Disable explicitly if PWM is running */
311 if (test_bit(PWMF_ENABLED, &pwm->flags))
312 pm_runtime_put_sync(dev);
313
314 return 0;
315}
316
317static int ecap_pwm_resume(struct device *dev)
318{
319 struct ecap_pwm_chip *pc = dev_get_drvdata(dev);
320 struct pwm_device *pwm = pc->chip.pwms;
321
322 /* Enable explicitly if PWM was running */
323 if (test_bit(PWMF_ENABLED, &pwm->flags))
324 pm_runtime_get_sync(dev);
325
326 ecap_pwm_restore_context(pc);
327 return 0;
328}
329#endif
330
331static SIMPLE_DEV_PM_OPS(ecap_pwm_pm_ops, ecap_pwm_suspend, ecap_pwm_resume);
332
333static struct platform_driver ecap_pwm_driver = {
334 .driver = {
335 .name = "ecap",
336 .owner = THIS_MODULE,
337 .of_match_table = ecap_of_match,
338 .pm = &ecap_pwm_pm_ops,
339 },
340 .probe = ecap_pwm_probe,
341 .remove = ecap_pwm_remove,
342};
343
344module_platform_driver(ecap_pwm_driver);
345
346MODULE_DESCRIPTION("ECAP PWM driver");
347MODULE_AUTHOR("Texas Instruments");
348MODULE_LICENSE("GPL");