Loading...
Note: File does not exist in v3.1.
1/*
2 * Copyright (c) 2012 Qualcomm Atheros, Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/interrupt.h>
18
19#include "wil6210.h"
20#include "trace.h"
21
22/**
23 * Theory of operation:
24 *
25 * There is ISR pseudo-cause register,
26 * dma_rgf->DMA_RGF.PSEUDO_CAUSE.PSEUDO_CAUSE
27 * Its bits represents OR'ed bits from 3 real ISR registers:
28 * TX, RX, and MISC.
29 *
30 * Registers may be configured to either "write 1 to clear" or
31 * "clear on read" mode
32 *
33 * When handling interrupt, one have to mask/unmask interrupts for the
34 * real ISR registers, or hardware may malfunction.
35 *
36 */
37
38#define WIL6210_IRQ_DISABLE (0xFFFFFFFFUL)
39#define WIL6210_IMC_RX BIT_DMA_EP_RX_ICR_RX_DONE
40#define WIL6210_IMC_TX (BIT_DMA_EP_TX_ICR_TX_DONE | \
41 BIT_DMA_EP_TX_ICR_TX_DONE_N(0))
42#define WIL6210_IMC_MISC (ISR_MISC_FW_READY | \
43 ISR_MISC_MBOX_EVT | \
44 ISR_MISC_FW_ERROR)
45
46#define WIL6210_IRQ_PSEUDO_MASK (u32)(~(BIT_DMA_PSEUDO_CAUSE_RX | \
47 BIT_DMA_PSEUDO_CAUSE_TX | \
48 BIT_DMA_PSEUDO_CAUSE_MISC))
49
50#if defined(CONFIG_WIL6210_ISR_COR)
51/* configure to Clear-On-Read mode */
52#define WIL_ICR_ICC_VALUE (0xFFFFFFFFUL)
53
54static inline void wil_icr_clear(u32 x, void __iomem *addr)
55{
56}
57#else /* defined(CONFIG_WIL6210_ISR_COR) */
58/* configure to Write-1-to-Clear mode */
59#define WIL_ICR_ICC_VALUE (0UL)
60
61static inline void wil_icr_clear(u32 x, void __iomem *addr)
62{
63 iowrite32(x, addr);
64}
65#endif /* defined(CONFIG_WIL6210_ISR_COR) */
66
67static inline u32 wil_ioread32_and_clear(void __iomem *addr)
68{
69 u32 x = ioread32(addr);
70
71 wil_icr_clear(x, addr);
72
73 return x;
74}
75
76static void wil6210_mask_irq_tx(struct wil6210_priv *wil)
77{
78 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
79 HOSTADDR(RGF_DMA_EP_TX_ICR) +
80 offsetof(struct RGF_ICR, IMS));
81}
82
83static void wil6210_mask_irq_rx(struct wil6210_priv *wil)
84{
85 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
86 HOSTADDR(RGF_DMA_EP_RX_ICR) +
87 offsetof(struct RGF_ICR, IMS));
88}
89
90static void wil6210_mask_irq_misc(struct wil6210_priv *wil)
91{
92 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
93 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
94 offsetof(struct RGF_ICR, IMS));
95}
96
97static void wil6210_mask_irq_pseudo(struct wil6210_priv *wil)
98{
99 wil_dbg_irq(wil, "%s()\n", __func__);
100
101 iowrite32(WIL6210_IRQ_DISABLE, wil->csr +
102 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
103
104 clear_bit(wil_status_irqen, &wil->status);
105}
106
107void wil6210_unmask_irq_tx(struct wil6210_priv *wil)
108{
109 iowrite32(WIL6210_IMC_TX, wil->csr +
110 HOSTADDR(RGF_DMA_EP_TX_ICR) +
111 offsetof(struct RGF_ICR, IMC));
112}
113
114void wil6210_unmask_irq_rx(struct wil6210_priv *wil)
115{
116 iowrite32(WIL6210_IMC_RX, wil->csr +
117 HOSTADDR(RGF_DMA_EP_RX_ICR) +
118 offsetof(struct RGF_ICR, IMC));
119}
120
121static void wil6210_unmask_irq_misc(struct wil6210_priv *wil)
122{
123 iowrite32(WIL6210_IMC_MISC, wil->csr +
124 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
125 offsetof(struct RGF_ICR, IMC));
126}
127
128static void wil6210_unmask_irq_pseudo(struct wil6210_priv *wil)
129{
130 wil_dbg_irq(wil, "%s()\n", __func__);
131
132 set_bit(wil_status_irqen, &wil->status);
133
134 iowrite32(WIL6210_IRQ_PSEUDO_MASK, wil->csr +
135 HOSTADDR(RGF_DMA_PSEUDO_CAUSE_MASK_SW));
136}
137
138void wil6210_disable_irq(struct wil6210_priv *wil)
139{
140 wil_dbg_irq(wil, "%s()\n", __func__);
141
142 wil6210_mask_irq_tx(wil);
143 wil6210_mask_irq_rx(wil);
144 wil6210_mask_irq_misc(wil);
145 wil6210_mask_irq_pseudo(wil);
146}
147
148void wil6210_enable_irq(struct wil6210_priv *wil)
149{
150 wil_dbg_irq(wil, "%s()\n", __func__);
151
152 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
153 offsetof(struct RGF_ICR, ICC));
154 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
155 offsetof(struct RGF_ICR, ICC));
156 iowrite32(WIL_ICR_ICC_VALUE, wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
157 offsetof(struct RGF_ICR, ICC));
158
159 /* interrupt moderation parameters */
160 if (wil->wdev->iftype == NL80211_IFTYPE_MONITOR) {
161 /* disable interrupt moderation for monitor
162 * to get better timestamp precision
163 */
164 iowrite32(0, wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
165 } else {
166 iowrite32(WIL6210_ITR_TRSH,
167 wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_TRSH));
168 iowrite32(BIT_DMA_ITR_CNT_CRL_EN,
169 wil->csr + HOSTADDR(RGF_DMA_ITR_CNT_CRL));
170 }
171
172 wil6210_unmask_irq_pseudo(wil);
173 wil6210_unmask_irq_tx(wil);
174 wil6210_unmask_irq_rx(wil);
175 wil6210_unmask_irq_misc(wil);
176}
177
178static irqreturn_t wil6210_irq_rx(int irq, void *cookie)
179{
180 struct wil6210_priv *wil = cookie;
181 u32 isr = wil_ioread32_and_clear(wil->csr +
182 HOSTADDR(RGF_DMA_EP_RX_ICR) +
183 offsetof(struct RGF_ICR, ICR));
184
185 trace_wil6210_irq_rx(isr);
186 wil_dbg_irq(wil, "ISR RX 0x%08x\n", isr);
187
188 if (!isr) {
189 wil_err(wil, "spurious IRQ: RX\n");
190 return IRQ_NONE;
191 }
192
193 wil6210_mask_irq_rx(wil);
194
195 if (isr & BIT_DMA_EP_RX_ICR_RX_DONE) {
196 wil_dbg_irq(wil, "RX done\n");
197 isr &= ~BIT_DMA_EP_RX_ICR_RX_DONE;
198 if (test_bit(wil_status_reset_done, &wil->status)) {
199 wil_dbg_txrx(wil, "NAPI(Rx) schedule\n");
200 napi_schedule(&wil->napi_rx);
201 } else {
202 wil_err(wil, "Got Rx interrupt while in reset\n");
203 }
204 }
205
206 if (isr)
207 wil_err(wil, "un-handled RX ISR bits 0x%08x\n", isr);
208
209 /* Rx IRQ will be enabled when NAPI processing finished */
210
211 return IRQ_HANDLED;
212}
213
214static irqreturn_t wil6210_irq_tx(int irq, void *cookie)
215{
216 struct wil6210_priv *wil = cookie;
217 u32 isr = wil_ioread32_and_clear(wil->csr +
218 HOSTADDR(RGF_DMA_EP_TX_ICR) +
219 offsetof(struct RGF_ICR, ICR));
220
221 trace_wil6210_irq_tx(isr);
222 wil_dbg_irq(wil, "ISR TX 0x%08x\n", isr);
223
224 if (!isr) {
225 wil_err(wil, "spurious IRQ: TX\n");
226 return IRQ_NONE;
227 }
228
229 wil6210_mask_irq_tx(wil);
230
231 if (isr & BIT_DMA_EP_TX_ICR_TX_DONE) {
232 wil_dbg_irq(wil, "TX done\n");
233 isr &= ~BIT_DMA_EP_TX_ICR_TX_DONE;
234 /* clear also all VRING interrupts */
235 isr &= ~(BIT(25) - 1UL);
236 if (test_bit(wil_status_reset_done, &wil->status)) {
237 wil_dbg_txrx(wil, "NAPI(Tx) schedule\n");
238 napi_schedule(&wil->napi_tx);
239 } else {
240 wil_err(wil, "Got Tx interrupt while in reset\n");
241 }
242 }
243
244 if (isr)
245 wil_err(wil, "un-handled TX ISR bits 0x%08x\n", isr);
246
247 /* Tx IRQ will be enabled when NAPI processing finished */
248
249 return IRQ_HANDLED;
250}
251
252static void wil_notify_fw_error(struct wil6210_priv *wil)
253{
254 struct device *dev = &wil_to_ndev(wil)->dev;
255 char *envp[3] = {
256 [0] = "SOURCE=wil6210",
257 [1] = "EVENT=FW_ERROR",
258 [2] = NULL,
259 };
260 kobject_uevent_env(&dev->kobj, KOBJ_CHANGE, envp);
261}
262
263static void wil_cache_mbox_regs(struct wil6210_priv *wil)
264{
265 /* make shadow copy of registers that should not change on run time */
266 wil_memcpy_fromio_32(&wil->mbox_ctl, wil->csr + HOST_MBOX,
267 sizeof(struct wil6210_mbox_ctl));
268 wil_mbox_ring_le2cpus(&wil->mbox_ctl.rx);
269 wil_mbox_ring_le2cpus(&wil->mbox_ctl.tx);
270}
271
272static irqreturn_t wil6210_irq_misc(int irq, void *cookie)
273{
274 struct wil6210_priv *wil = cookie;
275 u32 isr = wil_ioread32_and_clear(wil->csr +
276 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
277 offsetof(struct RGF_ICR, ICR));
278
279 trace_wil6210_irq_misc(isr);
280 wil_dbg_irq(wil, "ISR MISC 0x%08x\n", isr);
281
282 if (!isr) {
283 wil_err(wil, "spurious IRQ: MISC\n");
284 return IRQ_NONE;
285 }
286
287 wil6210_mask_irq_misc(wil);
288
289 if (isr & ISR_MISC_FW_ERROR) {
290 wil_err(wil, "Firmware error detected\n");
291 clear_bit(wil_status_fwready, &wil->status);
292 /*
293 * do not clear @isr here - we do 2-nd part in thread
294 * there, user space get notified, and it should be done
295 * in non-atomic context
296 */
297 }
298
299 if (isr & ISR_MISC_FW_READY) {
300 wil_dbg_irq(wil, "IRQ: FW ready\n");
301 wil_cache_mbox_regs(wil);
302 set_bit(wil_status_reset_done, &wil->status);
303 /**
304 * Actual FW ready indicated by the
305 * WMI_FW_READY_EVENTID
306 */
307 isr &= ~ISR_MISC_FW_READY;
308 }
309
310 wil->isr_misc = isr;
311
312 if (isr) {
313 return IRQ_WAKE_THREAD;
314 } else {
315 wil6210_unmask_irq_misc(wil);
316 return IRQ_HANDLED;
317 }
318}
319
320static irqreturn_t wil6210_irq_misc_thread(int irq, void *cookie)
321{
322 struct wil6210_priv *wil = cookie;
323 u32 isr = wil->isr_misc;
324
325 trace_wil6210_irq_misc_thread(isr);
326 wil_dbg_irq(wil, "Thread ISR MISC 0x%08x\n", isr);
327
328 if (isr & ISR_MISC_FW_ERROR) {
329 wil_notify_fw_error(wil);
330 isr &= ~ISR_MISC_FW_ERROR;
331 wil_fw_error_recovery(wil);
332 }
333
334 if (isr & ISR_MISC_MBOX_EVT) {
335 wil_dbg_irq(wil, "MBOX event\n");
336 wmi_recv_cmd(wil);
337 isr &= ~ISR_MISC_MBOX_EVT;
338 }
339
340 if (isr)
341 wil_err(wil, "un-handled MISC ISR bits 0x%08x\n", isr);
342
343 wil->isr_misc = 0;
344
345 wil6210_unmask_irq_misc(wil);
346
347 return IRQ_HANDLED;
348}
349
350/**
351 * thread IRQ handler
352 */
353static irqreturn_t wil6210_thread_irq(int irq, void *cookie)
354{
355 struct wil6210_priv *wil = cookie;
356
357 wil_dbg_irq(wil, "Thread IRQ\n");
358 /* Discover real IRQ cause */
359 if (wil->isr_misc)
360 wil6210_irq_misc_thread(irq, cookie);
361
362 wil6210_unmask_irq_pseudo(wil);
363
364 return IRQ_HANDLED;
365}
366
367/* DEBUG
368 * There is subtle bug in hardware that causes IRQ to raise when it should be
369 * masked. It is quite rare and hard to debug.
370 *
371 * Catch irq issue if it happens and print all I can.
372 */
373static int wil6210_debug_irq_mask(struct wil6210_priv *wil, u32 pseudo_cause)
374{
375 if (!test_bit(wil_status_irqen, &wil->status)) {
376 u32 icm_rx = wil_ioread32_and_clear(wil->csr +
377 HOSTADDR(RGF_DMA_EP_RX_ICR) +
378 offsetof(struct RGF_ICR, ICM));
379 u32 icr_rx = wil_ioread32_and_clear(wil->csr +
380 HOSTADDR(RGF_DMA_EP_RX_ICR) +
381 offsetof(struct RGF_ICR, ICR));
382 u32 imv_rx = ioread32(wil->csr +
383 HOSTADDR(RGF_DMA_EP_RX_ICR) +
384 offsetof(struct RGF_ICR, IMV));
385 u32 icm_tx = wil_ioread32_and_clear(wil->csr +
386 HOSTADDR(RGF_DMA_EP_TX_ICR) +
387 offsetof(struct RGF_ICR, ICM));
388 u32 icr_tx = wil_ioread32_and_clear(wil->csr +
389 HOSTADDR(RGF_DMA_EP_TX_ICR) +
390 offsetof(struct RGF_ICR, ICR));
391 u32 imv_tx = ioread32(wil->csr +
392 HOSTADDR(RGF_DMA_EP_TX_ICR) +
393 offsetof(struct RGF_ICR, IMV));
394 u32 icm_misc = wil_ioread32_and_clear(wil->csr +
395 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
396 offsetof(struct RGF_ICR, ICM));
397 u32 icr_misc = wil_ioread32_and_clear(wil->csr +
398 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
399 offsetof(struct RGF_ICR, ICR));
400 u32 imv_misc = ioread32(wil->csr +
401 HOSTADDR(RGF_DMA_EP_MISC_ICR) +
402 offsetof(struct RGF_ICR, IMV));
403 wil_err(wil, "IRQ when it should be masked: pseudo 0x%08x\n"
404 "Rx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
405 "Tx icm:icr:imv 0x%08x 0x%08x 0x%08x\n"
406 "Misc icm:icr:imv 0x%08x 0x%08x 0x%08x\n",
407 pseudo_cause,
408 icm_rx, icr_rx, imv_rx,
409 icm_tx, icr_tx, imv_tx,
410 icm_misc, icr_misc, imv_misc);
411
412 return -EINVAL;
413 }
414
415 return 0;
416}
417
418static irqreturn_t wil6210_hardirq(int irq, void *cookie)
419{
420 irqreturn_t rc = IRQ_HANDLED;
421 struct wil6210_priv *wil = cookie;
422 u32 pseudo_cause = ioread32(wil->csr + HOSTADDR(RGF_DMA_PSEUDO_CAUSE));
423
424 /**
425 * pseudo_cause is Clear-On-Read, no need to ACK
426 */
427 if ((pseudo_cause == 0) || ((pseudo_cause & 0xff) == 0xff))
428 return IRQ_NONE;
429
430 /* FIXME: IRQ mask debug */
431 if (wil6210_debug_irq_mask(wil, pseudo_cause))
432 return IRQ_NONE;
433
434 trace_wil6210_irq_pseudo(pseudo_cause);
435 wil_dbg_irq(wil, "Pseudo IRQ 0x%08x\n", pseudo_cause);
436
437 wil6210_mask_irq_pseudo(wil);
438
439 /* Discover real IRQ cause
440 * There are 2 possible phases for every IRQ:
441 * - hard IRQ handler called right here
442 * - threaded handler called later
443 *
444 * Hard IRQ handler reads and clears ISR.
445 *
446 * If threaded handler requested, hard IRQ handler
447 * returns IRQ_WAKE_THREAD and saves ISR register value
448 * for the threaded handler use.
449 *
450 * voting for wake thread - need at least 1 vote
451 */
452 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_RX) &&
453 (wil6210_irq_rx(irq, cookie) == IRQ_WAKE_THREAD))
454 rc = IRQ_WAKE_THREAD;
455
456 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_TX) &&
457 (wil6210_irq_tx(irq, cookie) == IRQ_WAKE_THREAD))
458 rc = IRQ_WAKE_THREAD;
459
460 if ((pseudo_cause & BIT_DMA_PSEUDO_CAUSE_MISC) &&
461 (wil6210_irq_misc(irq, cookie) == IRQ_WAKE_THREAD))
462 rc = IRQ_WAKE_THREAD;
463
464 /* if thread is requested, it will unmask IRQ */
465 if (rc != IRQ_WAKE_THREAD)
466 wil6210_unmask_irq_pseudo(wil);
467
468 return rc;
469}
470
471static int wil6210_request_3msi(struct wil6210_priv *wil, int irq)
472{
473 int rc;
474 /*
475 * IRQ's are in the following order:
476 * - Tx
477 * - Rx
478 * - Misc
479 */
480
481 rc = request_irq(irq, wil6210_irq_tx, IRQF_SHARED,
482 WIL_NAME"_tx", wil);
483 if (rc)
484 return rc;
485
486 rc = request_irq(irq + 1, wil6210_irq_rx, IRQF_SHARED,
487 WIL_NAME"_rx", wil);
488 if (rc)
489 goto free0;
490
491 rc = request_threaded_irq(irq + 2, wil6210_irq_misc,
492 wil6210_irq_misc_thread,
493 IRQF_SHARED, WIL_NAME"_misc", wil);
494 if (rc)
495 goto free1;
496
497 return 0;
498 /* error branch */
499free1:
500 free_irq(irq + 1, wil);
501free0:
502 free_irq(irq, wil);
503
504 return rc;
505}
506/* can't use wil_ioread32_and_clear because ICC value is not ser yet */
507static inline void wil_clear32(void __iomem *addr)
508{
509 u32 x = ioread32(addr);
510
511 iowrite32(x, addr);
512}
513
514void wil6210_clear_irq(struct wil6210_priv *wil)
515{
516 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_RX_ICR) +
517 offsetof(struct RGF_ICR, ICR));
518 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_TX_ICR) +
519 offsetof(struct RGF_ICR, ICR));
520 wil_clear32(wil->csr + HOSTADDR(RGF_DMA_EP_MISC_ICR) +
521 offsetof(struct RGF_ICR, ICR));
522}
523
524int wil6210_init_irq(struct wil6210_priv *wil, int irq)
525{
526 int rc;
527 if (wil->n_msi == 3)
528 rc = wil6210_request_3msi(wil, irq);
529 else
530 rc = request_threaded_irq(irq, wil6210_hardirq,
531 wil6210_thread_irq,
532 wil->n_msi ? 0 : IRQF_SHARED,
533 WIL_NAME, wil);
534 if (rc)
535 return rc;
536
537 wil6210_enable_irq(wil);
538
539 return 0;
540}
541
542void wil6210_fini_irq(struct wil6210_priv *wil, int irq)
543{
544 wil6210_disable_irq(wil);
545 free_irq(irq, wil);
546 if (wil->n_msi == 3) {
547 free_irq(irq + 1, wil);
548 free_irq(irq + 2, wil);
549 }
550}