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1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define SKB_CB_ATHBUF(__skb) (*((struct ath_buf **)__skb->cb))
22
23static inline bool ath_is_alt_ant_ratio_better(int alt_ratio, int maxdelta,
24 int mindelta, int main_rssi_avg,
25 int alt_rssi_avg, int pkt_count)
26{
27 return (((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
28 (alt_rssi_avg > main_rssi_avg + maxdelta)) ||
29 (alt_rssi_avg > main_rssi_avg + mindelta)) && (pkt_count > 50);
30}
31
32static inline bool ath_ant_div_comb_alt_check(u8 div_group, int alt_ratio,
33 int curr_main_set, int curr_alt_set,
34 int alt_rssi_avg, int main_rssi_avg)
35{
36 bool result = false;
37 switch (div_group) {
38 case 0:
39 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
40 result = true;
41 break;
42 case 1:
43 case 2:
44 if ((((curr_main_set == ATH_ANT_DIV_COMB_LNA2) &&
45 (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) &&
46 (alt_rssi_avg >= (main_rssi_avg - 5))) ||
47 ((curr_main_set == ATH_ANT_DIV_COMB_LNA1) &&
48 (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) &&
49 (alt_rssi_avg >= (main_rssi_avg - 2)))) &&
50 (alt_rssi_avg >= 4))
51 result = true;
52 else
53 result = false;
54 break;
55 }
56
57 return result;
58}
59
60static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
61{
62 return sc->ps_enabled &&
63 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
64}
65
66/*
67 * Setup and link descriptors.
68 *
69 * 11N: we can no longer afford to self link the last descriptor.
70 * MAC acknowledges BA status as long as it copies frames to host
71 * buffer (or rx fifo). This can incorrectly acknowledge packets
72 * to a sender if last desc is self-linked.
73 */
74static void ath_rx_buf_link(struct ath_softc *sc, struct ath_buf *bf)
75{
76 struct ath_hw *ah = sc->sc_ah;
77 struct ath_common *common = ath9k_hw_common(ah);
78 struct ath_desc *ds;
79 struct sk_buff *skb;
80
81 ATH_RXBUF_RESET(bf);
82
83 ds = bf->bf_desc;
84 ds->ds_link = 0; /* link to null */
85 ds->ds_data = bf->bf_buf_addr;
86
87 /* virtual addr of the beginning of the buffer. */
88 skb = bf->bf_mpdu;
89 BUG_ON(skb == NULL);
90 ds->ds_vdata = skb->data;
91
92 /*
93 * setup rx descriptors. The rx_bufsize here tells the hardware
94 * how much data it can DMA to us and that we are prepared
95 * to process
96 */
97 ath9k_hw_setuprxdesc(ah, ds,
98 common->rx_bufsize,
99 0);
100
101 if (sc->rx.rxlink == NULL)
102 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
103 else
104 *sc->rx.rxlink = bf->bf_daddr;
105
106 sc->rx.rxlink = &ds->ds_link;
107}
108
109static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
110{
111 /* XXX block beacon interrupts */
112 ath9k_hw_setantenna(sc->sc_ah, antenna);
113 sc->rx.defant = antenna;
114 sc->rx.rxotherant = 0;
115}
116
117static void ath_opmode_init(struct ath_softc *sc)
118{
119 struct ath_hw *ah = sc->sc_ah;
120 struct ath_common *common = ath9k_hw_common(ah);
121
122 u32 rfilt, mfilt[2];
123
124 /* configure rx filter */
125 rfilt = ath_calcrxfilter(sc);
126 ath9k_hw_setrxfilter(ah, rfilt);
127
128 /* configure bssid mask */
129 ath_hw_setbssidmask(common);
130
131 /* configure operational mode */
132 ath9k_hw_setopmode(ah);
133
134 /* calculate and install multicast filter */
135 mfilt[0] = mfilt[1] = ~0;
136 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
137}
138
139static bool ath_rx_edma_buf_link(struct ath_softc *sc,
140 enum ath9k_rx_qtype qtype)
141{
142 struct ath_hw *ah = sc->sc_ah;
143 struct ath_rx_edma *rx_edma;
144 struct sk_buff *skb;
145 struct ath_buf *bf;
146
147 rx_edma = &sc->rx.rx_edma[qtype];
148 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
149 return false;
150
151 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
152 list_del_init(&bf->list);
153
154 skb = bf->bf_mpdu;
155
156 ATH_RXBUF_RESET(bf);
157 memset(skb->data, 0, ah->caps.rx_status_len);
158 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
159 ah->caps.rx_status_len, DMA_TO_DEVICE);
160
161 SKB_CB_ATHBUF(skb) = bf;
162 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
163 skb_queue_tail(&rx_edma->rx_fifo, skb);
164
165 return true;
166}
167
168static void ath_rx_addbuffer_edma(struct ath_softc *sc,
169 enum ath9k_rx_qtype qtype, int size)
170{
171 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
172 u32 nbuf = 0;
173
174 if (list_empty(&sc->rx.rxbuf)) {
175 ath_dbg(common, ATH_DBG_QUEUE, "No free rx buf available\n");
176 return;
177 }
178
179 while (!list_empty(&sc->rx.rxbuf)) {
180 nbuf++;
181
182 if (!ath_rx_edma_buf_link(sc, qtype))
183 break;
184
185 if (nbuf >= size)
186 break;
187 }
188}
189
190static void ath_rx_remove_buffer(struct ath_softc *sc,
191 enum ath9k_rx_qtype qtype)
192{
193 struct ath_buf *bf;
194 struct ath_rx_edma *rx_edma;
195 struct sk_buff *skb;
196
197 rx_edma = &sc->rx.rx_edma[qtype];
198
199 while ((skb = skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
200 bf = SKB_CB_ATHBUF(skb);
201 BUG_ON(!bf);
202 list_add_tail(&bf->list, &sc->rx.rxbuf);
203 }
204}
205
206static void ath_rx_edma_cleanup(struct ath_softc *sc)
207{
208 struct ath_hw *ah = sc->sc_ah;
209 struct ath_common *common = ath9k_hw_common(ah);
210 struct ath_buf *bf;
211
212 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
213 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
214
215 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
216 if (bf->bf_mpdu) {
217 dma_unmap_single(sc->dev, bf->bf_buf_addr,
218 common->rx_bufsize,
219 DMA_BIDIRECTIONAL);
220 dev_kfree_skb_any(bf->bf_mpdu);
221 bf->bf_buf_addr = 0;
222 bf->bf_mpdu = NULL;
223 }
224 }
225
226 INIT_LIST_HEAD(&sc->rx.rxbuf);
227
228 kfree(sc->rx.rx_bufptr);
229 sc->rx.rx_bufptr = NULL;
230}
231
232static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
233{
234 skb_queue_head_init(&rx_edma->rx_fifo);
235 skb_queue_head_init(&rx_edma->rx_buffers);
236 rx_edma->rx_fifo_hwsize = size;
237}
238
239static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
240{
241 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
242 struct ath_hw *ah = sc->sc_ah;
243 struct sk_buff *skb;
244 struct ath_buf *bf;
245 int error = 0, i;
246 u32 size;
247
248 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
249 ah->caps.rx_status_len);
250
251 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
252 ah->caps.rx_lp_qdepth);
253 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
254 ah->caps.rx_hp_qdepth);
255
256 size = sizeof(struct ath_buf) * nbufs;
257 bf = kzalloc(size, GFP_KERNEL);
258 if (!bf)
259 return -ENOMEM;
260
261 INIT_LIST_HEAD(&sc->rx.rxbuf);
262 sc->rx.rx_bufptr = bf;
263
264 for (i = 0; i < nbufs; i++, bf++) {
265 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
266 if (!skb) {
267 error = -ENOMEM;
268 goto rx_init_fail;
269 }
270
271 memset(skb->data, 0, common->rx_bufsize);
272 bf->bf_mpdu = skb;
273
274 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
275 common->rx_bufsize,
276 DMA_BIDIRECTIONAL);
277 if (unlikely(dma_mapping_error(sc->dev,
278 bf->bf_buf_addr))) {
279 dev_kfree_skb_any(skb);
280 bf->bf_mpdu = NULL;
281 bf->bf_buf_addr = 0;
282 ath_err(common,
283 "dma_mapping_error() on RX init\n");
284 error = -ENOMEM;
285 goto rx_init_fail;
286 }
287
288 list_add_tail(&bf->list, &sc->rx.rxbuf);
289 }
290
291 return 0;
292
293rx_init_fail:
294 ath_rx_edma_cleanup(sc);
295 return error;
296}
297
298static void ath_edma_start_recv(struct ath_softc *sc)
299{
300 spin_lock_bh(&sc->rx.rxbuflock);
301
302 ath9k_hw_rxena(sc->sc_ah);
303
304 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP,
305 sc->rx.rx_edma[ATH9K_RX_QUEUE_HP].rx_fifo_hwsize);
306
307 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP,
308 sc->rx.rx_edma[ATH9K_RX_QUEUE_LP].rx_fifo_hwsize);
309
310 ath_opmode_init(sc);
311
312 ath9k_hw_startpcureceive(sc->sc_ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
313
314 spin_unlock_bh(&sc->rx.rxbuflock);
315}
316
317static void ath_edma_stop_recv(struct ath_softc *sc)
318{
319 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
320 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
321}
322
323int ath_rx_init(struct ath_softc *sc, int nbufs)
324{
325 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
326 struct sk_buff *skb;
327 struct ath_buf *bf;
328 int error = 0;
329
330 spin_lock_init(&sc->sc_pcu_lock);
331 sc->sc_flags &= ~SC_OP_RXFLUSH;
332 spin_lock_init(&sc->rx.rxbuflock);
333
334 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
335 sc->sc_ah->caps.rx_status_len;
336
337 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
338 return ath_rx_edma_init(sc, nbufs);
339 } else {
340 ath_dbg(common, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
341 common->cachelsz, common->rx_bufsize);
342
343 /* Initialize rx descriptors */
344
345 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
346 "rx", nbufs, 1, 0);
347 if (error != 0) {
348 ath_err(common,
349 "failed to allocate rx descriptors: %d\n",
350 error);
351 goto err;
352 }
353
354 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
355 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
356 GFP_KERNEL);
357 if (skb == NULL) {
358 error = -ENOMEM;
359 goto err;
360 }
361
362 bf->bf_mpdu = skb;
363 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
364 common->rx_bufsize,
365 DMA_FROM_DEVICE);
366 if (unlikely(dma_mapping_error(sc->dev,
367 bf->bf_buf_addr))) {
368 dev_kfree_skb_any(skb);
369 bf->bf_mpdu = NULL;
370 bf->bf_buf_addr = 0;
371 ath_err(common,
372 "dma_mapping_error() on RX init\n");
373 error = -ENOMEM;
374 goto err;
375 }
376 }
377 sc->rx.rxlink = NULL;
378 }
379
380err:
381 if (error)
382 ath_rx_cleanup(sc);
383
384 return error;
385}
386
387void ath_rx_cleanup(struct ath_softc *sc)
388{
389 struct ath_hw *ah = sc->sc_ah;
390 struct ath_common *common = ath9k_hw_common(ah);
391 struct sk_buff *skb;
392 struct ath_buf *bf;
393
394 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
395 ath_rx_edma_cleanup(sc);
396 return;
397 } else {
398 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
399 skb = bf->bf_mpdu;
400 if (skb) {
401 dma_unmap_single(sc->dev, bf->bf_buf_addr,
402 common->rx_bufsize,
403 DMA_FROM_DEVICE);
404 dev_kfree_skb(skb);
405 bf->bf_buf_addr = 0;
406 bf->bf_mpdu = NULL;
407 }
408 }
409
410 if (sc->rx.rxdma.dd_desc_len != 0)
411 ath_descdma_cleanup(sc, &sc->rx.rxdma, &sc->rx.rxbuf);
412 }
413}
414
415/*
416 * Calculate the receive filter according to the
417 * operating mode and state:
418 *
419 * o always accept unicast, broadcast, and multicast traffic
420 * o maintain current state of phy error reception (the hal
421 * may enable phy error frames for noise immunity work)
422 * o probe request frames are accepted only when operating in
423 * hostap, adhoc, or monitor modes
424 * o enable promiscuous mode according to the interface state
425 * o accept beacons:
426 * - when operating in adhoc mode so the 802.11 layer creates
427 * node table entries for peers,
428 * - when operating in station mode for collecting rssi data when
429 * the station is otherwise quiet, or
430 * - when operating as a repeater so we see repeater-sta beacons
431 * - when scanning
432 */
433
434u32 ath_calcrxfilter(struct ath_softc *sc)
435{
436#define RX_FILTER_PRESERVE (ATH9K_RX_FILTER_PHYERR | ATH9K_RX_FILTER_PHYRADAR)
437
438 u32 rfilt;
439
440 rfilt = (ath9k_hw_getrxfilter(sc->sc_ah) & RX_FILTER_PRESERVE)
441 | ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
442 | ATH9K_RX_FILTER_MCAST;
443
444 if (sc->rx.rxfilter & FIF_PROBE_REQ)
445 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
446
447 /*
448 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
449 * mode interface or when in monitor mode. AP mode does not need this
450 * since it receives all in-BSS frames anyway.
451 */
452 if (sc->sc_ah->is_monitoring)
453 rfilt |= ATH9K_RX_FILTER_PROM;
454
455 if (sc->rx.rxfilter & FIF_CONTROL)
456 rfilt |= ATH9K_RX_FILTER_CONTROL;
457
458 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
459 (sc->nvifs <= 1) &&
460 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
461 rfilt |= ATH9K_RX_FILTER_MYBEACON;
462 else
463 rfilt |= ATH9K_RX_FILTER_BEACON;
464
465 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
466 (sc->rx.rxfilter & FIF_PSPOLL))
467 rfilt |= ATH9K_RX_FILTER_PSPOLL;
468
469 if (conf_is_ht(&sc->hw->conf))
470 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
471
472 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
473 /* The following may also be needed for other older chips */
474 if (sc->sc_ah->hw_version.macVersion == AR_SREV_VERSION_9160)
475 rfilt |= ATH9K_RX_FILTER_PROM;
476 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
477 }
478
479 return rfilt;
480
481#undef RX_FILTER_PRESERVE
482}
483
484int ath_startrecv(struct ath_softc *sc)
485{
486 struct ath_hw *ah = sc->sc_ah;
487 struct ath_buf *bf, *tbf;
488
489 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
490 ath_edma_start_recv(sc);
491 return 0;
492 }
493
494 spin_lock_bh(&sc->rx.rxbuflock);
495 if (list_empty(&sc->rx.rxbuf))
496 goto start_recv;
497
498 sc->rx.rxlink = NULL;
499 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
500 ath_rx_buf_link(sc, bf);
501 }
502
503 /* We could have deleted elements so the list may be empty now */
504 if (list_empty(&sc->rx.rxbuf))
505 goto start_recv;
506
507 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
508 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
509 ath9k_hw_rxena(ah);
510
511start_recv:
512 ath_opmode_init(sc);
513 ath9k_hw_startpcureceive(ah, (sc->sc_flags & SC_OP_OFFCHANNEL));
514
515 spin_unlock_bh(&sc->rx.rxbuflock);
516
517 return 0;
518}
519
520bool ath_stoprecv(struct ath_softc *sc)
521{
522 struct ath_hw *ah = sc->sc_ah;
523 bool stopped, reset = false;
524
525 spin_lock_bh(&sc->rx.rxbuflock);
526 ath9k_hw_abortpcurecv(ah);
527 ath9k_hw_setrxfilter(ah, 0);
528 stopped = ath9k_hw_stopdmarecv(ah, &reset);
529
530 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
531 ath_edma_stop_recv(sc);
532 else
533 sc->rx.rxlink = NULL;
534 spin_unlock_bh(&sc->rx.rxbuflock);
535
536 if (!(ah->ah_flags & AH_UNPLUGGED) &&
537 unlikely(!stopped)) {
538 ath_err(ath9k_hw_common(sc->sc_ah),
539 "Could not stop RX, we could be "
540 "confusing the DMA engine when we start RX up\n");
541 ATH_DBG_WARN_ON_ONCE(!stopped);
542 }
543 return stopped && !reset;
544}
545
546void ath_flushrecv(struct ath_softc *sc)
547{
548 sc->sc_flags |= SC_OP_RXFLUSH;
549 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
550 ath_rx_tasklet(sc, 1, true);
551 ath_rx_tasklet(sc, 1, false);
552 sc->sc_flags &= ~SC_OP_RXFLUSH;
553}
554
555static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
556{
557 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
558 struct ieee80211_mgmt *mgmt;
559 u8 *pos, *end, id, elen;
560 struct ieee80211_tim_ie *tim;
561
562 mgmt = (struct ieee80211_mgmt *)skb->data;
563 pos = mgmt->u.beacon.variable;
564 end = skb->data + skb->len;
565
566 while (pos + 2 < end) {
567 id = *pos++;
568 elen = *pos++;
569 if (pos + elen > end)
570 break;
571
572 if (id == WLAN_EID_TIM) {
573 if (elen < sizeof(*tim))
574 break;
575 tim = (struct ieee80211_tim_ie *) pos;
576 if (tim->dtim_count != 0)
577 break;
578 return tim->bitmap_ctrl & 0x01;
579 }
580
581 pos += elen;
582 }
583
584 return false;
585}
586
587static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
588{
589 struct ieee80211_mgmt *mgmt;
590 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
591
592 if (skb->len < 24 + 8 + 2 + 2)
593 return;
594
595 mgmt = (struct ieee80211_mgmt *)skb->data;
596 if (memcmp(common->curbssid, mgmt->bssid, ETH_ALEN) != 0) {
597 /* TODO: This doesn't work well if you have stations
598 * associated to two different APs because curbssid
599 * is just the last AP that any of the stations associated
600 * with.
601 */
602 return; /* not from our current AP */
603 }
604
605 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
606
607 if (sc->ps_flags & PS_BEACON_SYNC) {
608 sc->ps_flags &= ~PS_BEACON_SYNC;
609 ath_dbg(common, ATH_DBG_PS,
610 "Reconfigure Beacon timers based on timestamp from the AP\n");
611 ath_set_beacon(sc);
612 sc->ps_flags &= ~PS_TSFOOR_SYNC;
613 }
614
615 if (ath_beacon_dtim_pending_cab(skb)) {
616 /*
617 * Remain awake waiting for buffered broadcast/multicast
618 * frames. If the last broadcast/multicast frame is not
619 * received properly, the next beacon frame will work as
620 * a backup trigger for returning into NETWORK SLEEP state,
621 * so we are waiting for it as well.
622 */
623 ath_dbg(common, ATH_DBG_PS,
624 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
625 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
626 return;
627 }
628
629 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
630 /*
631 * This can happen if a broadcast frame is dropped or the AP
632 * fails to send a frame indicating that all CAB frames have
633 * been delivered.
634 */
635 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
636 ath_dbg(common, ATH_DBG_PS,
637 "PS wait for CAB frames timed out\n");
638 }
639}
640
641static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
642{
643 struct ieee80211_hdr *hdr;
644 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
645
646 hdr = (struct ieee80211_hdr *)skb->data;
647
648 /* Process Beacon and CAB receive in PS state */
649 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
650 && ieee80211_is_beacon(hdr->frame_control))
651 ath_rx_ps_beacon(sc, skb);
652 else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
653 (ieee80211_is_data(hdr->frame_control) ||
654 ieee80211_is_action(hdr->frame_control)) &&
655 is_multicast_ether_addr(hdr->addr1) &&
656 !ieee80211_has_moredata(hdr->frame_control)) {
657 /*
658 * No more broadcast/multicast frames to be received at this
659 * point.
660 */
661 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
662 ath_dbg(common, ATH_DBG_PS,
663 "All PS CAB frames received, back to sleep\n");
664 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
665 !is_multicast_ether_addr(hdr->addr1) &&
666 !ieee80211_has_morefrags(hdr->frame_control)) {
667 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
668 ath_dbg(common, ATH_DBG_PS,
669 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
670 sc->ps_flags & (PS_WAIT_FOR_BEACON |
671 PS_WAIT_FOR_CAB |
672 PS_WAIT_FOR_PSPOLL_DATA |
673 PS_WAIT_FOR_TX_ACK));
674 }
675}
676
677static bool ath_edma_get_buffers(struct ath_softc *sc,
678 enum ath9k_rx_qtype qtype)
679{
680 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
681 struct ath_hw *ah = sc->sc_ah;
682 struct ath_common *common = ath9k_hw_common(ah);
683 struct sk_buff *skb;
684 struct ath_buf *bf;
685 int ret;
686
687 skb = skb_peek(&rx_edma->rx_fifo);
688 if (!skb)
689 return false;
690
691 bf = SKB_CB_ATHBUF(skb);
692 BUG_ON(!bf);
693
694 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
695 common->rx_bufsize, DMA_FROM_DEVICE);
696
697 ret = ath9k_hw_process_rxdesc_edma(ah, NULL, skb->data);
698 if (ret == -EINPROGRESS) {
699 /*let device gain the buffer again*/
700 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
701 common->rx_bufsize, DMA_FROM_DEVICE);
702 return false;
703 }
704
705 __skb_unlink(skb, &rx_edma->rx_fifo);
706 if (ret == -EINVAL) {
707 /* corrupt descriptor, skip this one and the following one */
708 list_add_tail(&bf->list, &sc->rx.rxbuf);
709 ath_rx_edma_buf_link(sc, qtype);
710 skb = skb_peek(&rx_edma->rx_fifo);
711 if (!skb)
712 return true;
713
714 bf = SKB_CB_ATHBUF(skb);
715 BUG_ON(!bf);
716
717 __skb_unlink(skb, &rx_edma->rx_fifo);
718 list_add_tail(&bf->list, &sc->rx.rxbuf);
719 ath_rx_edma_buf_link(sc, qtype);
720 return true;
721 }
722 skb_queue_tail(&rx_edma->rx_buffers, skb);
723
724 return true;
725}
726
727static struct ath_buf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
728 struct ath_rx_status *rs,
729 enum ath9k_rx_qtype qtype)
730{
731 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
732 struct sk_buff *skb;
733 struct ath_buf *bf;
734
735 while (ath_edma_get_buffers(sc, qtype));
736 skb = __skb_dequeue(&rx_edma->rx_buffers);
737 if (!skb)
738 return NULL;
739
740 bf = SKB_CB_ATHBUF(skb);
741 ath9k_hw_process_rxdesc_edma(sc->sc_ah, rs, skb->data);
742 return bf;
743}
744
745static struct ath_buf *ath_get_next_rx_buf(struct ath_softc *sc,
746 struct ath_rx_status *rs)
747{
748 struct ath_hw *ah = sc->sc_ah;
749 struct ath_common *common = ath9k_hw_common(ah);
750 struct ath_desc *ds;
751 struct ath_buf *bf;
752 int ret;
753
754 if (list_empty(&sc->rx.rxbuf)) {
755 sc->rx.rxlink = NULL;
756 return NULL;
757 }
758
759 bf = list_first_entry(&sc->rx.rxbuf, struct ath_buf, list);
760 ds = bf->bf_desc;
761
762 /*
763 * Must provide the virtual address of the current
764 * descriptor, the physical address, and the virtual
765 * address of the next descriptor in the h/w chain.
766 * This allows the HAL to look ahead to see if the
767 * hardware is done with a descriptor by checking the
768 * done bit in the following descriptor and the address
769 * of the current descriptor the DMA engine is working
770 * on. All this is necessary because of our use of
771 * a self-linked list to avoid rx overruns.
772 */
773 ret = ath9k_hw_rxprocdesc(ah, ds, rs, 0);
774 if (ret == -EINPROGRESS) {
775 struct ath_rx_status trs;
776 struct ath_buf *tbf;
777 struct ath_desc *tds;
778
779 memset(&trs, 0, sizeof(trs));
780 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
781 sc->rx.rxlink = NULL;
782 return NULL;
783 }
784
785 tbf = list_entry(bf->list.next, struct ath_buf, list);
786
787 /*
788 * On some hardware the descriptor status words could
789 * get corrupted, including the done bit. Because of
790 * this, check if the next descriptor's done bit is
791 * set or not.
792 *
793 * If the next descriptor's done bit is set, the current
794 * descriptor has been corrupted. Force s/w to discard
795 * this descriptor and continue...
796 */
797
798 tds = tbf->bf_desc;
799 ret = ath9k_hw_rxprocdesc(ah, tds, &trs, 0);
800 if (ret == -EINPROGRESS)
801 return NULL;
802 }
803
804 if (!bf->bf_mpdu)
805 return bf;
806
807 /*
808 * Synchronize the DMA transfer with CPU before
809 * 1. accessing the frame
810 * 2. requeueing the same buffer to h/w
811 */
812 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
813 common->rx_bufsize,
814 DMA_FROM_DEVICE);
815
816 return bf;
817}
818
819/* Assumes you've already done the endian to CPU conversion */
820static bool ath9k_rx_accept(struct ath_common *common,
821 struct ieee80211_hdr *hdr,
822 struct ieee80211_rx_status *rxs,
823 struct ath_rx_status *rx_stats,
824 bool *decrypt_error)
825{
826 bool is_mc, is_valid_tkip, strip_mic, mic_error;
827 struct ath_hw *ah = common->ah;
828 __le16 fc;
829 u8 rx_status_len = ah->caps.rx_status_len;
830
831 fc = hdr->frame_control;
832
833 is_mc = !!is_multicast_ether_addr(hdr->addr1);
834 is_valid_tkip = rx_stats->rs_keyix != ATH9K_RXKEYIX_INVALID &&
835 test_bit(rx_stats->rs_keyix, common->tkip_keymap);
836 strip_mic = is_valid_tkip && !(rx_stats->rs_status &
837 (ATH9K_RXERR_DECRYPT | ATH9K_RXERR_CRC | ATH9K_RXERR_MIC));
838
839 if (!rx_stats->rs_datalen)
840 return false;
841 /*
842 * rs_status follows rs_datalen so if rs_datalen is too large
843 * we can take a hint that hardware corrupted it, so ignore
844 * those frames.
845 */
846 if (rx_stats->rs_datalen > (common->rx_bufsize - rx_status_len))
847 return false;
848
849 /* Only use error bits from the last fragment */
850 if (rx_stats->rs_more)
851 return true;
852
853 mic_error = is_valid_tkip && !ieee80211_is_ctl(fc) &&
854 !ieee80211_has_morefrags(fc) &&
855 !(le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG) &&
856 (rx_stats->rs_status & ATH9K_RXERR_MIC);
857
858 /*
859 * The rx_stats->rs_status will not be set until the end of the
860 * chained descriptors so it can be ignored if rs_more is set. The
861 * rs_more will be false at the last element of the chained
862 * descriptors.
863 */
864 if (rx_stats->rs_status != 0) {
865 if (rx_stats->rs_status & ATH9K_RXERR_CRC) {
866 rxs->flag |= RX_FLAG_FAILED_FCS_CRC;
867 mic_error = false;
868 }
869 if (rx_stats->rs_status & ATH9K_RXERR_PHY)
870 return false;
871
872 if (rx_stats->rs_status & ATH9K_RXERR_DECRYPT) {
873 *decrypt_error = true;
874 mic_error = false;
875 }
876
877 /*
878 * Reject error frames with the exception of
879 * decryption and MIC failures. For monitor mode,
880 * we also ignore the CRC error.
881 */
882 if (ah->is_monitoring) {
883 if (rx_stats->rs_status &
884 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC |
885 ATH9K_RXERR_CRC))
886 return false;
887 } else {
888 if (rx_stats->rs_status &
889 ~(ATH9K_RXERR_DECRYPT | ATH9K_RXERR_MIC)) {
890 return false;
891 }
892 }
893 }
894
895 /*
896 * For unicast frames the MIC error bit can have false positives,
897 * so all MIC error reports need to be validated in software.
898 * False negatives are not common, so skip software verification
899 * if the hardware considers the MIC valid.
900 */
901 if (strip_mic)
902 rxs->flag |= RX_FLAG_MMIC_STRIPPED;
903 else if (is_mc && mic_error)
904 rxs->flag |= RX_FLAG_MMIC_ERROR;
905
906 return true;
907}
908
909static int ath9k_process_rate(struct ath_common *common,
910 struct ieee80211_hw *hw,
911 struct ath_rx_status *rx_stats,
912 struct ieee80211_rx_status *rxs)
913{
914 struct ieee80211_supported_band *sband;
915 enum ieee80211_band band;
916 unsigned int i = 0;
917
918 band = hw->conf.channel->band;
919 sband = hw->wiphy->bands[band];
920
921 if (rx_stats->rs_rate & 0x80) {
922 /* HT rate */
923 rxs->flag |= RX_FLAG_HT;
924 if (rx_stats->rs_flags & ATH9K_RX_2040)
925 rxs->flag |= RX_FLAG_40MHZ;
926 if (rx_stats->rs_flags & ATH9K_RX_GI)
927 rxs->flag |= RX_FLAG_SHORT_GI;
928 rxs->rate_idx = rx_stats->rs_rate & 0x7f;
929 return 0;
930 }
931
932 for (i = 0; i < sband->n_bitrates; i++) {
933 if (sband->bitrates[i].hw_value == rx_stats->rs_rate) {
934 rxs->rate_idx = i;
935 return 0;
936 }
937 if (sband->bitrates[i].hw_value_short == rx_stats->rs_rate) {
938 rxs->flag |= RX_FLAG_SHORTPRE;
939 rxs->rate_idx = i;
940 return 0;
941 }
942 }
943
944 /*
945 * No valid hardware bitrate found -- we should not get here
946 * because hardware has already validated this frame as OK.
947 */
948 ath_dbg(common, ATH_DBG_XMIT,
949 "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
950 rx_stats->rs_rate);
951
952 return -EINVAL;
953}
954
955static void ath9k_process_rssi(struct ath_common *common,
956 struct ieee80211_hw *hw,
957 struct ieee80211_hdr *hdr,
958 struct ath_rx_status *rx_stats)
959{
960 struct ath_softc *sc = hw->priv;
961 struct ath_hw *ah = common->ah;
962 int last_rssi;
963 __le16 fc;
964
965 if ((ah->opmode != NL80211_IFTYPE_STATION) &&
966 (ah->opmode != NL80211_IFTYPE_ADHOC))
967 return;
968
969 fc = hdr->frame_control;
970 if (!ieee80211_is_beacon(fc) ||
971 compare_ether_addr(hdr->addr3, common->curbssid)) {
972 /* TODO: This doesn't work well if you have stations
973 * associated to two different APs because curbssid
974 * is just the last AP that any of the stations associated
975 * with.
976 */
977 return;
978 }
979
980 if (rx_stats->rs_rssi != ATH9K_RSSI_BAD && !rx_stats->rs_moreaggr)
981 ATH_RSSI_LPF(sc->last_rssi, rx_stats->rs_rssi);
982
983 last_rssi = sc->last_rssi;
984 if (likely(last_rssi != ATH_RSSI_DUMMY_MARKER))
985 rx_stats->rs_rssi = ATH_EP_RND(last_rssi,
986 ATH_RSSI_EP_MULTIPLIER);
987 if (rx_stats->rs_rssi < 0)
988 rx_stats->rs_rssi = 0;
989
990 /* Update Beacon RSSI, this is used by ANI. */
991 ah->stats.avgbrssi = rx_stats->rs_rssi;
992}
993
994/*
995 * For Decrypt or Demic errors, we only mark packet status here and always push
996 * up the frame up to let mac80211 handle the actual error case, be it no
997 * decryption key or real decryption error. This let us keep statistics there.
998 */
999static int ath9k_rx_skb_preprocess(struct ath_common *common,
1000 struct ieee80211_hw *hw,
1001 struct ieee80211_hdr *hdr,
1002 struct ath_rx_status *rx_stats,
1003 struct ieee80211_rx_status *rx_status,
1004 bool *decrypt_error)
1005{
1006 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
1007
1008 /*
1009 * everything but the rate is checked here, the rate check is done
1010 * separately to avoid doing two lookups for a rate for each frame.
1011 */
1012 if (!ath9k_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error))
1013 return -EINVAL;
1014
1015 /* Only use status info from the last fragment */
1016 if (rx_stats->rs_more)
1017 return 0;
1018
1019 ath9k_process_rssi(common, hw, hdr, rx_stats);
1020
1021 if (ath9k_process_rate(common, hw, rx_stats, rx_status))
1022 return -EINVAL;
1023
1024 rx_status->band = hw->conf.channel->band;
1025 rx_status->freq = hw->conf.channel->center_freq;
1026 rx_status->signal = ATH_DEFAULT_NOISE_FLOOR + rx_stats->rs_rssi;
1027 rx_status->antenna = rx_stats->rs_antenna;
1028 rx_status->flag |= RX_FLAG_MACTIME_MPDU;
1029
1030 return 0;
1031}
1032
1033static void ath9k_rx_skb_postprocess(struct ath_common *common,
1034 struct sk_buff *skb,
1035 struct ath_rx_status *rx_stats,
1036 struct ieee80211_rx_status *rxs,
1037 bool decrypt_error)
1038{
1039 struct ath_hw *ah = common->ah;
1040 struct ieee80211_hdr *hdr;
1041 int hdrlen, padpos, padsize;
1042 u8 keyix;
1043 __le16 fc;
1044
1045 /* see if any padding is done by the hw and remove it */
1046 hdr = (struct ieee80211_hdr *) skb->data;
1047 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1048 fc = hdr->frame_control;
1049 padpos = ath9k_cmn_padpos(hdr->frame_control);
1050
1051 /* The MAC header is padded to have 32-bit boundary if the
1052 * packet payload is non-zero. The general calculation for
1053 * padsize would take into account odd header lengths:
1054 * padsize = (4 - padpos % 4) % 4; However, since only
1055 * even-length headers are used, padding can only be 0 or 2
1056 * bytes and we can optimize this a bit. In addition, we must
1057 * not try to remove padding from short control frames that do
1058 * not have payload. */
1059 padsize = padpos & 3;
1060 if (padsize && skb->len>=padpos+padsize+FCS_LEN) {
1061 memmove(skb->data + padsize, skb->data, padpos);
1062 skb_pull(skb, padsize);
1063 }
1064
1065 keyix = rx_stats->rs_keyix;
1066
1067 if (!(keyix == ATH9K_RXKEYIX_INVALID) && !decrypt_error &&
1068 ieee80211_has_protected(fc)) {
1069 rxs->flag |= RX_FLAG_DECRYPTED;
1070 } else if (ieee80211_has_protected(fc)
1071 && !decrypt_error && skb->len >= hdrlen + 4) {
1072 keyix = skb->data[hdrlen + 3] >> 6;
1073
1074 if (test_bit(keyix, common->keymap))
1075 rxs->flag |= RX_FLAG_DECRYPTED;
1076 }
1077 if (ah->sw_mgmt_crypto &&
1078 (rxs->flag & RX_FLAG_DECRYPTED) &&
1079 ieee80211_is_mgmt(fc))
1080 /* Use software decrypt for management frames. */
1081 rxs->flag &= ~RX_FLAG_DECRYPTED;
1082}
1083
1084static void ath_lnaconf_alt_good_scan(struct ath_ant_comb *antcomb,
1085 struct ath_hw_antcomb_conf ant_conf,
1086 int main_rssi_avg)
1087{
1088 antcomb->quick_scan_cnt = 0;
1089
1090 if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA2)
1091 antcomb->rssi_lna2 = main_rssi_avg;
1092 else if (ant_conf.main_lna_conf == ATH_ANT_DIV_COMB_LNA1)
1093 antcomb->rssi_lna1 = main_rssi_avg;
1094
1095 switch ((ant_conf.main_lna_conf << 4) | ant_conf.alt_lna_conf) {
1096 case 0x10: /* LNA2 A-B */
1097 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1098 antcomb->first_quick_scan_conf =
1099 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1100 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1101 break;
1102 case 0x20: /* LNA1 A-B */
1103 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1104 antcomb->first_quick_scan_conf =
1105 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1106 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1107 break;
1108 case 0x21: /* LNA1 LNA2 */
1109 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA2;
1110 antcomb->first_quick_scan_conf =
1111 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1112 antcomb->second_quick_scan_conf =
1113 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1114 break;
1115 case 0x12: /* LNA2 LNA1 */
1116 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1;
1117 antcomb->first_quick_scan_conf =
1118 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1119 antcomb->second_quick_scan_conf =
1120 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1121 break;
1122 case 0x13: /* LNA2 A+B */
1123 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1124 antcomb->first_quick_scan_conf =
1125 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1126 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA1;
1127 break;
1128 case 0x23: /* LNA1 A+B */
1129 antcomb->main_conf = ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1130 antcomb->first_quick_scan_conf =
1131 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1132 antcomb->second_quick_scan_conf = ATH_ANT_DIV_COMB_LNA2;
1133 break;
1134 default:
1135 break;
1136 }
1137}
1138
1139static void ath_select_ant_div_from_quick_scan(struct ath_ant_comb *antcomb,
1140 struct ath_hw_antcomb_conf *div_ant_conf,
1141 int main_rssi_avg, int alt_rssi_avg,
1142 int alt_ratio)
1143{
1144 /* alt_good */
1145 switch (antcomb->quick_scan_cnt) {
1146 case 0:
1147 /* set alt to main, and alt to first conf */
1148 div_ant_conf->main_lna_conf = antcomb->main_conf;
1149 div_ant_conf->alt_lna_conf = antcomb->first_quick_scan_conf;
1150 break;
1151 case 1:
1152 /* set alt to main, and alt to first conf */
1153 div_ant_conf->main_lna_conf = antcomb->main_conf;
1154 div_ant_conf->alt_lna_conf = antcomb->second_quick_scan_conf;
1155 antcomb->rssi_first = main_rssi_avg;
1156 antcomb->rssi_second = alt_rssi_avg;
1157
1158 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1159 /* main is LNA1 */
1160 if (ath_is_alt_ant_ratio_better(alt_ratio,
1161 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1162 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1163 main_rssi_avg, alt_rssi_avg,
1164 antcomb->total_pkt_count))
1165 antcomb->first_ratio = true;
1166 else
1167 antcomb->first_ratio = false;
1168 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1169 if (ath_is_alt_ant_ratio_better(alt_ratio,
1170 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1171 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1172 main_rssi_avg, alt_rssi_avg,
1173 antcomb->total_pkt_count))
1174 antcomb->first_ratio = true;
1175 else
1176 antcomb->first_ratio = false;
1177 } else {
1178 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1179 (alt_rssi_avg > main_rssi_avg +
1180 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1181 (alt_rssi_avg > main_rssi_avg)) &&
1182 (antcomb->total_pkt_count > 50))
1183 antcomb->first_ratio = true;
1184 else
1185 antcomb->first_ratio = false;
1186 }
1187 break;
1188 case 2:
1189 antcomb->alt_good = false;
1190 antcomb->scan_not_start = false;
1191 antcomb->scan = false;
1192 antcomb->rssi_first = main_rssi_avg;
1193 antcomb->rssi_third = alt_rssi_avg;
1194
1195 if (antcomb->second_quick_scan_conf == ATH_ANT_DIV_COMB_LNA1)
1196 antcomb->rssi_lna1 = alt_rssi_avg;
1197 else if (antcomb->second_quick_scan_conf ==
1198 ATH_ANT_DIV_COMB_LNA2)
1199 antcomb->rssi_lna2 = alt_rssi_avg;
1200 else if (antcomb->second_quick_scan_conf ==
1201 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2) {
1202 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2)
1203 antcomb->rssi_lna2 = main_rssi_avg;
1204 else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1)
1205 antcomb->rssi_lna1 = main_rssi_avg;
1206 }
1207
1208 if (antcomb->rssi_lna2 > antcomb->rssi_lna1 +
1209 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)
1210 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1211 else
1212 div_ant_conf->main_lna_conf = ATH_ANT_DIV_COMB_LNA1;
1213
1214 if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) {
1215 if (ath_is_alt_ant_ratio_better(alt_ratio,
1216 ATH_ANT_DIV_COMB_LNA1_DELTA_HI,
1217 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1218 main_rssi_avg, alt_rssi_avg,
1219 antcomb->total_pkt_count))
1220 antcomb->second_ratio = true;
1221 else
1222 antcomb->second_ratio = false;
1223 } else if (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2) {
1224 if (ath_is_alt_ant_ratio_better(alt_ratio,
1225 ATH_ANT_DIV_COMB_LNA1_DELTA_MID,
1226 ATH_ANT_DIV_COMB_LNA1_DELTA_LOW,
1227 main_rssi_avg, alt_rssi_avg,
1228 antcomb->total_pkt_count))
1229 antcomb->second_ratio = true;
1230 else
1231 antcomb->second_ratio = false;
1232 } else {
1233 if ((((alt_ratio >= ATH_ANT_DIV_COMB_ALT_ANT_RATIO2) &&
1234 (alt_rssi_avg > main_rssi_avg +
1235 ATH_ANT_DIV_COMB_LNA1_DELTA_HI)) ||
1236 (alt_rssi_avg > main_rssi_avg)) &&
1237 (antcomb->total_pkt_count > 50))
1238 antcomb->second_ratio = true;
1239 else
1240 antcomb->second_ratio = false;
1241 }
1242
1243 /* set alt to the conf with maximun ratio */
1244 if (antcomb->first_ratio && antcomb->second_ratio) {
1245 if (antcomb->rssi_second > antcomb->rssi_third) {
1246 /* first alt*/
1247 if ((antcomb->first_quick_scan_conf ==
1248 ATH_ANT_DIV_COMB_LNA1) ||
1249 (antcomb->first_quick_scan_conf ==
1250 ATH_ANT_DIV_COMB_LNA2))
1251 /* Set alt LNA1 or LNA2*/
1252 if (div_ant_conf->main_lna_conf ==
1253 ATH_ANT_DIV_COMB_LNA2)
1254 div_ant_conf->alt_lna_conf =
1255 ATH_ANT_DIV_COMB_LNA1;
1256 else
1257 div_ant_conf->alt_lna_conf =
1258 ATH_ANT_DIV_COMB_LNA2;
1259 else
1260 /* Set alt to A+B or A-B */
1261 div_ant_conf->alt_lna_conf =
1262 antcomb->first_quick_scan_conf;
1263 } else if ((antcomb->second_quick_scan_conf ==
1264 ATH_ANT_DIV_COMB_LNA1) ||
1265 (antcomb->second_quick_scan_conf ==
1266 ATH_ANT_DIV_COMB_LNA2)) {
1267 /* Set alt LNA1 or LNA2 */
1268 if (div_ant_conf->main_lna_conf ==
1269 ATH_ANT_DIV_COMB_LNA2)
1270 div_ant_conf->alt_lna_conf =
1271 ATH_ANT_DIV_COMB_LNA1;
1272 else
1273 div_ant_conf->alt_lna_conf =
1274 ATH_ANT_DIV_COMB_LNA2;
1275 } else {
1276 /* Set alt to A+B or A-B */
1277 div_ant_conf->alt_lna_conf =
1278 antcomb->second_quick_scan_conf;
1279 }
1280 } else if (antcomb->first_ratio) {
1281 /* first alt */
1282 if ((antcomb->first_quick_scan_conf ==
1283 ATH_ANT_DIV_COMB_LNA1) ||
1284 (antcomb->first_quick_scan_conf ==
1285 ATH_ANT_DIV_COMB_LNA2))
1286 /* Set alt LNA1 or LNA2 */
1287 if (div_ant_conf->main_lna_conf ==
1288 ATH_ANT_DIV_COMB_LNA2)
1289 div_ant_conf->alt_lna_conf =
1290 ATH_ANT_DIV_COMB_LNA1;
1291 else
1292 div_ant_conf->alt_lna_conf =
1293 ATH_ANT_DIV_COMB_LNA2;
1294 else
1295 /* Set alt to A+B or A-B */
1296 div_ant_conf->alt_lna_conf =
1297 antcomb->first_quick_scan_conf;
1298 } else if (antcomb->second_ratio) {
1299 /* second alt */
1300 if ((antcomb->second_quick_scan_conf ==
1301 ATH_ANT_DIV_COMB_LNA1) ||
1302 (antcomb->second_quick_scan_conf ==
1303 ATH_ANT_DIV_COMB_LNA2))
1304 /* Set alt LNA1 or LNA2 */
1305 if (div_ant_conf->main_lna_conf ==
1306 ATH_ANT_DIV_COMB_LNA2)
1307 div_ant_conf->alt_lna_conf =
1308 ATH_ANT_DIV_COMB_LNA1;
1309 else
1310 div_ant_conf->alt_lna_conf =
1311 ATH_ANT_DIV_COMB_LNA2;
1312 else
1313 /* Set alt to A+B or A-B */
1314 div_ant_conf->alt_lna_conf =
1315 antcomb->second_quick_scan_conf;
1316 } else {
1317 /* main is largest */
1318 if ((antcomb->main_conf == ATH_ANT_DIV_COMB_LNA1) ||
1319 (antcomb->main_conf == ATH_ANT_DIV_COMB_LNA2))
1320 /* Set alt LNA1 or LNA2 */
1321 if (div_ant_conf->main_lna_conf ==
1322 ATH_ANT_DIV_COMB_LNA2)
1323 div_ant_conf->alt_lna_conf =
1324 ATH_ANT_DIV_COMB_LNA1;
1325 else
1326 div_ant_conf->alt_lna_conf =
1327 ATH_ANT_DIV_COMB_LNA2;
1328 else
1329 /* Set alt to A+B or A-B */
1330 div_ant_conf->alt_lna_conf = antcomb->main_conf;
1331 }
1332 break;
1333 default:
1334 break;
1335 }
1336}
1337
1338static void ath_ant_div_conf_fast_divbias(struct ath_hw_antcomb_conf *ant_conf,
1339 struct ath_ant_comb *antcomb, int alt_ratio)
1340{
1341 if (ant_conf->div_group == 0) {
1342 /* Adjust the fast_div_bias based on main and alt lna conf */
1343 switch ((ant_conf->main_lna_conf << 4) |
1344 ant_conf->alt_lna_conf) {
1345 case 0x01: /* A-B LNA2 */
1346 ant_conf->fast_div_bias = 0x3b;
1347 break;
1348 case 0x02: /* A-B LNA1 */
1349 ant_conf->fast_div_bias = 0x3d;
1350 break;
1351 case 0x03: /* A-B A+B */
1352 ant_conf->fast_div_bias = 0x1;
1353 break;
1354 case 0x10: /* LNA2 A-B */
1355 ant_conf->fast_div_bias = 0x7;
1356 break;
1357 case 0x12: /* LNA2 LNA1 */
1358 ant_conf->fast_div_bias = 0x2;
1359 break;
1360 case 0x13: /* LNA2 A+B */
1361 ant_conf->fast_div_bias = 0x7;
1362 break;
1363 case 0x20: /* LNA1 A-B */
1364 ant_conf->fast_div_bias = 0x6;
1365 break;
1366 case 0x21: /* LNA1 LNA2 */
1367 ant_conf->fast_div_bias = 0x0;
1368 break;
1369 case 0x23: /* LNA1 A+B */
1370 ant_conf->fast_div_bias = 0x6;
1371 break;
1372 case 0x30: /* A+B A-B */
1373 ant_conf->fast_div_bias = 0x1;
1374 break;
1375 case 0x31: /* A+B LNA2 */
1376 ant_conf->fast_div_bias = 0x3b;
1377 break;
1378 case 0x32: /* A+B LNA1 */
1379 ant_conf->fast_div_bias = 0x3d;
1380 break;
1381 default:
1382 break;
1383 }
1384 } else if (ant_conf->div_group == 1) {
1385 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1386 switch ((ant_conf->main_lna_conf << 4) |
1387 ant_conf->alt_lna_conf) {
1388 case 0x01: /* A-B LNA2 */
1389 ant_conf->fast_div_bias = 0x1;
1390 ant_conf->main_gaintb = 0;
1391 ant_conf->alt_gaintb = 0;
1392 break;
1393 case 0x02: /* A-B LNA1 */
1394 ant_conf->fast_div_bias = 0x1;
1395 ant_conf->main_gaintb = 0;
1396 ant_conf->alt_gaintb = 0;
1397 break;
1398 case 0x03: /* A-B A+B */
1399 ant_conf->fast_div_bias = 0x1;
1400 ant_conf->main_gaintb = 0;
1401 ant_conf->alt_gaintb = 0;
1402 break;
1403 case 0x10: /* LNA2 A-B */
1404 if (!(antcomb->scan) &&
1405 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1406 ant_conf->fast_div_bias = 0x3f;
1407 else
1408 ant_conf->fast_div_bias = 0x1;
1409 ant_conf->main_gaintb = 0;
1410 ant_conf->alt_gaintb = 0;
1411 break;
1412 case 0x12: /* LNA2 LNA1 */
1413 ant_conf->fast_div_bias = 0x1;
1414 ant_conf->main_gaintb = 0;
1415 ant_conf->alt_gaintb = 0;
1416 break;
1417 case 0x13: /* LNA2 A+B */
1418 if (!(antcomb->scan) &&
1419 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1420 ant_conf->fast_div_bias = 0x3f;
1421 else
1422 ant_conf->fast_div_bias = 0x1;
1423 ant_conf->main_gaintb = 0;
1424 ant_conf->alt_gaintb = 0;
1425 break;
1426 case 0x20: /* LNA1 A-B */
1427 if (!(antcomb->scan) &&
1428 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1429 ant_conf->fast_div_bias = 0x3f;
1430 else
1431 ant_conf->fast_div_bias = 0x1;
1432 ant_conf->main_gaintb = 0;
1433 ant_conf->alt_gaintb = 0;
1434 break;
1435 case 0x21: /* LNA1 LNA2 */
1436 ant_conf->fast_div_bias = 0x1;
1437 ant_conf->main_gaintb = 0;
1438 ant_conf->alt_gaintb = 0;
1439 break;
1440 case 0x23: /* LNA1 A+B */
1441 if (!(antcomb->scan) &&
1442 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1443 ant_conf->fast_div_bias = 0x3f;
1444 else
1445 ant_conf->fast_div_bias = 0x1;
1446 ant_conf->main_gaintb = 0;
1447 ant_conf->alt_gaintb = 0;
1448 break;
1449 case 0x30: /* A+B A-B */
1450 ant_conf->fast_div_bias = 0x1;
1451 ant_conf->main_gaintb = 0;
1452 ant_conf->alt_gaintb = 0;
1453 break;
1454 case 0x31: /* A+B LNA2 */
1455 ant_conf->fast_div_bias = 0x1;
1456 ant_conf->main_gaintb = 0;
1457 ant_conf->alt_gaintb = 0;
1458 break;
1459 case 0x32: /* A+B LNA1 */
1460 ant_conf->fast_div_bias = 0x1;
1461 ant_conf->main_gaintb = 0;
1462 ant_conf->alt_gaintb = 0;
1463 break;
1464 default:
1465 break;
1466 }
1467 } else if (ant_conf->div_group == 2) {
1468 /* Adjust the fast_div_bias based on main and alt_lna_conf */
1469 switch ((ant_conf->main_lna_conf << 4) |
1470 ant_conf->alt_lna_conf) {
1471 case 0x01: /* A-B LNA2 */
1472 ant_conf->fast_div_bias = 0x1;
1473 ant_conf->main_gaintb = 0;
1474 ant_conf->alt_gaintb = 0;
1475 break;
1476 case 0x02: /* A-B LNA1 */
1477 ant_conf->fast_div_bias = 0x1;
1478 ant_conf->main_gaintb = 0;
1479 ant_conf->alt_gaintb = 0;
1480 break;
1481 case 0x03: /* A-B A+B */
1482 ant_conf->fast_div_bias = 0x1;
1483 ant_conf->main_gaintb = 0;
1484 ant_conf->alt_gaintb = 0;
1485 break;
1486 case 0x10: /* LNA2 A-B */
1487 if (!(antcomb->scan) &&
1488 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1489 ant_conf->fast_div_bias = 0x1;
1490 else
1491 ant_conf->fast_div_bias = 0x2;
1492 ant_conf->main_gaintb = 0;
1493 ant_conf->alt_gaintb = 0;
1494 break;
1495 case 0x12: /* LNA2 LNA1 */
1496 ant_conf->fast_div_bias = 0x1;
1497 ant_conf->main_gaintb = 0;
1498 ant_conf->alt_gaintb = 0;
1499 break;
1500 case 0x13: /* LNA2 A+B */
1501 if (!(antcomb->scan) &&
1502 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1503 ant_conf->fast_div_bias = 0x1;
1504 else
1505 ant_conf->fast_div_bias = 0x2;
1506 ant_conf->main_gaintb = 0;
1507 ant_conf->alt_gaintb = 0;
1508 break;
1509 case 0x20: /* LNA1 A-B */
1510 if (!(antcomb->scan) &&
1511 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1512 ant_conf->fast_div_bias = 0x1;
1513 else
1514 ant_conf->fast_div_bias = 0x2;
1515 ant_conf->main_gaintb = 0;
1516 ant_conf->alt_gaintb = 0;
1517 break;
1518 case 0x21: /* LNA1 LNA2 */
1519 ant_conf->fast_div_bias = 0x1;
1520 ant_conf->main_gaintb = 0;
1521 ant_conf->alt_gaintb = 0;
1522 break;
1523 case 0x23: /* LNA1 A+B */
1524 if (!(antcomb->scan) &&
1525 (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO))
1526 ant_conf->fast_div_bias = 0x1;
1527 else
1528 ant_conf->fast_div_bias = 0x2;
1529 ant_conf->main_gaintb = 0;
1530 ant_conf->alt_gaintb = 0;
1531 break;
1532 case 0x30: /* A+B A-B */
1533 ant_conf->fast_div_bias = 0x1;
1534 ant_conf->main_gaintb = 0;
1535 ant_conf->alt_gaintb = 0;
1536 break;
1537 case 0x31: /* A+B LNA2 */
1538 ant_conf->fast_div_bias = 0x1;
1539 ant_conf->main_gaintb = 0;
1540 ant_conf->alt_gaintb = 0;
1541 break;
1542 case 0x32: /* A+B LNA1 */
1543 ant_conf->fast_div_bias = 0x1;
1544 ant_conf->main_gaintb = 0;
1545 ant_conf->alt_gaintb = 0;
1546 break;
1547 default:
1548 break;
1549 }
1550 }
1551}
1552
1553/* Antenna diversity and combining */
1554static void ath_ant_comb_scan(struct ath_softc *sc, struct ath_rx_status *rs)
1555{
1556 struct ath_hw_antcomb_conf div_ant_conf;
1557 struct ath_ant_comb *antcomb = &sc->ant_comb;
1558 int alt_ratio = 0, alt_rssi_avg = 0, main_rssi_avg = 0, curr_alt_set;
1559 int curr_main_set;
1560 int main_rssi = rs->rs_rssi_ctl0;
1561 int alt_rssi = rs->rs_rssi_ctl1;
1562 int rx_ant_conf, main_ant_conf;
1563 bool short_scan = false;
1564
1565 rx_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_CURRENT_SHIFT) &
1566 ATH_ANT_RX_MASK;
1567 main_ant_conf = (rs->rs_rssi_ctl2 >> ATH_ANT_RX_MAIN_SHIFT) &
1568 ATH_ANT_RX_MASK;
1569
1570 /* Record packet only when both main_rssi and alt_rssi is positive */
1571 if (main_rssi > 0 && alt_rssi > 0) {
1572 antcomb->total_pkt_count++;
1573 antcomb->main_total_rssi += main_rssi;
1574 antcomb->alt_total_rssi += alt_rssi;
1575 if (main_ant_conf == rx_ant_conf)
1576 antcomb->main_recv_cnt++;
1577 else
1578 antcomb->alt_recv_cnt++;
1579 }
1580
1581 /* Short scan check */
1582 if (antcomb->scan && antcomb->alt_good) {
1583 if (time_after(jiffies, antcomb->scan_start_time +
1584 msecs_to_jiffies(ATH_ANT_DIV_COMB_SHORT_SCAN_INTR)))
1585 short_scan = true;
1586 else
1587 if (antcomb->total_pkt_count ==
1588 ATH_ANT_DIV_COMB_SHORT_SCAN_PKTCOUNT) {
1589 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1590 antcomb->total_pkt_count);
1591 if (alt_ratio < ATH_ANT_DIV_COMB_ALT_ANT_RATIO)
1592 short_scan = true;
1593 }
1594 }
1595
1596 if (((antcomb->total_pkt_count < ATH_ANT_DIV_COMB_MAX_PKTCOUNT) ||
1597 rs->rs_moreaggr) && !short_scan)
1598 return;
1599
1600 if (antcomb->total_pkt_count) {
1601 alt_ratio = ((antcomb->alt_recv_cnt * 100) /
1602 antcomb->total_pkt_count);
1603 main_rssi_avg = (antcomb->main_total_rssi /
1604 antcomb->total_pkt_count);
1605 alt_rssi_avg = (antcomb->alt_total_rssi /
1606 antcomb->total_pkt_count);
1607 }
1608
1609
1610 ath9k_hw_antdiv_comb_conf_get(sc->sc_ah, &div_ant_conf);
1611 curr_alt_set = div_ant_conf.alt_lna_conf;
1612 curr_main_set = div_ant_conf.main_lna_conf;
1613
1614 antcomb->count++;
1615
1616 if (antcomb->count == ATH_ANT_DIV_COMB_MAX_COUNT) {
1617 if (alt_ratio > ATH_ANT_DIV_COMB_ALT_ANT_RATIO) {
1618 ath_lnaconf_alt_good_scan(antcomb, div_ant_conf,
1619 main_rssi_avg);
1620 antcomb->alt_good = true;
1621 } else {
1622 antcomb->alt_good = false;
1623 }
1624
1625 antcomb->count = 0;
1626 antcomb->scan = true;
1627 antcomb->scan_not_start = true;
1628 }
1629
1630 if (!antcomb->scan) {
1631 if (ath_ant_div_comb_alt_check(div_ant_conf.div_group,
1632 alt_ratio, curr_main_set, curr_alt_set,
1633 alt_rssi_avg, main_rssi_avg)) {
1634 if (curr_alt_set == ATH_ANT_DIV_COMB_LNA2) {
1635 /* Switch main and alt LNA */
1636 div_ant_conf.main_lna_conf =
1637 ATH_ANT_DIV_COMB_LNA2;
1638 div_ant_conf.alt_lna_conf =
1639 ATH_ANT_DIV_COMB_LNA1;
1640 } else if (curr_alt_set == ATH_ANT_DIV_COMB_LNA1) {
1641 div_ant_conf.main_lna_conf =
1642 ATH_ANT_DIV_COMB_LNA1;
1643 div_ant_conf.alt_lna_conf =
1644 ATH_ANT_DIV_COMB_LNA2;
1645 }
1646
1647 goto div_comb_done;
1648 } else if ((curr_alt_set != ATH_ANT_DIV_COMB_LNA1) &&
1649 (curr_alt_set != ATH_ANT_DIV_COMB_LNA2)) {
1650 /* Set alt to another LNA */
1651 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2)
1652 div_ant_conf.alt_lna_conf =
1653 ATH_ANT_DIV_COMB_LNA1;
1654 else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1)
1655 div_ant_conf.alt_lna_conf =
1656 ATH_ANT_DIV_COMB_LNA2;
1657
1658 goto div_comb_done;
1659 }
1660
1661 if ((alt_rssi_avg < (main_rssi_avg +
1662 div_ant_conf.lna1_lna2_delta)))
1663 goto div_comb_done;
1664 }
1665
1666 if (!antcomb->scan_not_start) {
1667 switch (curr_alt_set) {
1668 case ATH_ANT_DIV_COMB_LNA2:
1669 antcomb->rssi_lna2 = alt_rssi_avg;
1670 antcomb->rssi_lna1 = main_rssi_avg;
1671 antcomb->scan = true;
1672 /* set to A+B */
1673 div_ant_conf.main_lna_conf =
1674 ATH_ANT_DIV_COMB_LNA1;
1675 div_ant_conf.alt_lna_conf =
1676 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1677 break;
1678 case ATH_ANT_DIV_COMB_LNA1:
1679 antcomb->rssi_lna1 = alt_rssi_avg;
1680 antcomb->rssi_lna2 = main_rssi_avg;
1681 antcomb->scan = true;
1682 /* set to A+B */
1683 div_ant_conf.main_lna_conf = ATH_ANT_DIV_COMB_LNA2;
1684 div_ant_conf.alt_lna_conf =
1685 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1686 break;
1687 case ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2:
1688 antcomb->rssi_add = alt_rssi_avg;
1689 antcomb->scan = true;
1690 /* set to A-B */
1691 div_ant_conf.alt_lna_conf =
1692 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1693 break;
1694 case ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2:
1695 antcomb->rssi_sub = alt_rssi_avg;
1696 antcomb->scan = false;
1697 if (antcomb->rssi_lna2 >
1698 (antcomb->rssi_lna1 +
1699 ATH_ANT_DIV_COMB_LNA1_LNA2_SWITCH_DELTA)) {
1700 /* use LNA2 as main LNA */
1701 if ((antcomb->rssi_add > antcomb->rssi_lna1) &&
1702 (antcomb->rssi_add > antcomb->rssi_sub)) {
1703 /* set to A+B */
1704 div_ant_conf.main_lna_conf =
1705 ATH_ANT_DIV_COMB_LNA2;
1706 div_ant_conf.alt_lna_conf =
1707 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1708 } else if (antcomb->rssi_sub >
1709 antcomb->rssi_lna1) {
1710 /* set to A-B */
1711 div_ant_conf.main_lna_conf =
1712 ATH_ANT_DIV_COMB_LNA2;
1713 div_ant_conf.alt_lna_conf =
1714 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1715 } else {
1716 /* set to LNA1 */
1717 div_ant_conf.main_lna_conf =
1718 ATH_ANT_DIV_COMB_LNA2;
1719 div_ant_conf.alt_lna_conf =
1720 ATH_ANT_DIV_COMB_LNA1;
1721 }
1722 } else {
1723 /* use LNA1 as main LNA */
1724 if ((antcomb->rssi_add > antcomb->rssi_lna2) &&
1725 (antcomb->rssi_add > antcomb->rssi_sub)) {
1726 /* set to A+B */
1727 div_ant_conf.main_lna_conf =
1728 ATH_ANT_DIV_COMB_LNA1;
1729 div_ant_conf.alt_lna_conf =
1730 ATH_ANT_DIV_COMB_LNA1_PLUS_LNA2;
1731 } else if (antcomb->rssi_sub >
1732 antcomb->rssi_lna1) {
1733 /* set to A-B */
1734 div_ant_conf.main_lna_conf =
1735 ATH_ANT_DIV_COMB_LNA1;
1736 div_ant_conf.alt_lna_conf =
1737 ATH_ANT_DIV_COMB_LNA1_MINUS_LNA2;
1738 } else {
1739 /* set to LNA2 */
1740 div_ant_conf.main_lna_conf =
1741 ATH_ANT_DIV_COMB_LNA1;
1742 div_ant_conf.alt_lna_conf =
1743 ATH_ANT_DIV_COMB_LNA2;
1744 }
1745 }
1746 break;
1747 default:
1748 break;
1749 }
1750 } else {
1751 if (!antcomb->alt_good) {
1752 antcomb->scan_not_start = false;
1753 /* Set alt to another LNA */
1754 if (curr_main_set == ATH_ANT_DIV_COMB_LNA2) {
1755 div_ant_conf.main_lna_conf =
1756 ATH_ANT_DIV_COMB_LNA2;
1757 div_ant_conf.alt_lna_conf =
1758 ATH_ANT_DIV_COMB_LNA1;
1759 } else if (curr_main_set == ATH_ANT_DIV_COMB_LNA1) {
1760 div_ant_conf.main_lna_conf =
1761 ATH_ANT_DIV_COMB_LNA1;
1762 div_ant_conf.alt_lna_conf =
1763 ATH_ANT_DIV_COMB_LNA2;
1764 }
1765 goto div_comb_done;
1766 }
1767 }
1768
1769 ath_select_ant_div_from_quick_scan(antcomb, &div_ant_conf,
1770 main_rssi_avg, alt_rssi_avg,
1771 alt_ratio);
1772
1773 antcomb->quick_scan_cnt++;
1774
1775div_comb_done:
1776 ath_ant_div_conf_fast_divbias(&div_ant_conf, antcomb, alt_ratio);
1777 ath9k_hw_antdiv_comb_conf_set(sc->sc_ah, &div_ant_conf);
1778
1779 antcomb->scan_start_time = jiffies;
1780 antcomb->total_pkt_count = 0;
1781 antcomb->main_total_rssi = 0;
1782 antcomb->alt_total_rssi = 0;
1783 antcomb->main_recv_cnt = 0;
1784 antcomb->alt_recv_cnt = 0;
1785}
1786
1787int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
1788{
1789 struct ath_buf *bf;
1790 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
1791 struct ieee80211_rx_status *rxs;
1792 struct ath_hw *ah = sc->sc_ah;
1793 struct ath_common *common = ath9k_hw_common(ah);
1794 /*
1795 * The hw can technically differ from common->hw when using ath9k
1796 * virtual wiphy so to account for that we iterate over the active
1797 * wiphys and find the appropriate wiphy and therefore hw.
1798 */
1799 struct ieee80211_hw *hw = sc->hw;
1800 struct ieee80211_hdr *hdr;
1801 int retval;
1802 bool decrypt_error = false;
1803 struct ath_rx_status rs;
1804 enum ath9k_rx_qtype qtype;
1805 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
1806 int dma_type;
1807 u8 rx_status_len = ah->caps.rx_status_len;
1808 u64 tsf = 0;
1809 u32 tsf_lower = 0;
1810 unsigned long flags;
1811
1812 if (edma)
1813 dma_type = DMA_BIDIRECTIONAL;
1814 else
1815 dma_type = DMA_FROM_DEVICE;
1816
1817 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
1818 spin_lock_bh(&sc->rx.rxbuflock);
1819
1820 tsf = ath9k_hw_gettsf64(ah);
1821 tsf_lower = tsf & 0xffffffff;
1822
1823 do {
1824 /* If handling rx interrupt and flush is in progress => exit */
1825 if ((sc->sc_flags & SC_OP_RXFLUSH) && (flush == 0))
1826 break;
1827
1828 memset(&rs, 0, sizeof(rs));
1829 if (edma)
1830 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
1831 else
1832 bf = ath_get_next_rx_buf(sc, &rs);
1833
1834 if (!bf)
1835 break;
1836
1837 skb = bf->bf_mpdu;
1838 if (!skb)
1839 continue;
1840
1841 /*
1842 * Take frame header from the first fragment and RX status from
1843 * the last one.
1844 */
1845 if (sc->rx.frag)
1846 hdr_skb = sc->rx.frag;
1847 else
1848 hdr_skb = skb;
1849
1850 hdr = (struct ieee80211_hdr *) (hdr_skb->data + rx_status_len);
1851 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1852
1853 ath_debug_stat_rx(sc, &rs);
1854
1855 /*
1856 * If we're asked to flush receive queue, directly
1857 * chain it back at the queue without processing it.
1858 */
1859 if (flush)
1860 goto requeue_drop_frag;
1861
1862 retval = ath9k_rx_skb_preprocess(common, hw, hdr, &rs,
1863 rxs, &decrypt_error);
1864 if (retval)
1865 goto requeue_drop_frag;
1866
1867 rxs->mactime = (tsf & ~0xffffffffULL) | rs.rs_tstamp;
1868 if (rs.rs_tstamp > tsf_lower &&
1869 unlikely(rs.rs_tstamp - tsf_lower > 0x10000000))
1870 rxs->mactime -= 0x100000000ULL;
1871
1872 if (rs.rs_tstamp < tsf_lower &&
1873 unlikely(tsf_lower - rs.rs_tstamp > 0x10000000))
1874 rxs->mactime += 0x100000000ULL;
1875
1876 /* Ensure we always have an skb to requeue once we are done
1877 * processing the current buffer's skb */
1878 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1879
1880 /* If there is no memory we ignore the current RX'd frame,
1881 * tell hardware it can give us a new frame using the old
1882 * skb and put it at the tail of the sc->rx.rxbuf list for
1883 * processing. */
1884 if (!requeue_skb)
1885 goto requeue_drop_frag;
1886
1887 /* Unmap the frame */
1888 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1889 common->rx_bufsize,
1890 dma_type);
1891
1892 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1893 if (ah->caps.rx_status_len)
1894 skb_pull(skb, ah->caps.rx_status_len);
1895
1896 if (!rs.rs_more)
1897 ath9k_rx_skb_postprocess(common, hdr_skb, &rs,
1898 rxs, decrypt_error);
1899
1900 /* We will now give hardware our shiny new allocated skb */
1901 bf->bf_mpdu = requeue_skb;
1902 bf->bf_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1903 common->rx_bufsize,
1904 dma_type);
1905 if (unlikely(dma_mapping_error(sc->dev,
1906 bf->bf_buf_addr))) {
1907 dev_kfree_skb_any(requeue_skb);
1908 bf->bf_mpdu = NULL;
1909 bf->bf_buf_addr = 0;
1910 ath_err(common, "dma_mapping_error() on RX\n");
1911 ieee80211_rx(hw, skb);
1912 break;
1913 }
1914
1915 if (rs.rs_more) {
1916 /*
1917 * rs_more indicates chained descriptors which can be
1918 * used to link buffers together for a sort of
1919 * scatter-gather operation.
1920 */
1921 if (sc->rx.frag) {
1922 /* too many fragments - cannot handle frame */
1923 dev_kfree_skb_any(sc->rx.frag);
1924 dev_kfree_skb_any(skb);
1925 skb = NULL;
1926 }
1927 sc->rx.frag = skb;
1928 goto requeue;
1929 }
1930
1931 if (sc->rx.frag) {
1932 int space = skb->len - skb_tailroom(hdr_skb);
1933
1934 sc->rx.frag = NULL;
1935
1936 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1937 dev_kfree_skb(skb);
1938 goto requeue_drop_frag;
1939 }
1940
1941 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1942 skb->len);
1943 dev_kfree_skb_any(skb);
1944 skb = hdr_skb;
1945 }
1946
1947 /*
1948 * change the default rx antenna if rx diversity chooses the
1949 * other antenna 3 times in a row.
1950 */
1951 if (sc->rx.defant != rs.rs_antenna) {
1952 if (++sc->rx.rxotherant >= 3)
1953 ath_setdefantenna(sc, rs.rs_antenna);
1954 } else {
1955 sc->rx.rxotherant = 0;
1956 }
1957
1958 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1959 skb_trim(skb, skb->len - 8);
1960
1961 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1962
1963 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1964 PS_WAIT_FOR_CAB |
1965 PS_WAIT_FOR_PSPOLL_DATA)) ||
1966 ath9k_check_auto_sleep(sc))
1967 ath_rx_ps(sc, skb);
1968 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1969
1970 if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
1971 ath_ant_comb_scan(sc, &rs);
1972
1973 ieee80211_rx(hw, skb);
1974
1975requeue_drop_frag:
1976 if (sc->rx.frag) {
1977 dev_kfree_skb_any(sc->rx.frag);
1978 sc->rx.frag = NULL;
1979 }
1980requeue:
1981 if (edma) {
1982 list_add_tail(&bf->list, &sc->rx.rxbuf);
1983 ath_rx_edma_buf_link(sc, qtype);
1984 } else {
1985 list_move_tail(&bf->list, &sc->rx.rxbuf);
1986 ath_rx_buf_link(sc, bf);
1987 ath9k_hw_rxena(ah);
1988 }
1989 } while (1);
1990
1991 spin_unlock_bh(&sc->rx.rxbuflock);
1992
1993 return 0;
1994}
1/*
2 * Copyright (c) 2008-2011 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#include <linux/dma-mapping.h>
18#include "ath9k.h"
19#include "ar9003_mac.h"
20
21#define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
22
23static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
24{
25 return sc->ps_enabled &&
26 (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
27}
28
29/*
30 * Setup and link descriptors.
31 *
32 * 11N: we can no longer afford to self link the last descriptor.
33 * MAC acknowledges BA status as long as it copies frames to host
34 * buffer (or rx fifo). This can incorrectly acknowledge packets
35 * to a sender if last desc is self-linked.
36 */
37static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf)
38{
39 struct ath_hw *ah = sc->sc_ah;
40 struct ath_common *common = ath9k_hw_common(ah);
41 struct ath_desc *ds;
42 struct sk_buff *skb;
43
44 ds = bf->bf_desc;
45 ds->ds_link = 0; /* link to null */
46 ds->ds_data = bf->bf_buf_addr;
47
48 /* virtual addr of the beginning of the buffer. */
49 skb = bf->bf_mpdu;
50 BUG_ON(skb == NULL);
51 ds->ds_vdata = skb->data;
52
53 /*
54 * setup rx descriptors. The rx_bufsize here tells the hardware
55 * how much data it can DMA to us and that we are prepared
56 * to process
57 */
58 ath9k_hw_setuprxdesc(ah, ds,
59 common->rx_bufsize,
60 0);
61
62 if (sc->rx.rxlink == NULL)
63 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
64 else
65 *sc->rx.rxlink = bf->bf_daddr;
66
67 sc->rx.rxlink = &ds->ds_link;
68}
69
70static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf)
71{
72 if (sc->rx.buf_hold)
73 ath_rx_buf_link(sc, sc->rx.buf_hold);
74
75 sc->rx.buf_hold = bf;
76}
77
78static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
79{
80 /* XXX block beacon interrupts */
81 ath9k_hw_setantenna(sc->sc_ah, antenna);
82 sc->rx.defant = antenna;
83 sc->rx.rxotherant = 0;
84}
85
86static void ath_opmode_init(struct ath_softc *sc)
87{
88 struct ath_hw *ah = sc->sc_ah;
89 struct ath_common *common = ath9k_hw_common(ah);
90
91 u32 rfilt, mfilt[2];
92
93 /* configure rx filter */
94 rfilt = ath_calcrxfilter(sc);
95 ath9k_hw_setrxfilter(ah, rfilt);
96
97 /* configure bssid mask */
98 ath_hw_setbssidmask(common);
99
100 /* configure operational mode */
101 ath9k_hw_setopmode(ah);
102
103 /* calculate and install multicast filter */
104 mfilt[0] = mfilt[1] = ~0;
105 ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
106}
107
108static bool ath_rx_edma_buf_link(struct ath_softc *sc,
109 enum ath9k_rx_qtype qtype)
110{
111 struct ath_hw *ah = sc->sc_ah;
112 struct ath_rx_edma *rx_edma;
113 struct sk_buff *skb;
114 struct ath_rxbuf *bf;
115
116 rx_edma = &sc->rx.rx_edma[qtype];
117 if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
118 return false;
119
120 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
121 list_del_init(&bf->list);
122
123 skb = bf->bf_mpdu;
124
125 memset(skb->data, 0, ah->caps.rx_status_len);
126 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
127 ah->caps.rx_status_len, DMA_TO_DEVICE);
128
129 SKB_CB_ATHBUF(skb) = bf;
130 ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
131 __skb_queue_tail(&rx_edma->rx_fifo, skb);
132
133 return true;
134}
135
136static void ath_rx_addbuffer_edma(struct ath_softc *sc,
137 enum ath9k_rx_qtype qtype)
138{
139 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
140 struct ath_rxbuf *bf, *tbf;
141
142 if (list_empty(&sc->rx.rxbuf)) {
143 ath_dbg(common, QUEUE, "No free rx buf available\n");
144 return;
145 }
146
147 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
148 if (!ath_rx_edma_buf_link(sc, qtype))
149 break;
150
151}
152
153static void ath_rx_remove_buffer(struct ath_softc *sc,
154 enum ath9k_rx_qtype qtype)
155{
156 struct ath_rxbuf *bf;
157 struct ath_rx_edma *rx_edma;
158 struct sk_buff *skb;
159
160 rx_edma = &sc->rx.rx_edma[qtype];
161
162 while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
163 bf = SKB_CB_ATHBUF(skb);
164 BUG_ON(!bf);
165 list_add_tail(&bf->list, &sc->rx.rxbuf);
166 }
167}
168
169static void ath_rx_edma_cleanup(struct ath_softc *sc)
170{
171 struct ath_hw *ah = sc->sc_ah;
172 struct ath_common *common = ath9k_hw_common(ah);
173 struct ath_rxbuf *bf;
174
175 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
176 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
177
178 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
179 if (bf->bf_mpdu) {
180 dma_unmap_single(sc->dev, bf->bf_buf_addr,
181 common->rx_bufsize,
182 DMA_BIDIRECTIONAL);
183 dev_kfree_skb_any(bf->bf_mpdu);
184 bf->bf_buf_addr = 0;
185 bf->bf_mpdu = NULL;
186 }
187 }
188}
189
190static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
191{
192 __skb_queue_head_init(&rx_edma->rx_fifo);
193 rx_edma->rx_fifo_hwsize = size;
194}
195
196static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
197{
198 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
199 struct ath_hw *ah = sc->sc_ah;
200 struct sk_buff *skb;
201 struct ath_rxbuf *bf;
202 int error = 0, i;
203 u32 size;
204
205 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
206 ah->caps.rx_status_len);
207
208 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
209 ah->caps.rx_lp_qdepth);
210 ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
211 ah->caps.rx_hp_qdepth);
212
213 size = sizeof(struct ath_rxbuf) * nbufs;
214 bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
215 if (!bf)
216 return -ENOMEM;
217
218 INIT_LIST_HEAD(&sc->rx.rxbuf);
219
220 for (i = 0; i < nbufs; i++, bf++) {
221 skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
222 if (!skb) {
223 error = -ENOMEM;
224 goto rx_init_fail;
225 }
226
227 memset(skb->data, 0, common->rx_bufsize);
228 bf->bf_mpdu = skb;
229
230 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
231 common->rx_bufsize,
232 DMA_BIDIRECTIONAL);
233 if (unlikely(dma_mapping_error(sc->dev,
234 bf->bf_buf_addr))) {
235 dev_kfree_skb_any(skb);
236 bf->bf_mpdu = NULL;
237 bf->bf_buf_addr = 0;
238 ath_err(common,
239 "dma_mapping_error() on RX init\n");
240 error = -ENOMEM;
241 goto rx_init_fail;
242 }
243
244 list_add_tail(&bf->list, &sc->rx.rxbuf);
245 }
246
247 return 0;
248
249rx_init_fail:
250 ath_rx_edma_cleanup(sc);
251 return error;
252}
253
254static void ath_edma_start_recv(struct ath_softc *sc)
255{
256 ath9k_hw_rxena(sc->sc_ah);
257 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
258 ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
259 ath_opmode_init(sc);
260 ath9k_hw_startpcureceive(sc->sc_ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
261}
262
263static void ath_edma_stop_recv(struct ath_softc *sc)
264{
265 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
266 ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
267}
268
269int ath_rx_init(struct ath_softc *sc, int nbufs)
270{
271 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
272 struct sk_buff *skb;
273 struct ath_rxbuf *bf;
274 int error = 0;
275
276 spin_lock_init(&sc->sc_pcu_lock);
277
278 common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
279 sc->sc_ah->caps.rx_status_len;
280
281 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
282 return ath_rx_edma_init(sc, nbufs);
283
284 ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
285 common->cachelsz, common->rx_bufsize);
286
287 /* Initialize rx descriptors */
288
289 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
290 "rx", nbufs, 1, 0);
291 if (error != 0) {
292 ath_err(common,
293 "failed to allocate rx descriptors: %d\n",
294 error);
295 goto err;
296 }
297
298 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
299 skb = ath_rxbuf_alloc(common, common->rx_bufsize,
300 GFP_KERNEL);
301 if (skb == NULL) {
302 error = -ENOMEM;
303 goto err;
304 }
305
306 bf->bf_mpdu = skb;
307 bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
308 common->rx_bufsize,
309 DMA_FROM_DEVICE);
310 if (unlikely(dma_mapping_error(sc->dev,
311 bf->bf_buf_addr))) {
312 dev_kfree_skb_any(skb);
313 bf->bf_mpdu = NULL;
314 bf->bf_buf_addr = 0;
315 ath_err(common,
316 "dma_mapping_error() on RX init\n");
317 error = -ENOMEM;
318 goto err;
319 }
320 }
321 sc->rx.rxlink = NULL;
322err:
323 if (error)
324 ath_rx_cleanup(sc);
325
326 return error;
327}
328
329void ath_rx_cleanup(struct ath_softc *sc)
330{
331 struct ath_hw *ah = sc->sc_ah;
332 struct ath_common *common = ath9k_hw_common(ah);
333 struct sk_buff *skb;
334 struct ath_rxbuf *bf;
335
336 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
337 ath_rx_edma_cleanup(sc);
338 return;
339 }
340
341 list_for_each_entry(bf, &sc->rx.rxbuf, list) {
342 skb = bf->bf_mpdu;
343 if (skb) {
344 dma_unmap_single(sc->dev, bf->bf_buf_addr,
345 common->rx_bufsize,
346 DMA_FROM_DEVICE);
347 dev_kfree_skb(skb);
348 bf->bf_buf_addr = 0;
349 bf->bf_mpdu = NULL;
350 }
351 }
352}
353
354/*
355 * Calculate the receive filter according to the
356 * operating mode and state:
357 *
358 * o always accept unicast, broadcast, and multicast traffic
359 * o maintain current state of phy error reception (the hal
360 * may enable phy error frames for noise immunity work)
361 * o probe request frames are accepted only when operating in
362 * hostap, adhoc, or monitor modes
363 * o enable promiscuous mode according to the interface state
364 * o accept beacons:
365 * - when operating in adhoc mode so the 802.11 layer creates
366 * node table entries for peers,
367 * - when operating in station mode for collecting rssi data when
368 * the station is otherwise quiet, or
369 * - when operating as a repeater so we see repeater-sta beacons
370 * - when scanning
371 */
372
373u32 ath_calcrxfilter(struct ath_softc *sc)
374{
375 u32 rfilt;
376
377 if (config_enabled(CONFIG_ATH9K_TX99))
378 return 0;
379
380 rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
381 | ATH9K_RX_FILTER_MCAST;
382
383 /* if operating on a DFS channel, enable radar pulse detection */
384 if (sc->hw->conf.radar_enabled)
385 rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
386
387 if (sc->rx.rxfilter & FIF_PROBE_REQ)
388 rfilt |= ATH9K_RX_FILTER_PROBEREQ;
389
390 /*
391 * Set promiscuous mode when FIF_PROMISC_IN_BSS is enabled for station
392 * mode interface or when in monitor mode. AP mode does not need this
393 * since it receives all in-BSS frames anyway.
394 */
395 if (sc->sc_ah->is_monitoring)
396 rfilt |= ATH9K_RX_FILTER_PROM;
397
398 if (sc->rx.rxfilter & FIF_CONTROL)
399 rfilt |= ATH9K_RX_FILTER_CONTROL;
400
401 if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
402 (sc->nvifs <= 1) &&
403 !(sc->rx.rxfilter & FIF_BCN_PRBRESP_PROMISC))
404 rfilt |= ATH9K_RX_FILTER_MYBEACON;
405 else
406 rfilt |= ATH9K_RX_FILTER_BEACON;
407
408 if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
409 (sc->rx.rxfilter & FIF_PSPOLL))
410 rfilt |= ATH9K_RX_FILTER_PSPOLL;
411
412 if (conf_is_ht(&sc->hw->conf))
413 rfilt |= ATH9K_RX_FILTER_COMP_BAR;
414
415 if (sc->nvifs > 1 || (sc->rx.rxfilter & FIF_OTHER_BSS)) {
416 /* This is needed for older chips */
417 if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
418 rfilt |= ATH9K_RX_FILTER_PROM;
419 rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
420 }
421
422 if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah))
423 rfilt |= ATH9K_RX_FILTER_4ADDRESS;
424
425 return rfilt;
426
427}
428
429int ath_startrecv(struct ath_softc *sc)
430{
431 struct ath_hw *ah = sc->sc_ah;
432 struct ath_rxbuf *bf, *tbf;
433
434 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
435 ath_edma_start_recv(sc);
436 return 0;
437 }
438
439 if (list_empty(&sc->rx.rxbuf))
440 goto start_recv;
441
442 sc->rx.buf_hold = NULL;
443 sc->rx.rxlink = NULL;
444 list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
445 ath_rx_buf_link(sc, bf);
446 }
447
448 /* We could have deleted elements so the list may be empty now */
449 if (list_empty(&sc->rx.rxbuf))
450 goto start_recv;
451
452 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
453 ath9k_hw_putrxbuf(ah, bf->bf_daddr);
454 ath9k_hw_rxena(ah);
455
456start_recv:
457 ath_opmode_init(sc);
458 ath9k_hw_startpcureceive(ah, !!(sc->hw->conf.flags & IEEE80211_CONF_OFFCHANNEL));
459
460 return 0;
461}
462
463static void ath_flushrecv(struct ath_softc *sc)
464{
465 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
466 ath_rx_tasklet(sc, 1, true);
467 ath_rx_tasklet(sc, 1, false);
468}
469
470bool ath_stoprecv(struct ath_softc *sc)
471{
472 struct ath_hw *ah = sc->sc_ah;
473 bool stopped, reset = false;
474
475 ath9k_hw_abortpcurecv(ah);
476 ath9k_hw_setrxfilter(ah, 0);
477 stopped = ath9k_hw_stopdmarecv(ah, &reset);
478
479 ath_flushrecv(sc);
480
481 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
482 ath_edma_stop_recv(sc);
483 else
484 sc->rx.rxlink = NULL;
485
486 if (!(ah->ah_flags & AH_UNPLUGGED) &&
487 unlikely(!stopped)) {
488 ath_err(ath9k_hw_common(sc->sc_ah),
489 "Could not stop RX, we could be "
490 "confusing the DMA engine when we start RX up\n");
491 ATH_DBG_WARN_ON_ONCE(!stopped);
492 }
493 return stopped && !reset;
494}
495
496static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
497{
498 /* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
499 struct ieee80211_mgmt *mgmt;
500 u8 *pos, *end, id, elen;
501 struct ieee80211_tim_ie *tim;
502
503 mgmt = (struct ieee80211_mgmt *)skb->data;
504 pos = mgmt->u.beacon.variable;
505 end = skb->data + skb->len;
506
507 while (pos + 2 < end) {
508 id = *pos++;
509 elen = *pos++;
510 if (pos + elen > end)
511 break;
512
513 if (id == WLAN_EID_TIM) {
514 if (elen < sizeof(*tim))
515 break;
516 tim = (struct ieee80211_tim_ie *) pos;
517 if (tim->dtim_count != 0)
518 break;
519 return tim->bitmap_ctrl & 0x01;
520 }
521
522 pos += elen;
523 }
524
525 return false;
526}
527
528static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
529{
530 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
531
532 if (skb->len < 24 + 8 + 2 + 2)
533 return;
534
535 sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
536
537 if (sc->ps_flags & PS_BEACON_SYNC) {
538 sc->ps_flags &= ~PS_BEACON_SYNC;
539 ath_dbg(common, PS,
540 "Reconfigure beacon timers based on synchronized timestamp\n");
541 ath9k_set_beacon(sc);
542 }
543
544 if (ath_beacon_dtim_pending_cab(skb)) {
545 /*
546 * Remain awake waiting for buffered broadcast/multicast
547 * frames. If the last broadcast/multicast frame is not
548 * received properly, the next beacon frame will work as
549 * a backup trigger for returning into NETWORK SLEEP state,
550 * so we are waiting for it as well.
551 */
552 ath_dbg(common, PS,
553 "Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
554 sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
555 return;
556 }
557
558 if (sc->ps_flags & PS_WAIT_FOR_CAB) {
559 /*
560 * This can happen if a broadcast frame is dropped or the AP
561 * fails to send a frame indicating that all CAB frames have
562 * been delivered.
563 */
564 sc->ps_flags &= ~PS_WAIT_FOR_CAB;
565 ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
566 }
567}
568
569static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
570{
571 struct ieee80211_hdr *hdr;
572 struct ath_common *common = ath9k_hw_common(sc->sc_ah);
573
574 hdr = (struct ieee80211_hdr *)skb->data;
575
576 /* Process Beacon and CAB receive in PS state */
577 if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
578 && mybeacon) {
579 ath_rx_ps_beacon(sc, skb);
580 } else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
581 (ieee80211_is_data(hdr->frame_control) ||
582 ieee80211_is_action(hdr->frame_control)) &&
583 is_multicast_ether_addr(hdr->addr1) &&
584 !ieee80211_has_moredata(hdr->frame_control)) {
585 /*
586 * No more broadcast/multicast frames to be received at this
587 * point.
588 */
589 sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
590 ath_dbg(common, PS,
591 "All PS CAB frames received, back to sleep\n");
592 } else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
593 !is_multicast_ether_addr(hdr->addr1) &&
594 !ieee80211_has_morefrags(hdr->frame_control)) {
595 sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
596 ath_dbg(common, PS,
597 "Going back to sleep after having received PS-Poll data (0x%lx)\n",
598 sc->ps_flags & (PS_WAIT_FOR_BEACON |
599 PS_WAIT_FOR_CAB |
600 PS_WAIT_FOR_PSPOLL_DATA |
601 PS_WAIT_FOR_TX_ACK));
602 }
603}
604
605static bool ath_edma_get_buffers(struct ath_softc *sc,
606 enum ath9k_rx_qtype qtype,
607 struct ath_rx_status *rs,
608 struct ath_rxbuf **dest)
609{
610 struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
611 struct ath_hw *ah = sc->sc_ah;
612 struct ath_common *common = ath9k_hw_common(ah);
613 struct sk_buff *skb;
614 struct ath_rxbuf *bf;
615 int ret;
616
617 skb = skb_peek(&rx_edma->rx_fifo);
618 if (!skb)
619 return false;
620
621 bf = SKB_CB_ATHBUF(skb);
622 BUG_ON(!bf);
623
624 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
625 common->rx_bufsize, DMA_FROM_DEVICE);
626
627 ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
628 if (ret == -EINPROGRESS) {
629 /*let device gain the buffer again*/
630 dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
631 common->rx_bufsize, DMA_FROM_DEVICE);
632 return false;
633 }
634
635 __skb_unlink(skb, &rx_edma->rx_fifo);
636 if (ret == -EINVAL) {
637 /* corrupt descriptor, skip this one and the following one */
638 list_add_tail(&bf->list, &sc->rx.rxbuf);
639 ath_rx_edma_buf_link(sc, qtype);
640
641 skb = skb_peek(&rx_edma->rx_fifo);
642 if (skb) {
643 bf = SKB_CB_ATHBUF(skb);
644 BUG_ON(!bf);
645
646 __skb_unlink(skb, &rx_edma->rx_fifo);
647 list_add_tail(&bf->list, &sc->rx.rxbuf);
648 ath_rx_edma_buf_link(sc, qtype);
649 }
650
651 bf = NULL;
652 }
653
654 *dest = bf;
655 return true;
656}
657
658static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
659 struct ath_rx_status *rs,
660 enum ath9k_rx_qtype qtype)
661{
662 struct ath_rxbuf *bf = NULL;
663
664 while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
665 if (!bf)
666 continue;
667
668 return bf;
669 }
670 return NULL;
671}
672
673static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc,
674 struct ath_rx_status *rs)
675{
676 struct ath_hw *ah = sc->sc_ah;
677 struct ath_common *common = ath9k_hw_common(ah);
678 struct ath_desc *ds;
679 struct ath_rxbuf *bf;
680 int ret;
681
682 if (list_empty(&sc->rx.rxbuf)) {
683 sc->rx.rxlink = NULL;
684 return NULL;
685 }
686
687 bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
688 if (bf == sc->rx.buf_hold)
689 return NULL;
690
691 ds = bf->bf_desc;
692
693 /*
694 * Must provide the virtual address of the current
695 * descriptor, the physical address, and the virtual
696 * address of the next descriptor in the h/w chain.
697 * This allows the HAL to look ahead to see if the
698 * hardware is done with a descriptor by checking the
699 * done bit in the following descriptor and the address
700 * of the current descriptor the DMA engine is working
701 * on. All this is necessary because of our use of
702 * a self-linked list to avoid rx overruns.
703 */
704 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
705 if (ret == -EINPROGRESS) {
706 struct ath_rx_status trs;
707 struct ath_rxbuf *tbf;
708 struct ath_desc *tds;
709
710 memset(&trs, 0, sizeof(trs));
711 if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
712 sc->rx.rxlink = NULL;
713 return NULL;
714 }
715
716 tbf = list_entry(bf->list.next, struct ath_rxbuf, list);
717
718 /*
719 * On some hardware the descriptor status words could
720 * get corrupted, including the done bit. Because of
721 * this, check if the next descriptor's done bit is
722 * set or not.
723 *
724 * If the next descriptor's done bit is set, the current
725 * descriptor has been corrupted. Force s/w to discard
726 * this descriptor and continue...
727 */
728
729 tds = tbf->bf_desc;
730 ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
731 if (ret == -EINPROGRESS)
732 return NULL;
733
734 /*
735 * Re-check previous descriptor, in case it has been filled
736 * in the mean time.
737 */
738 ret = ath9k_hw_rxprocdesc(ah, ds, rs);
739 if (ret == -EINPROGRESS) {
740 /*
741 * mark descriptor as zero-length and set the 'more'
742 * flag to ensure that both buffers get discarded
743 */
744 rs->rs_datalen = 0;
745 rs->rs_more = true;
746 }
747 }
748
749 list_del(&bf->list);
750 if (!bf->bf_mpdu)
751 return bf;
752
753 /*
754 * Synchronize the DMA transfer with CPU before
755 * 1. accessing the frame
756 * 2. requeueing the same buffer to h/w
757 */
758 dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
759 common->rx_bufsize,
760 DMA_FROM_DEVICE);
761
762 return bf;
763}
764
765static void ath9k_process_tsf(struct ath_rx_status *rs,
766 struct ieee80211_rx_status *rxs,
767 u64 tsf)
768{
769 u32 tsf_lower = tsf & 0xffffffff;
770
771 rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp;
772 if (rs->rs_tstamp > tsf_lower &&
773 unlikely(rs->rs_tstamp - tsf_lower > 0x10000000))
774 rxs->mactime -= 0x100000000ULL;
775
776 if (rs->rs_tstamp < tsf_lower &&
777 unlikely(tsf_lower - rs->rs_tstamp > 0x10000000))
778 rxs->mactime += 0x100000000ULL;
779}
780
781/*
782 * For Decrypt or Demic errors, we only mark packet status here and always push
783 * up the frame up to let mac80211 handle the actual error case, be it no
784 * decryption key or real decryption error. This let us keep statistics there.
785 */
786static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
787 struct sk_buff *skb,
788 struct ath_rx_status *rx_stats,
789 struct ieee80211_rx_status *rx_status,
790 bool *decrypt_error, u64 tsf)
791{
792 struct ieee80211_hw *hw = sc->hw;
793 struct ath_hw *ah = sc->sc_ah;
794 struct ath_common *common = ath9k_hw_common(ah);
795 struct ieee80211_hdr *hdr;
796 bool discard_current = sc->rx.discard_next;
797
798 /*
799 * Discard corrupt descriptors which are marked in
800 * ath_get_next_rx_buf().
801 */
802 if (discard_current)
803 goto corrupt;
804
805 sc->rx.discard_next = false;
806
807 /*
808 * Discard zero-length packets.
809 */
810 if (!rx_stats->rs_datalen) {
811 RX_STAT_INC(rx_len_err);
812 goto corrupt;
813 }
814
815 /*
816 * rs_status follows rs_datalen so if rs_datalen is too large
817 * we can take a hint that hardware corrupted it, so ignore
818 * those frames.
819 */
820 if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) {
821 RX_STAT_INC(rx_len_err);
822 goto corrupt;
823 }
824
825 /* Only use status info from the last fragment */
826 if (rx_stats->rs_more)
827 return 0;
828
829 /*
830 * Return immediately if the RX descriptor has been marked
831 * as corrupt based on the various error bits.
832 *
833 * This is different from the other corrupt descriptor
834 * condition handled above.
835 */
836 if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC)
837 goto corrupt;
838
839 hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len);
840
841 ath9k_process_tsf(rx_stats, rx_status, tsf);
842 ath_debug_stat_rx(sc, rx_stats);
843
844 /*
845 * Process PHY errors and return so that the packet
846 * can be dropped.
847 */
848 if (rx_stats->rs_status & ATH9K_RXERR_PHY) {
849 ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime);
850 if (ath_process_fft(sc, hdr, rx_stats, rx_status->mactime))
851 RX_STAT_INC(rx_spectral);
852
853 return -EINVAL;
854 }
855
856 /*
857 * everything but the rate is checked here, the rate check is done
858 * separately to avoid doing two lookups for a rate for each frame.
859 */
860 if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error, sc->rx.rxfilter))
861 return -EINVAL;
862
863 if (ath_is_mybeacon(common, hdr)) {
864 RX_STAT_INC(rx_beacons);
865 rx_stats->is_mybeacon = true;
866 }
867
868 /*
869 * This shouldn't happen, but have a safety check anyway.
870 */
871 if (WARN_ON(!ah->curchan))
872 return -EINVAL;
873
874 if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) {
875 /*
876 * No valid hardware bitrate found -- we should not get here
877 * because hardware has already validated this frame as OK.
878 */
879 ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
880 rx_stats->rs_rate);
881 RX_STAT_INC(rx_rate_err);
882 return -EINVAL;
883 }
884
885 ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status);
886
887 rx_status->band = ah->curchan->chan->band;
888 rx_status->freq = ah->curchan->chan->center_freq;
889 rx_status->antenna = rx_stats->rs_antenna;
890 rx_status->flag |= RX_FLAG_MACTIME_END;
891
892#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
893 if (ieee80211_is_data_present(hdr->frame_control) &&
894 !ieee80211_is_qos_nullfunc(hdr->frame_control))
895 sc->rx.num_pkts++;
896#endif
897
898 return 0;
899
900corrupt:
901 sc->rx.discard_next = rx_stats->rs_more;
902 return -EINVAL;
903}
904
905/*
906 * Run the LNA combining algorithm only in these cases:
907 *
908 * Standalone WLAN cards with both LNA/Antenna diversity
909 * enabled in the EEPROM.
910 *
911 * WLAN+BT cards which are in the supported card list
912 * in ath_pci_id_table and the user has loaded the
913 * driver with "bt_ant_diversity" set to true.
914 */
915static void ath9k_antenna_check(struct ath_softc *sc,
916 struct ath_rx_status *rs)
917{
918 struct ath_hw *ah = sc->sc_ah;
919 struct ath9k_hw_capabilities *pCap = &ah->caps;
920 struct ath_common *common = ath9k_hw_common(ah);
921
922 if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
923 return;
924
925 /*
926 * Change the default rx antenna if rx diversity
927 * chooses the other antenna 3 times in a row.
928 */
929 if (sc->rx.defant != rs->rs_antenna) {
930 if (++sc->rx.rxotherant >= 3)
931 ath_setdefantenna(sc, rs->rs_antenna);
932 } else {
933 sc->rx.rxotherant = 0;
934 }
935
936 if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) {
937 if (common->bt_ant_diversity)
938 ath_ant_comb_scan(sc, rs);
939 } else {
940 ath_ant_comb_scan(sc, rs);
941 }
942}
943
944static void ath9k_apply_ampdu_details(struct ath_softc *sc,
945 struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
946{
947 if (rs->rs_isaggr) {
948 rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
949
950 rxs->ampdu_reference = sc->rx.ampdu_ref;
951
952 if (!rs->rs_moreaggr) {
953 rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
954 sc->rx.ampdu_ref++;
955 }
956
957 if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
958 rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
959 }
960}
961
962int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
963{
964 struct ath_rxbuf *bf;
965 struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
966 struct ieee80211_rx_status *rxs;
967 struct ath_hw *ah = sc->sc_ah;
968 struct ath_common *common = ath9k_hw_common(ah);
969 struct ieee80211_hw *hw = sc->hw;
970 int retval;
971 struct ath_rx_status rs;
972 enum ath9k_rx_qtype qtype;
973 bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
974 int dma_type;
975 u64 tsf = 0;
976 unsigned long flags;
977 dma_addr_t new_buf_addr;
978 unsigned int budget = 512;
979
980 if (edma)
981 dma_type = DMA_BIDIRECTIONAL;
982 else
983 dma_type = DMA_FROM_DEVICE;
984
985 qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
986
987 tsf = ath9k_hw_gettsf64(ah);
988
989 do {
990 bool decrypt_error = false;
991
992 memset(&rs, 0, sizeof(rs));
993 if (edma)
994 bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
995 else
996 bf = ath_get_next_rx_buf(sc, &rs);
997
998 if (!bf)
999 break;
1000
1001 skb = bf->bf_mpdu;
1002 if (!skb)
1003 continue;
1004
1005 /*
1006 * Take frame header from the first fragment and RX status from
1007 * the last one.
1008 */
1009 if (sc->rx.frag)
1010 hdr_skb = sc->rx.frag;
1011 else
1012 hdr_skb = skb;
1013
1014 rxs = IEEE80211_SKB_RXCB(hdr_skb);
1015 memset(rxs, 0, sizeof(struct ieee80211_rx_status));
1016
1017 retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs,
1018 &decrypt_error, tsf);
1019 if (retval)
1020 goto requeue_drop_frag;
1021
1022 /* Ensure we always have an skb to requeue once we are done
1023 * processing the current buffer's skb */
1024 requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
1025
1026 /* If there is no memory we ignore the current RX'd frame,
1027 * tell hardware it can give us a new frame using the old
1028 * skb and put it at the tail of the sc->rx.rxbuf list for
1029 * processing. */
1030 if (!requeue_skb) {
1031 RX_STAT_INC(rx_oom_err);
1032 goto requeue_drop_frag;
1033 }
1034
1035 /* We will now give hardware our shiny new allocated skb */
1036 new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
1037 common->rx_bufsize, dma_type);
1038 if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
1039 dev_kfree_skb_any(requeue_skb);
1040 goto requeue_drop_frag;
1041 }
1042
1043 /* Unmap the frame */
1044 dma_unmap_single(sc->dev, bf->bf_buf_addr,
1045 common->rx_bufsize, dma_type);
1046
1047 bf->bf_mpdu = requeue_skb;
1048 bf->bf_buf_addr = new_buf_addr;
1049
1050 skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
1051 if (ah->caps.rx_status_len)
1052 skb_pull(skb, ah->caps.rx_status_len);
1053
1054 if (!rs.rs_more)
1055 ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs,
1056 rxs, decrypt_error);
1057
1058 if (rs.rs_more) {
1059 RX_STAT_INC(rx_frags);
1060 /*
1061 * rs_more indicates chained descriptors which can be
1062 * used to link buffers together for a sort of
1063 * scatter-gather operation.
1064 */
1065 if (sc->rx.frag) {
1066 /* too many fragments - cannot handle frame */
1067 dev_kfree_skb_any(sc->rx.frag);
1068 dev_kfree_skb_any(skb);
1069 RX_STAT_INC(rx_too_many_frags_err);
1070 skb = NULL;
1071 }
1072 sc->rx.frag = skb;
1073 goto requeue;
1074 }
1075
1076 if (sc->rx.frag) {
1077 int space = skb->len - skb_tailroom(hdr_skb);
1078
1079 if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
1080 dev_kfree_skb(skb);
1081 RX_STAT_INC(rx_oom_err);
1082 goto requeue_drop_frag;
1083 }
1084
1085 sc->rx.frag = NULL;
1086
1087 skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
1088 skb->len);
1089 dev_kfree_skb_any(skb);
1090 skb = hdr_skb;
1091 }
1092
1093 if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
1094 skb_trim(skb, skb->len - 8);
1095
1096 spin_lock_irqsave(&sc->sc_pm_lock, flags);
1097 if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
1098 PS_WAIT_FOR_CAB |
1099 PS_WAIT_FOR_PSPOLL_DATA)) ||
1100 ath9k_check_auto_sleep(sc))
1101 ath_rx_ps(sc, skb, rs.is_mybeacon);
1102 spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
1103
1104 ath9k_antenna_check(sc, &rs);
1105 ath9k_apply_ampdu_details(sc, &rs, rxs);
1106 ath_debug_rate_stats(sc, &rs, skb);
1107
1108 ieee80211_rx(hw, skb);
1109
1110requeue_drop_frag:
1111 if (sc->rx.frag) {
1112 dev_kfree_skb_any(sc->rx.frag);
1113 sc->rx.frag = NULL;
1114 }
1115requeue:
1116 list_add_tail(&bf->list, &sc->rx.rxbuf);
1117
1118 if (edma) {
1119 ath_rx_edma_buf_link(sc, qtype);
1120 } else {
1121 ath_rx_buf_relink(sc, bf);
1122 if (!flush)
1123 ath9k_hw_rxena(ah);
1124 }
1125
1126 if (!budget--)
1127 break;
1128 } while (1);
1129
1130 if (!(ah->imask & ATH9K_INT_RXEOL)) {
1131 ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
1132 ath9k_hw_set_interrupts(ah);
1133 }
1134
1135 return 0;
1136}