1/*
  2 * ChromeOS EC multi-function device (SPI)
  3 *
  4 * Copyright (C) 2012 Google, Inc
  5 *
  6 * This software is licensed under the terms of the GNU General Public
  7 * License version 2, as published by the Free Software Foundation, and
  8 * may be copied, distributed, and modified under those terms.
  9 *
 10 * This program is distributed in the hope that it will be useful,
 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 13 * GNU General Public License for more details.
 14 */
 15
 16#include <linux/delay.h>
 17#include <linux/kernel.h>
 18#include <linux/module.h>
 19#include <linux/mfd/cros_ec.h>
 20#include <linux/mfd/cros_ec_commands.h>
 21#include <linux/of.h>
 22#include <linux/platform_device.h>
 23#include <linux/slab.h>
 24#include <linux/spi/spi.h>
 25
 26
 27/* The header byte, which follows the preamble */
 28#define EC_MSG_HEADER			0xec
 29
 30/*
 31 * Number of EC preamble bytes we read at a time. Since it takes
 32 * about 400-500us for the EC to respond there is not a lot of
 33 * point in tuning this. If the EC could respond faster then
 34 * we could increase this so that might expect the preamble and
 35 * message to occur in a single transaction. However, the maximum
 36 * SPI transfer size is 256 bytes, so at 5MHz we need a response
 37 * time of perhaps <320us (200 bytes / 1600 bits).
 38 */
 39#define EC_MSG_PREAMBLE_COUNT		32
 40
 41/*
 42  * We must get a response from the EC in 5ms. This is a very long
 43  * time, but the flash write command can take 2-3ms. The EC command
 44  * processing is currently not very fast (about 500us). We could
 45  * look at speeding this up and making the flash write command a
 46  * 'slow' command, requiring a GET_STATUS wait loop, like flash
 47  * erase.
 48  */
 49#define EC_MSG_DEADLINE_MS		5
 50
 51/*
 52  * Time between raising the SPI chip select (for the end of a
 53  * transaction) and dropping it again (for the next transaction).
 54  * If we go too fast, the EC will miss the transaction. We know that we
 55  * need at least 70 us with the 16 MHz STM32 EC, so go with 200 us to be
 56  * safe.
 57  */
 58#define EC_SPI_RECOVERY_TIME_NS	(200 * 1000)
 59
 60/**
 61 * struct cros_ec_spi - information about a SPI-connected EC
 62 *
 63 * @spi: SPI device we are connected to
 64 * @last_transfer_ns: time that we last finished a transfer, or 0 if there
 65 *	if no record
 66 * @end_of_msg_delay: used to set the delay_usecs on the spi_transfer that
 67 *      is sent when we want to turn off CS at the end of a transaction.
 68 */
 69struct cros_ec_spi {
 70	struct spi_device *spi;
 71	s64 last_transfer_ns;
 72	unsigned int end_of_msg_delay;
 73};
 74
 75static void debug_packet(struct device *dev, const char *name, u8 *ptr,
 76			  int len)
 77{
 78#ifdef DEBUG
 79	int i;
 80
 81	dev_dbg(dev, "%s: ", name);
 82	for (i = 0; i < len; i++)
 83		pr_cont(" %02x", ptr[i]);
 84
 85	pr_cont("\n");
 86#endif
 87}
 88
 89/**
 90 * cros_ec_spi_receive_response - Receive a response from the EC.
 91 *
 92 * This function has two phases: reading the preamble bytes (since if we read
 93 * data from the EC before it is ready to send, we just get preamble) and
 94 * reading the actual message.
 95 *
 96 * The received data is placed into ec_dev->din.
 97 *
 98 * @ec_dev: ChromeOS EC device
 99 * @need_len: Number of message bytes we need to read
100 */
101static int cros_ec_spi_receive_response(struct cros_ec_device *ec_dev,
102					int need_len)
103{
104	struct cros_ec_spi *ec_spi = ec_dev->priv;
105	struct spi_transfer trans;
106	struct spi_message msg;
107	u8 *ptr, *end;
108	int ret;
109	unsigned long deadline;
110	int todo;
111
112	/* Receive data until we see the header byte */
113	deadline = jiffies + msecs_to_jiffies(EC_MSG_DEADLINE_MS);
114	do {
115		memset(&trans, 0, sizeof(trans));
116		trans.cs_change = 1;
117		trans.rx_buf = ptr = ec_dev->din;
118		trans.len = EC_MSG_PREAMBLE_COUNT;
119
120		spi_message_init(&msg);
121		spi_message_add_tail(&trans, &msg);
122		ret = spi_sync(ec_spi->spi, &msg);
123		if (ret < 0) {
124			dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
125			return ret;
126		}
127
128		for (end = ptr + EC_MSG_PREAMBLE_COUNT; ptr != end; ptr++) {
129			if (*ptr == EC_MSG_HEADER) {
130				dev_dbg(ec_dev->dev, "msg found at %zd\n",
131					ptr - ec_dev->din);
132				break;
133			}
134		}
135
136		if (time_after(jiffies, deadline)) {
137			dev_warn(ec_dev->dev, "EC failed to respond in time\n");
138			return -ETIMEDOUT;
139		}
140	} while (ptr == end);
141
142	/*
143	 * ptr now points to the header byte. Copy any valid data to the
144	 * start of our buffer
145	 */
146	todo = end - ++ptr;
147	BUG_ON(todo < 0 || todo > ec_dev->din_size);
148	todo = min(todo, need_len);
149	memmove(ec_dev->din, ptr, todo);
150	ptr = ec_dev->din + todo;
151	dev_dbg(ec_dev->dev, "need %d, got %d bytes from preamble\n",
152		 need_len, todo);
153	need_len -= todo;
154
155	/* Receive data until we have it all */
156	while (need_len > 0) {
157		/*
158		 * We can't support transfers larger than the SPI FIFO size
159		 * unless we have DMA. We don't have DMA on the ISP SPI ports
160		 * for Exynos. We need a way of asking SPI driver for
161		 * maximum-supported transfer size.
162		 */
163		todo = min(need_len, 256);
164		dev_dbg(ec_dev->dev, "loop, todo=%d, need_len=%d, ptr=%zd\n",
165			todo, need_len, ptr - ec_dev->din);
166
167		memset(&trans, 0, sizeof(trans));
168		trans.cs_change = 1;
169		trans.rx_buf = ptr;
170		trans.len = todo;
171		spi_message_init(&msg);
172		spi_message_add_tail(&trans, &msg);
173
174		/* send command to EC and read answer */
175		BUG_ON((u8 *)trans.rx_buf - ec_dev->din + todo >
176				ec_dev->din_size);
177		ret = spi_sync(ec_spi->spi, &msg);
178		if (ret < 0) {
179			dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
180			return ret;
181		}
182
183		debug_packet(ec_dev->dev, "interim", ptr, todo);
184		ptr += todo;
185		need_len -= todo;
186	}
187
188	dev_dbg(ec_dev->dev, "loop done, ptr=%zd\n", ptr - ec_dev->din);
189
190	return 0;
191}
192
193/**
194 * cros_ec_command_spi_xfer - Transfer a message over SPI and receive the reply
195 *
196 * @ec_dev: ChromeOS EC device
197 * @ec_msg: Message to transfer
198 */
199static int cros_ec_command_spi_xfer(struct cros_ec_device *ec_dev,
200				    struct cros_ec_msg *ec_msg)
201{
202	struct cros_ec_spi *ec_spi = ec_dev->priv;
203	struct spi_transfer trans;
204	struct spi_message msg;
205	int i, len;
206	u8 *ptr;
207	int sum;
208	int ret = 0, final_ret;
209	struct timespec ts;
210
211	len = cros_ec_prepare_tx(ec_dev, ec_msg);
212	dev_dbg(ec_dev->dev, "prepared, len=%d\n", len);
213
214	/* If it's too soon to do another transaction, wait */
215	if (ec_spi->last_transfer_ns) {
216		struct timespec ts;
217		unsigned long delay;	/* The delay completed so far */
218
219		ktime_get_ts(&ts);
220		delay = timespec_to_ns(&ts) - ec_spi->last_transfer_ns;
221		if (delay < EC_SPI_RECOVERY_TIME_NS)
222			ndelay(delay);
223	}
224
225	/* Transmit phase - send our message */
226	debug_packet(ec_dev->dev, "out", ec_dev->dout, len);
227	memset(&trans, 0, sizeof(trans));
228	trans.tx_buf = ec_dev->dout;
229	trans.len = len;
230	trans.cs_change = 1;
231	spi_message_init(&msg);
232	spi_message_add_tail(&trans, &msg);
233	ret = spi_sync(ec_spi->spi, &msg);
234
235	/* Get the response */
236	if (!ret) {
237		ret = cros_ec_spi_receive_response(ec_dev,
238				ec_msg->in_len + EC_MSG_TX_PROTO_BYTES);
239	} else {
240		dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
241	}
242
243	/* turn off CS */
244	spi_message_init(&msg);
245
246	if (ec_spi->end_of_msg_delay) {
247		/*
248		 * Add delay for last transaction, to ensure the rising edge
249		 * doesn't come too soon after the end of the data.
250		 */
251		memset(&trans, 0, sizeof(trans));
252		trans.delay_usecs = ec_spi->end_of_msg_delay;
253		spi_message_add_tail(&trans, &msg);
254	}
255
256	final_ret = spi_sync(ec_spi->spi, &msg);
257	ktime_get_ts(&ts);
258	ec_spi->last_transfer_ns = timespec_to_ns(&ts);
259	if (!ret)
260		ret = final_ret;
261	if (ret < 0) {
262		dev_err(ec_dev->dev, "spi transfer failed: %d\n", ret);
263		return ret;
264	}
265
266	/* check response error code */
267	ptr = ec_dev->din;
268	if (ptr[0]) {
269		dev_warn(ec_dev->dev, "command 0x%02x returned an error %d\n",
270			 ec_msg->cmd, ptr[0]);
271		debug_packet(ec_dev->dev, "in_err", ptr, len);
272		return -EINVAL;
273	}
274	len = ptr[1];
275	sum = ptr[0] + ptr[1];
276	if (len > ec_msg->in_len) {
277		dev_err(ec_dev->dev, "packet too long (%d bytes, expected %d)",
278			len, ec_msg->in_len);
279		return -ENOSPC;
280	}
281
282	/* copy response packet payload and compute checksum */
283	for (i = 0; i < len; i++) {
284		sum += ptr[i + 2];
285		if (ec_msg->in_len)
286			ec_msg->in_buf[i] = ptr[i + 2];
287	}
288	sum &= 0xff;
289
290	debug_packet(ec_dev->dev, "in", ptr, len + 3);
291
292	if (sum != ptr[len + 2]) {
293		dev_err(ec_dev->dev,
294			"bad packet checksum, expected %02x, got %02x\n",
295			sum, ptr[len + 2]);
296		return -EBADMSG;
297	}
298
299	return 0;
300}
301
302static void cros_ec_spi_dt_probe(struct cros_ec_spi *ec_spi, struct device *dev)
303{
304	struct device_node *np = dev->of_node;
305	u32 val;
306	int ret;
307
308	ret = of_property_read_u32(np, "google,cros-ec-spi-msg-delay", &val);
309	if (!ret)
310		ec_spi->end_of_msg_delay = val;
311}
312
313static int cros_ec_spi_probe(struct spi_device *spi)
314{
315	struct device *dev = &spi->dev;
316	struct cros_ec_device *ec_dev;
317	struct cros_ec_spi *ec_spi;
318	int err;
319
320	spi->bits_per_word = 8;
321	spi->mode = SPI_MODE_0;
322	err = spi_setup(spi);
323	if (err < 0)
324		return err;
325
326	ec_spi = devm_kzalloc(dev, sizeof(*ec_spi), GFP_KERNEL);
327	if (ec_spi == NULL)
328		return -ENOMEM;
329	ec_spi->spi = spi;
330	ec_dev = devm_kzalloc(dev, sizeof(*ec_dev), GFP_KERNEL);
331	if (!ec_dev)
332		return -ENOMEM;
333
334	/* Check for any DT properties */
335	cros_ec_spi_dt_probe(ec_spi, dev);
336
337	spi_set_drvdata(spi, ec_dev);
338	ec_dev->name = "SPI";
339	ec_dev->dev = dev;
340	ec_dev->priv = ec_spi;
341	ec_dev->irq = spi->irq;
342	ec_dev->command_xfer = cros_ec_command_spi_xfer;
343	ec_dev->ec_name = ec_spi->spi->modalias;
344	ec_dev->phys_name = dev_name(&ec_spi->spi->dev);
345	ec_dev->parent = &ec_spi->spi->dev;
346	ec_dev->din_size = EC_MSG_BYTES + EC_MSG_PREAMBLE_COUNT;
347	ec_dev->dout_size = EC_MSG_BYTES;
348
349	err = cros_ec_register(ec_dev);
350	if (err) {
351		dev_err(dev, "cannot register EC\n");
352		return err;
353	}
354
355	return 0;
356}
357
358static int cros_ec_spi_remove(struct spi_device *spi)
359{
360	struct cros_ec_device *ec_dev;
361
362	ec_dev = spi_get_drvdata(spi);
363	cros_ec_remove(ec_dev);
364
365	return 0;
366}
367
368#ifdef CONFIG_PM_SLEEP
369static int cros_ec_spi_suspend(struct device *dev)
370{
371	struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
372
373	return cros_ec_suspend(ec_dev);
374}
375
376static int cros_ec_spi_resume(struct device *dev)
377{
378	struct cros_ec_device *ec_dev = dev_get_drvdata(dev);
379
380	return cros_ec_resume(ec_dev);
381}
382#endif
383
384static SIMPLE_DEV_PM_OPS(cros_ec_spi_pm_ops, cros_ec_spi_suspend,
385			 cros_ec_spi_resume);
386
387static const struct spi_device_id cros_ec_spi_id[] = {
388	{ "cros-ec-spi", 0 },
389	{ }
390};
391MODULE_DEVICE_TABLE(spi, cros_ec_spi_id);
392
393static struct spi_driver cros_ec_driver_spi = {
394	.driver	= {
395		.name	= "cros-ec-spi",
396		.owner	= THIS_MODULE,
397		.pm	= &cros_ec_spi_pm_ops,
398	},
399	.probe		= cros_ec_spi_probe,
400	.remove		= cros_ec_spi_remove,
401	.id_table	= cros_ec_spi_id,
402};
403
404module_spi_driver(cros_ec_driver_spi);
405
406MODULE_LICENSE("GPL v2");
407MODULE_DESCRIPTION("ChromeOS EC multi function device (SPI)");