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1/*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Alex Deucher
23 */
24#ifndef CIK_H
25#define CIK_H
26
27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
29
30#define CIK_RB_BITMAP_WIDTH_PER_SH 2
31#define HAWAII_RB_BITMAP_WIDTH_PER_SH 4
32
33/* DIDT IND registers */
34#define DIDT_SQ_CTRL0 0x0
35# define DIDT_CTRL_EN (1 << 0)
36#define DIDT_DB_CTRL0 0x20
37#define DIDT_TD_CTRL0 0x40
38#define DIDT_TCP_CTRL0 0x60
39
40/* SMC IND registers */
41#define DPM_TABLE_475 0x3F768
42# define SamuBootLevel(x) ((x) << 0)
43# define SamuBootLevel_MASK 0x000000ff
44# define SamuBootLevel_SHIFT 0
45# define AcpBootLevel(x) ((x) << 8)
46# define AcpBootLevel_MASK 0x0000ff00
47# define AcpBootLevel_SHIFT 8
48# define VceBootLevel(x) ((x) << 16)
49# define VceBootLevel_MASK 0x00ff0000
50# define VceBootLevel_SHIFT 16
51# define UvdBootLevel(x) ((x) << 24)
52# define UvdBootLevel_MASK 0xff000000
53# define UvdBootLevel_SHIFT 24
54
55#define FIRMWARE_FLAGS 0x3F800
56# define INTERRUPTS_ENABLED (1 << 0)
57
58#define NB_DPM_CONFIG_1 0x3F9E8
59# define Dpm0PgNbPsLo(x) ((x) << 0)
60# define Dpm0PgNbPsLo_MASK 0x000000ff
61# define Dpm0PgNbPsLo_SHIFT 0
62# define Dpm0PgNbPsHi(x) ((x) << 8)
63# define Dpm0PgNbPsHi_MASK 0x0000ff00
64# define Dpm0PgNbPsHi_SHIFT 8
65# define DpmXNbPsLo(x) ((x) << 16)
66# define DpmXNbPsLo_MASK 0x00ff0000
67# define DpmXNbPsLo_SHIFT 16
68# define DpmXNbPsHi(x) ((x) << 24)
69# define DpmXNbPsHi_MASK 0xff000000
70# define DpmXNbPsHi_SHIFT 24
71
72#define SMC_SYSCON_RESET_CNTL 0x80000000
73# define RST_REG (1 << 0)
74#define SMC_SYSCON_CLOCK_CNTL_0 0x80000004
75# define CK_DISABLE (1 << 0)
76# define CKEN (1 << 24)
77
78#define SMC_SYSCON_MISC_CNTL 0x80000010
79
80#define SMC_SYSCON_MSG_ARG_0 0x80000068
81
82#define SMC_PC_C 0x80000370
83
84#define SMC_SCRATCH9 0x80000424
85
86#define RCU_UC_EVENTS 0xC0000004
87# define BOOT_SEQ_DONE (1 << 7)
88
89#define GENERAL_PWRMGT 0xC0200000
90# define GLOBAL_PWRMGT_EN (1 << 0)
91# define STATIC_PM_EN (1 << 1)
92# define THERMAL_PROTECTION_DIS (1 << 2)
93# define THERMAL_PROTECTION_TYPE (1 << 3)
94# define SW_SMIO_INDEX(x) ((x) << 6)
95# define SW_SMIO_INDEX_MASK (1 << 6)
96# define SW_SMIO_INDEX_SHIFT 6
97# define VOLT_PWRMGT_EN (1 << 10)
98# define GPU_COUNTER_CLK (1 << 15)
99# define DYN_SPREAD_SPECTRUM_EN (1 << 23)
100
101#define CNB_PWRMGT_CNTL 0xC0200004
102# define GNB_SLOW_MODE(x) ((x) << 0)
103# define GNB_SLOW_MODE_MASK (3 << 0)
104# define GNB_SLOW_MODE_SHIFT 0
105# define GNB_SLOW (1 << 2)
106# define FORCE_NB_PS1 (1 << 3)
107# define DPM_ENABLED (1 << 4)
108
109#define SCLK_PWRMGT_CNTL 0xC0200008
110# define SCLK_PWRMGT_OFF (1 << 0)
111# define RESET_BUSY_CNT (1 << 4)
112# define RESET_SCLK_CNT (1 << 5)
113# define DYNAMIC_PM_EN (1 << 21)
114
115#define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014
116# define CURRENT_STATE_MASK (0xf << 4)
117# define CURRENT_STATE_SHIFT 4
118# define CURR_MCLK_INDEX_MASK (0xf << 8)
119# define CURR_MCLK_INDEX_SHIFT 8
120# define CURR_SCLK_INDEX_MASK (0x1f << 16)
121# define CURR_SCLK_INDEX_SHIFT 16
122
123#define CG_SSP 0xC0200044
124# define SST(x) ((x) << 0)
125# define SST_MASK (0xffff << 0)
126# define SSTU(x) ((x) << 16)
127# define SSTU_MASK (0xf << 16)
128
129#define CG_DISPLAY_GAP_CNTL 0xC0200060
130# define DISP_GAP(x) ((x) << 0)
131# define DISP_GAP_MASK (3 << 0)
132# define VBI_TIMER_COUNT(x) ((x) << 4)
133# define VBI_TIMER_COUNT_MASK (0x3fff << 4)
134# define VBI_TIMER_UNIT(x) ((x) << 20)
135# define VBI_TIMER_UNIT_MASK (7 << 20)
136# define DISP_GAP_MCHG(x) ((x) << 24)
137# define DISP_GAP_MCHG_MASK (3 << 24)
138
139#define SMU_VOLTAGE_STATUS 0xC0200094
140# define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1)
141# define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1
142
143#define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0
144# define CURR_PCIE_INDEX_MASK (0xf << 24)
145# define CURR_PCIE_INDEX_SHIFT 24
146
147#define CG_ULV_PARAMETER 0xC0200158
148
149#define CG_FTV_0 0xC02001A8
150#define CG_FTV_1 0xC02001AC
151#define CG_FTV_2 0xC02001B0
152#define CG_FTV_3 0xC02001B4
153#define CG_FTV_4 0xC02001B8
154#define CG_FTV_5 0xC02001BC
155#define CG_FTV_6 0xC02001C0
156#define CG_FTV_7 0xC02001C4
157
158#define CG_DISPLAY_GAP_CNTL2 0xC0200230
159
160#define LCAC_SX0_OVR_SEL 0xC0400D04
161#define LCAC_SX0_OVR_VAL 0xC0400D08
162
163#define LCAC_MC0_CNTL 0xC0400D30
164#define LCAC_MC0_OVR_SEL 0xC0400D34
165#define LCAC_MC0_OVR_VAL 0xC0400D38
166#define LCAC_MC1_CNTL 0xC0400D3C
167#define LCAC_MC1_OVR_SEL 0xC0400D40
168#define LCAC_MC1_OVR_VAL 0xC0400D44
169
170#define LCAC_MC2_OVR_SEL 0xC0400D4C
171#define LCAC_MC2_OVR_VAL 0xC0400D50
172
173#define LCAC_MC3_OVR_SEL 0xC0400D58
174#define LCAC_MC3_OVR_VAL 0xC0400D5C
175
176#define LCAC_CPL_CNTL 0xC0400D80
177#define LCAC_CPL_OVR_SEL 0xC0400D84
178#define LCAC_CPL_OVR_VAL 0xC0400D88
179
180/* dGPU */
181#define CG_THERMAL_CTRL 0xC0300004
182#define DPM_EVENT_SRC(x) ((x) << 0)
183#define DPM_EVENT_SRC_MASK (7 << 0)
184#define DIG_THERM_DPM(x) ((x) << 14)
185#define DIG_THERM_DPM_MASK 0x003FC000
186#define DIG_THERM_DPM_SHIFT 14
187
188#define CG_THERMAL_INT 0xC030000C
189#define CI_DIG_THERM_INTH(x) ((x) << 8)
190#define CI_DIG_THERM_INTH_MASK 0x0000FF00
191#define CI_DIG_THERM_INTH_SHIFT 8
192#define CI_DIG_THERM_INTL(x) ((x) << 16)
193#define CI_DIG_THERM_INTL_MASK 0x00FF0000
194#define CI_DIG_THERM_INTL_SHIFT 16
195#define THERM_INT_MASK_HIGH (1 << 24)
196#define THERM_INT_MASK_LOW (1 << 25)
197
198#define CG_MULT_THERMAL_STATUS 0xC0300014
199#define ASIC_MAX_TEMP(x) ((x) << 0)
200#define ASIC_MAX_TEMP_MASK 0x000001ff
201#define ASIC_MAX_TEMP_SHIFT 0
202#define CTF_TEMP(x) ((x) << 9)
203#define CTF_TEMP_MASK 0x0003fe00
204#define CTF_TEMP_SHIFT 9
205
206#define CG_ECLK_CNTL 0xC05000AC
207# define ECLK_DIVIDER_MASK 0x7f
208# define ECLK_DIR_CNTL_EN (1 << 8)
209#define CG_ECLK_STATUS 0xC05000B0
210# define ECLK_STATUS (1 << 0)
211
212#define CG_SPLL_FUNC_CNTL 0xC0500140
213#define SPLL_RESET (1 << 0)
214#define SPLL_PWRON (1 << 1)
215#define SPLL_BYPASS_EN (1 << 3)
216#define SPLL_REF_DIV(x) ((x) << 5)
217#define SPLL_REF_DIV_MASK (0x3f << 5)
218#define SPLL_PDIV_A(x) ((x) << 20)
219#define SPLL_PDIV_A_MASK (0x7f << 20)
220#define SPLL_PDIV_A_SHIFT 20
221#define CG_SPLL_FUNC_CNTL_2 0xC0500144
222#define SCLK_MUX_SEL(x) ((x) << 0)
223#define SCLK_MUX_SEL_MASK (0x1ff << 0)
224#define CG_SPLL_FUNC_CNTL_3 0xC0500148
225#define SPLL_FB_DIV(x) ((x) << 0)
226#define SPLL_FB_DIV_MASK (0x3ffffff << 0)
227#define SPLL_FB_DIV_SHIFT 0
228#define SPLL_DITHEN (1 << 28)
229#define CG_SPLL_FUNC_CNTL_4 0xC050014C
230
231#define CG_SPLL_SPREAD_SPECTRUM 0xC0500164
232#define SSEN (1 << 0)
233#define CLK_S(x) ((x) << 4)
234#define CLK_S_MASK (0xfff << 4)
235#define CLK_S_SHIFT 4
236#define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168
237#define CLK_V(x) ((x) << 0)
238#define CLK_V_MASK (0x3ffffff << 0)
239#define CLK_V_SHIFT 0
240
241#define MPLL_BYPASSCLK_SEL 0xC050019C
242# define MPLL_CLKOUT_SEL(x) ((x) << 8)
243# define MPLL_CLKOUT_SEL_MASK 0xFF00
244#define CG_CLKPIN_CNTL 0xC05001A0
245# define XTALIN_DIVIDE (1 << 1)
246# define BCLK_AS_XCLK (1 << 2)
247#define CG_CLKPIN_CNTL_2 0xC05001A4
248# define FORCE_BIF_REFCLK_EN (1 << 3)
249# define MUX_TCLK_TO_XCLK (1 << 8)
250#define THM_CLK_CNTL 0xC05001A8
251# define CMON_CLK_SEL(x) ((x) << 0)
252# define CMON_CLK_SEL_MASK 0xFF
253# define TMON_CLK_SEL(x) ((x) << 8)
254# define TMON_CLK_SEL_MASK 0xFF00
255#define MISC_CLK_CTRL 0xC05001AC
256# define DEEP_SLEEP_CLK_SEL(x) ((x) << 0)
257# define DEEP_SLEEP_CLK_SEL_MASK 0xFF
258# define ZCLK_SEL(x) ((x) << 8)
259# define ZCLK_SEL_MASK 0xFF00
260
261/* KV/KB */
262#define CG_THERMAL_INT_CTRL 0xC2100028
263#define DIG_THERM_INTH(x) ((x) << 0)
264#define DIG_THERM_INTH_MASK 0x000000FF
265#define DIG_THERM_INTH_SHIFT 0
266#define DIG_THERM_INTL(x) ((x) << 8)
267#define DIG_THERM_INTL_MASK 0x0000FF00
268#define DIG_THERM_INTL_SHIFT 8
269#define THERM_INTH_MASK (1 << 24)
270#define THERM_INTL_MASK (1 << 25)
271
272/* PCIE registers idx/data 0x38/0x3c */
273#define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */
274# define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7)
275# define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7)
276# define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7
277# define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10)
278# define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10)
279# define PLL_POWER_STATE_IN_OFF_0_SHIFT 10
280# define PLL_RAMP_UP_TIME_0(x) ((x) << 24)
281# define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24)
282# define PLL_RAMP_UP_TIME_0_SHIFT 24
283#define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */
284# define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7)
285# define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7)
286# define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7
287# define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10)
288# define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10)
289# define PLL_POWER_STATE_IN_OFF_1_SHIFT 10
290# define PLL_RAMP_UP_TIME_1(x) ((x) << 24)
291# define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24)
292# define PLL_RAMP_UP_TIME_1_SHIFT 24
293
294#define PCIE_CNTL2 0x1001001c /* PCIE */
295# define SLV_MEM_LS_EN (1 << 16)
296# define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17)
297# define MST_MEM_LS_EN (1 << 18)
298# define REPLAY_MEM_LS_EN (1 << 19)
299
300#define PCIE_LC_STATUS1 0x1400028 /* PCIE */
301# define LC_REVERSE_RCVR (1 << 0)
302# define LC_REVERSE_XMIT (1 << 1)
303# define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2)
304# define LC_OPERATING_LINK_WIDTH_SHIFT 2
305# define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5)
306# define LC_DETECTED_LINK_WIDTH_SHIFT 5
307
308#define PCIE_P_CNTL 0x1400040 /* PCIE */
309# define P_IGNORE_EDB_ERR (1 << 6)
310
311#define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */
312#define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */
313
314#define PCIE_LC_CNTL 0x100100A0 /* PCIE */
315# define LC_L0S_INACTIVITY(x) ((x) << 8)
316# define LC_L0S_INACTIVITY_MASK (0xf << 8)
317# define LC_L0S_INACTIVITY_SHIFT 8
318# define LC_L1_INACTIVITY(x) ((x) << 12)
319# define LC_L1_INACTIVITY_MASK (0xf << 12)
320# define LC_L1_INACTIVITY_SHIFT 12
321# define LC_PMI_TO_L1_DIS (1 << 16)
322# define LC_ASPM_TO_L1_DIS (1 << 24)
323
324#define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */
325# define LC_LINK_WIDTH_SHIFT 0
326# define LC_LINK_WIDTH_MASK 0x7
327# define LC_LINK_WIDTH_X0 0
328# define LC_LINK_WIDTH_X1 1
329# define LC_LINK_WIDTH_X2 2
330# define LC_LINK_WIDTH_X4 3
331# define LC_LINK_WIDTH_X8 4
332# define LC_LINK_WIDTH_X16 6
333# define LC_LINK_WIDTH_RD_SHIFT 4
334# define LC_LINK_WIDTH_RD_MASK 0x70
335# define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
336# define LC_RECONFIG_NOW (1 << 8)
337# define LC_RENEGOTIATION_SUPPORT (1 << 9)
338# define LC_RENEGOTIATE_EN (1 << 10)
339# define LC_SHORT_RECONFIG_EN (1 << 11)
340# define LC_UPCONFIGURE_SUPPORT (1 << 12)
341# define LC_UPCONFIGURE_DIS (1 << 13)
342# define LC_DYN_LANES_PWR_STATE(x) ((x) << 21)
343# define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21)
344# define LC_DYN_LANES_PWR_STATE_SHIFT 21
345#define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */
346# define LC_XMIT_N_FTS(x) ((x) << 0)
347# define LC_XMIT_N_FTS_MASK (0xff << 0)
348# define LC_XMIT_N_FTS_SHIFT 0
349# define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8)
350# define LC_N_FTS_MASK (0xff << 24)
351#define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */
352# define LC_GEN2_EN_STRAP (1 << 0)
353# define LC_GEN3_EN_STRAP (1 << 1)
354# define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2)
355# define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3)
356# define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3
357# define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5)
358# define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6)
359# define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7)
360# define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8)
361# define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9)
362# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10)
363# define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10
364# define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */
365# define LC_CURRENT_DATA_RATE_SHIFT 13
366# define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16)
367# define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18)
368# define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19)
369# define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20)
370# define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21)
371
372#define PCIE_LC_CNTL2 0x100100B1 /* PCIE */
373# define LC_ALLOW_PDWN_IN_L1 (1 << 17)
374# define LC_ALLOW_PDWN_IN_L23 (1 << 18)
375
376#define PCIE_LC_CNTL3 0x100100B5 /* PCIE */
377# define LC_GO_TO_RECOVERY (1 << 30)
378#define PCIE_LC_CNTL4 0x100100B6 /* PCIE */
379# define LC_REDO_EQ (1 << 5)
380# define LC_SET_QUIESCE (1 << 13)
381
382/* direct registers */
383#define PCIE_INDEX 0x38
384#define PCIE_DATA 0x3C
385
386#define SMC_IND_INDEX_0 0x200
387#define SMC_IND_DATA_0 0x204
388
389#define SMC_IND_ACCESS_CNTL 0x240
390#define AUTO_INCREMENT_IND_0 (1 << 0)
391
392#define SMC_MESSAGE_0 0x250
393#define SMC_MSG_MASK 0xffff
394#define SMC_RESP_0 0x254
395#define SMC_RESP_MASK 0xffff
396
397#define SMC_MSG_ARG_0 0x290
398
399#define VGA_HDP_CONTROL 0x328
400#define VGA_MEMORY_DISABLE (1 << 4)
401
402#define DMIF_ADDR_CALC 0xC00
403
404#define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0
405# define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0)
406# define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4)
407
408#define SRBM_GFX_CNTL 0xE44
409#define PIPEID(x) ((x) << 0)
410#define MEID(x) ((x) << 2)
411#define VMID(x) ((x) << 4)
412#define QUEUEID(x) ((x) << 8)
413
414#define SRBM_STATUS2 0xE4C
415#define SDMA_BUSY (1 << 5)
416#define SDMA1_BUSY (1 << 6)
417#define SRBM_STATUS 0xE50
418#define UVD_RQ_PENDING (1 << 1)
419#define GRBM_RQ_PENDING (1 << 5)
420#define VMC_BUSY (1 << 8)
421#define MCB_BUSY (1 << 9)
422#define MCB_NON_DISPLAY_BUSY (1 << 10)
423#define MCC_BUSY (1 << 11)
424#define MCD_BUSY (1 << 12)
425#define SEM_BUSY (1 << 14)
426#define IH_BUSY (1 << 17)
427#define UVD_BUSY (1 << 19)
428
429#define SRBM_SOFT_RESET 0xE60
430#define SOFT_RESET_BIF (1 << 1)
431#define SOFT_RESET_R0PLL (1 << 4)
432#define SOFT_RESET_DC (1 << 5)
433#define SOFT_RESET_SDMA1 (1 << 6)
434#define SOFT_RESET_GRBM (1 << 8)
435#define SOFT_RESET_HDP (1 << 9)
436#define SOFT_RESET_IH (1 << 10)
437#define SOFT_RESET_MC (1 << 11)
438#define SOFT_RESET_ROM (1 << 14)
439#define SOFT_RESET_SEM (1 << 15)
440#define SOFT_RESET_VMC (1 << 17)
441#define SOFT_RESET_SDMA (1 << 20)
442#define SOFT_RESET_TST (1 << 21)
443#define SOFT_RESET_REGBB (1 << 22)
444#define SOFT_RESET_ORB (1 << 23)
445#define SOFT_RESET_VCE (1 << 24)
446
447#define VM_L2_CNTL 0x1400
448#define ENABLE_L2_CACHE (1 << 0)
449#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
450#define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2)
451#define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4)
452#define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
453#define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10)
454#define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15)
455#define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19)
456#define VM_L2_CNTL2 0x1404
457#define INVALIDATE_ALL_L1_TLBS (1 << 0)
458#define INVALIDATE_L2_CACHE (1 << 1)
459#define INVALIDATE_CACHE_MODE(x) ((x) << 26)
460#define INVALIDATE_PTE_AND_PDE_CACHES 0
461#define INVALIDATE_ONLY_PTE_CACHES 1
462#define INVALIDATE_ONLY_PDE_CACHES 2
463#define VM_L2_CNTL3 0x1408
464#define BANK_SELECT(x) ((x) << 0)
465#define L2_CACHE_UPDATE_MODE(x) ((x) << 6)
466#define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15)
467#define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20)
468#define VM_L2_STATUS 0x140C
469#define L2_BUSY (1 << 0)
470#define VM_CONTEXT0_CNTL 0x1410
471#define ENABLE_CONTEXT (1 << 0)
472#define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
473#define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3)
474#define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
475#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6)
476#define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7)
477#define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9)
478#define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10)
479#define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12)
480#define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13)
481#define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15)
482#define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16)
483#define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18)
484#define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19)
485#define VM_CONTEXT1_CNTL 0x1414
486#define VM_CONTEXT0_CNTL2 0x1430
487#define VM_CONTEXT1_CNTL2 0x1434
488#define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438
489#define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c
490#define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440
491#define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444
492#define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448
493#define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c
494#define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450
495#define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454
496
497#define VM_INVALIDATE_REQUEST 0x1478
498#define VM_INVALIDATE_RESPONSE 0x147c
499
500#define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC
501#define PROTECTIONS_MASK (0xf << 0)
502#define PROTECTIONS_SHIFT 0
503 /* bit 0: range
504 * bit 1: pde0
505 * bit 2: valid
506 * bit 3: read
507 * bit 4: write
508 */
509#define MEMORY_CLIENT_ID_MASK (0xff << 12)
510#define HAWAII_MEMORY_CLIENT_ID_MASK (0x1ff << 12)
511#define MEMORY_CLIENT_ID_SHIFT 12
512#define MEMORY_CLIENT_RW_MASK (1 << 24)
513#define MEMORY_CLIENT_RW_SHIFT 24
514#define FAULT_VMID_MASK (0xf << 25)
515#define FAULT_VMID_SHIFT 25
516
517#define VM_CONTEXT1_PROTECTION_FAULT_MCCLIENT 0x14E4
518
519#define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC
520
521#define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
522#define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c
523
524#define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c
525#define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540
526#define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544
527#define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548
528#define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c
529#define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550
530#define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554
531#define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558
532#define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c
533#define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560
534
535#define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
536#define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580
537
538#define VM_L2_CG 0x15c0
539#define MC_CG_ENABLE (1 << 18)
540#define MC_LS_ENABLE (1 << 19)
541
542#define MC_SHARED_CHMAP 0x2004
543#define NOOFCHAN_SHIFT 12
544#define NOOFCHAN_MASK 0x0000f000
545#define MC_SHARED_CHREMAP 0x2008
546
547#define CHUB_CONTROL 0x1864
548#define BYPASS_VM (1 << 0)
549
550#define MC_VM_FB_LOCATION 0x2024
551#define MC_VM_AGP_TOP 0x2028
552#define MC_VM_AGP_BOT 0x202C
553#define MC_VM_AGP_BASE 0x2030
554#define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
555#define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
556#define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
557
558#define MC_VM_MX_L1_TLB_CNTL 0x2064
559#define ENABLE_L1_TLB (1 << 0)
560#define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
561#define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
562#define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
563#define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
564#define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
565#define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
566#define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6)
567#define MC_VM_FB_OFFSET 0x2068
568
569#define MC_SHARED_BLACKOUT_CNTL 0x20ac
570
571#define MC_HUB_MISC_HUB_CG 0x20b8
572#define MC_HUB_MISC_VM_CG 0x20bc
573
574#define MC_HUB_MISC_SIP_CG 0x20c0
575
576#define MC_XPB_CLK_GAT 0x2478
577
578#define MC_CITF_MISC_RD_CG 0x2648
579#define MC_CITF_MISC_WR_CG 0x264c
580#define MC_CITF_MISC_VM_CG 0x2650
581
582#define MC_ARB_RAMCFG 0x2760
583#define NOOFBANK_SHIFT 0
584#define NOOFBANK_MASK 0x00000003
585#define NOOFRANK_SHIFT 2
586#define NOOFRANK_MASK 0x00000004
587#define NOOFROWS_SHIFT 3
588#define NOOFROWS_MASK 0x00000038
589#define NOOFCOLS_SHIFT 6
590#define NOOFCOLS_MASK 0x000000C0
591#define CHANSIZE_SHIFT 8
592#define CHANSIZE_MASK 0x00000100
593#define NOOFGROUPS_SHIFT 12
594#define NOOFGROUPS_MASK 0x00001000
595
596#define MC_ARB_DRAM_TIMING 0x2774
597#define MC_ARB_DRAM_TIMING2 0x2778
598
599#define MC_ARB_BURST_TIME 0x2808
600#define STATE0(x) ((x) << 0)
601#define STATE0_MASK (0x1f << 0)
602#define STATE0_SHIFT 0
603#define STATE1(x) ((x) << 5)
604#define STATE1_MASK (0x1f << 5)
605#define STATE1_SHIFT 5
606#define STATE2(x) ((x) << 10)
607#define STATE2_MASK (0x1f << 10)
608#define STATE2_SHIFT 10
609#define STATE3(x) ((x) << 15)
610#define STATE3_MASK (0x1f << 15)
611#define STATE3_SHIFT 15
612
613#define MC_SEQ_RAS_TIMING 0x28a0
614#define MC_SEQ_CAS_TIMING 0x28a4
615#define MC_SEQ_MISC_TIMING 0x28a8
616#define MC_SEQ_MISC_TIMING2 0x28ac
617#define MC_SEQ_PMG_TIMING 0x28b0
618#define MC_SEQ_RD_CTL_D0 0x28b4
619#define MC_SEQ_RD_CTL_D1 0x28b8
620#define MC_SEQ_WR_CTL_D0 0x28bc
621#define MC_SEQ_WR_CTL_D1 0x28c0
622
623#define MC_SEQ_SUP_CNTL 0x28c8
624#define RUN_MASK (1 << 0)
625#define MC_SEQ_SUP_PGM 0x28cc
626#define MC_PMG_AUTO_CMD 0x28d0
627
628#define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8
629#define TRAIN_DONE_D0 (1 << 30)
630#define TRAIN_DONE_D1 (1 << 31)
631
632#define MC_IO_PAD_CNTL_D0 0x29d0
633#define MEM_FALL_OUT_CMD (1 << 8)
634
635#define MC_SEQ_MISC0 0x2a00
636#define MC_SEQ_MISC0_VEN_ID_SHIFT 8
637#define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00
638#define MC_SEQ_MISC0_VEN_ID_VALUE 3
639#define MC_SEQ_MISC0_REV_ID_SHIFT 12
640#define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000
641#define MC_SEQ_MISC0_REV_ID_VALUE 1
642#define MC_SEQ_MISC0_GDDR5_SHIFT 28
643#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
644#define MC_SEQ_MISC0_GDDR5_VALUE 5
645#define MC_SEQ_MISC1 0x2a04
646#define MC_SEQ_RESERVE_M 0x2a08
647#define MC_PMG_CMD_EMRS 0x2a0c
648
649#define MC_SEQ_IO_DEBUG_INDEX 0x2a44
650#define MC_SEQ_IO_DEBUG_DATA 0x2a48
651
652#define MC_SEQ_MISC5 0x2a54
653#define MC_SEQ_MISC6 0x2a58
654
655#define MC_SEQ_MISC7 0x2a64
656
657#define MC_SEQ_RAS_TIMING_LP 0x2a6c
658#define MC_SEQ_CAS_TIMING_LP 0x2a70
659#define MC_SEQ_MISC_TIMING_LP 0x2a74
660#define MC_SEQ_MISC_TIMING2_LP 0x2a78
661#define MC_SEQ_WR_CTL_D0_LP 0x2a7c
662#define MC_SEQ_WR_CTL_D1_LP 0x2a80
663#define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84
664#define MC_SEQ_PMG_CMD_MRS_LP 0x2a88
665
666#define MC_PMG_CMD_MRS 0x2aac
667
668#define MC_SEQ_RD_CTL_D0_LP 0x2b1c
669#define MC_SEQ_RD_CTL_D1_LP 0x2b20
670
671#define MC_PMG_CMD_MRS1 0x2b44
672#define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48
673#define MC_SEQ_PMG_TIMING_LP 0x2b4c
674
675#define MC_SEQ_WR_CTL_2 0x2b54
676#define MC_SEQ_WR_CTL_2_LP 0x2b58
677#define MC_PMG_CMD_MRS2 0x2b5c
678#define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60
679
680#define MCLK_PWRMGT_CNTL 0x2ba0
681# define DLL_SPEED(x) ((x) << 0)
682# define DLL_SPEED_MASK (0x1f << 0)
683# define DLL_READY (1 << 6)
684# define MC_INT_CNTL (1 << 7)
685# define MRDCK0_PDNB (1 << 8)
686# define MRDCK1_PDNB (1 << 9)
687# define MRDCK0_RESET (1 << 16)
688# define MRDCK1_RESET (1 << 17)
689# define DLL_READY_READ (1 << 24)
690#define DLL_CNTL 0x2ba4
691# define MRDCK0_BYPASS (1 << 24)
692# define MRDCK1_BYPASS (1 << 25)
693
694#define MPLL_FUNC_CNTL 0x2bb4
695#define BWCTRL(x) ((x) << 20)
696#define BWCTRL_MASK (0xff << 20)
697#define MPLL_FUNC_CNTL_1 0x2bb8
698#define VCO_MODE(x) ((x) << 0)
699#define VCO_MODE_MASK (3 << 0)
700#define CLKFRAC(x) ((x) << 4)
701#define CLKFRAC_MASK (0xfff << 4)
702#define CLKF(x) ((x) << 16)
703#define CLKF_MASK (0xfff << 16)
704#define MPLL_FUNC_CNTL_2 0x2bbc
705#define MPLL_AD_FUNC_CNTL 0x2bc0
706#define YCLK_POST_DIV(x) ((x) << 0)
707#define YCLK_POST_DIV_MASK (7 << 0)
708#define MPLL_DQ_FUNC_CNTL 0x2bc4
709#define YCLK_SEL(x) ((x) << 4)
710#define YCLK_SEL_MASK (1 << 4)
711
712#define MPLL_SS1 0x2bcc
713#define CLKV(x) ((x) << 0)
714#define CLKV_MASK (0x3ffffff << 0)
715#define MPLL_SS2 0x2bd0
716#define CLKS(x) ((x) << 0)
717#define CLKS_MASK (0xfff << 0)
718
719#define HDP_HOST_PATH_CNTL 0x2C00
720#define CLOCK_GATING_DIS (1 << 23)
721#define HDP_NONSURFACE_BASE 0x2C04
722#define HDP_NONSURFACE_INFO 0x2C08
723#define HDP_NONSURFACE_SIZE 0x2C0C
724
725#define HDP_ADDR_CONFIG 0x2F48
726#define HDP_MISC_CNTL 0x2F4C
727#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
728#define HDP_MEM_POWER_LS 0x2F50
729#define HDP_LS_ENABLE (1 << 0)
730
731#define ATC_MISC_CG 0x3350
732
733#define GMCON_RENG_EXECUTE 0x3508
734#define RENG_EXECUTE_ON_PWR_UP (1 << 0)
735#define GMCON_MISC 0x350c
736#define RENG_EXECUTE_ON_REG_UPDATE (1 << 11)
737#define STCTRL_STUTTER_EN (1 << 16)
738
739#define GMCON_PGFSM_CONFIG 0x3538
740#define GMCON_PGFSM_WRITE 0x353c
741#define GMCON_PGFSM_READ 0x3540
742#define GMCON_MISC3 0x3544
743
744#define MC_SEQ_CNTL_3 0x3600
745# define CAC_EN (1 << 31)
746#define MC_SEQ_G5PDX_CTRL 0x3604
747#define MC_SEQ_G5PDX_CTRL_LP 0x3608
748#define MC_SEQ_G5PDX_CMD0 0x360c
749#define MC_SEQ_G5PDX_CMD0_LP 0x3610
750#define MC_SEQ_G5PDX_CMD1 0x3614
751#define MC_SEQ_G5PDX_CMD1_LP 0x3618
752
753#define MC_SEQ_PMG_DVS_CTL 0x3628
754#define MC_SEQ_PMG_DVS_CTL_LP 0x362c
755#define MC_SEQ_PMG_DVS_CMD 0x3630
756#define MC_SEQ_PMG_DVS_CMD_LP 0x3634
757#define MC_SEQ_DLL_STBY 0x3638
758#define MC_SEQ_DLL_STBY_LP 0x363c
759
760#define IH_RB_CNTL 0x3e00
761# define IH_RB_ENABLE (1 << 0)
762# define IH_RB_SIZE(x) ((x) << 1) /* log2 */
763# define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
764# define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
765# define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
766# define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
767# define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
768#define IH_RB_BASE 0x3e04
769#define IH_RB_RPTR 0x3e08
770#define IH_RB_WPTR 0x3e0c
771# define RB_OVERFLOW (1 << 0)
772# define WPTR_OFFSET_MASK 0x3fffc
773#define IH_RB_WPTR_ADDR_HI 0x3e10
774#define IH_RB_WPTR_ADDR_LO 0x3e14
775#define IH_CNTL 0x3e18
776# define ENABLE_INTR (1 << 0)
777# define IH_MC_SWAP(x) ((x) << 1)
778# define IH_MC_SWAP_NONE 0
779# define IH_MC_SWAP_16BIT 1
780# define IH_MC_SWAP_32BIT 2
781# define IH_MC_SWAP_64BIT 3
782# define RPTR_REARM (1 << 4)
783# define MC_WRREQ_CREDIT(x) ((x) << 15)
784# define MC_WR_CLEAN_CNT(x) ((x) << 20)
785# define MC_VMID(x) ((x) << 25)
786
787#define BIF_LNCNT_RESET 0x5220
788# define RESET_LNCNT_EN (1 << 0)
789
790#define CONFIG_MEMSIZE 0x5428
791
792#define INTERRUPT_CNTL 0x5468
793# define IH_DUMMY_RD_OVERRIDE (1 << 0)
794# define IH_DUMMY_RD_EN (1 << 1)
795# define IH_REQ_NONSNOOP_EN (1 << 3)
796# define GEN_IH_INT_EN (1 << 8)
797#define INTERRUPT_CNTL2 0x546c
798
799#define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
800
801#define BIF_FB_EN 0x5490
802#define FB_READ_EN (1 << 0)
803#define FB_WRITE_EN (1 << 1)
804
805#define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
806
807#define GPU_HDP_FLUSH_REQ 0x54DC
808#define GPU_HDP_FLUSH_DONE 0x54E0
809#define CP0 (1 << 0)
810#define CP1 (1 << 1)
811#define CP2 (1 << 2)
812#define CP3 (1 << 3)
813#define CP4 (1 << 4)
814#define CP5 (1 << 5)
815#define CP6 (1 << 6)
816#define CP7 (1 << 7)
817#define CP8 (1 << 8)
818#define CP9 (1 << 9)
819#define SDMA0 (1 << 10)
820#define SDMA1 (1 << 11)
821
822/* 0x6b04, 0x7704, 0x10304, 0x10f04, 0x11b04, 0x12704 */
823#define LB_MEMORY_CTRL 0x6b04
824#define LB_MEMORY_SIZE(x) ((x) << 0)
825#define LB_MEMORY_CONFIG(x) ((x) << 20)
826
827#define DPG_WATERMARK_MASK_CONTROL 0x6cc8
828# define LATENCY_WATERMARK_MASK(x) ((x) << 8)
829#define DPG_PIPE_LATENCY_CONTROL 0x6ccc
830# define LATENCY_LOW_WATERMARK(x) ((x) << 0)
831# define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
832
833/* 0x6b24, 0x7724, 0x10324, 0x10f24, 0x11b24, 0x12724 */
834#define LB_VLINE_STATUS 0x6b24
835# define VLINE_OCCURRED (1 << 0)
836# define VLINE_ACK (1 << 4)
837# define VLINE_STAT (1 << 12)
838# define VLINE_INTERRUPT (1 << 16)
839# define VLINE_INTERRUPT_TYPE (1 << 17)
840/* 0x6b2c, 0x772c, 0x1032c, 0x10f2c, 0x11b2c, 0x1272c */
841#define LB_VBLANK_STATUS 0x6b2c
842# define VBLANK_OCCURRED (1 << 0)
843# define VBLANK_ACK (1 << 4)
844# define VBLANK_STAT (1 << 12)
845# define VBLANK_INTERRUPT (1 << 16)
846# define VBLANK_INTERRUPT_TYPE (1 << 17)
847
848/* 0x6b20, 0x7720, 0x10320, 0x10f20, 0x11b20, 0x12720 */
849#define LB_INTERRUPT_MASK 0x6b20
850# define VBLANK_INTERRUPT_MASK (1 << 0)
851# define VLINE_INTERRUPT_MASK (1 << 4)
852# define VLINE2_INTERRUPT_MASK (1 << 8)
853
854#define DISP_INTERRUPT_STATUS 0x60f4
855# define LB_D1_VLINE_INTERRUPT (1 << 2)
856# define LB_D1_VBLANK_INTERRUPT (1 << 3)
857# define DC_HPD1_INTERRUPT (1 << 17)
858# define DC_HPD1_RX_INTERRUPT (1 << 18)
859# define DACA_AUTODETECT_INTERRUPT (1 << 22)
860# define DACB_AUTODETECT_INTERRUPT (1 << 23)
861# define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
862# define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
863#define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
864# define LB_D2_VLINE_INTERRUPT (1 << 2)
865# define LB_D2_VBLANK_INTERRUPT (1 << 3)
866# define DC_HPD2_INTERRUPT (1 << 17)
867# define DC_HPD2_RX_INTERRUPT (1 << 18)
868# define DISP_TIMER_INTERRUPT (1 << 24)
869#define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
870# define LB_D3_VLINE_INTERRUPT (1 << 2)
871# define LB_D3_VBLANK_INTERRUPT (1 << 3)
872# define DC_HPD3_INTERRUPT (1 << 17)
873# define DC_HPD3_RX_INTERRUPT (1 << 18)
874#define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
875# define LB_D4_VLINE_INTERRUPT (1 << 2)
876# define LB_D4_VBLANK_INTERRUPT (1 << 3)
877# define DC_HPD4_INTERRUPT (1 << 17)
878# define DC_HPD4_RX_INTERRUPT (1 << 18)
879#define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
880# define LB_D5_VLINE_INTERRUPT (1 << 2)
881# define LB_D5_VBLANK_INTERRUPT (1 << 3)
882# define DC_HPD5_INTERRUPT (1 << 17)
883# define DC_HPD5_RX_INTERRUPT (1 << 18)
884#define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150
885# define LB_D6_VLINE_INTERRUPT (1 << 2)
886# define LB_D6_VBLANK_INTERRUPT (1 << 3)
887# define DC_HPD6_INTERRUPT (1 << 17)
888# define DC_HPD6_RX_INTERRUPT (1 << 18)
889#define DISP_INTERRUPT_STATUS_CONTINUE6 0x6780
890
891/* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
892#define GRPH_INT_STATUS 0x6858
893# define GRPH_PFLIP_INT_OCCURRED (1 << 0)
894# define GRPH_PFLIP_INT_CLEAR (1 << 8)
895/* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
896#define GRPH_INT_CONTROL 0x685c
897# define GRPH_PFLIP_INT_MASK (1 << 0)
898# define GRPH_PFLIP_INT_TYPE (1 << 8)
899
900#define DAC_AUTODETECT_INT_CONTROL 0x67c8
901
902#define DC_HPD1_INT_STATUS 0x601c
903#define DC_HPD2_INT_STATUS 0x6028
904#define DC_HPD3_INT_STATUS 0x6034
905#define DC_HPD4_INT_STATUS 0x6040
906#define DC_HPD5_INT_STATUS 0x604c
907#define DC_HPD6_INT_STATUS 0x6058
908# define DC_HPDx_INT_STATUS (1 << 0)
909# define DC_HPDx_SENSE (1 << 1)
910# define DC_HPDx_SENSE_DELAYED (1 << 4)
911# define DC_HPDx_RX_INT_STATUS (1 << 8)
912
913#define DC_HPD1_INT_CONTROL 0x6020
914#define DC_HPD2_INT_CONTROL 0x602c
915#define DC_HPD3_INT_CONTROL 0x6038
916#define DC_HPD4_INT_CONTROL 0x6044
917#define DC_HPD5_INT_CONTROL 0x6050
918#define DC_HPD6_INT_CONTROL 0x605c
919# define DC_HPDx_INT_ACK (1 << 0)
920# define DC_HPDx_INT_POLARITY (1 << 8)
921# define DC_HPDx_INT_EN (1 << 16)
922# define DC_HPDx_RX_INT_ACK (1 << 20)
923# define DC_HPDx_RX_INT_EN (1 << 24)
924
925#define DC_HPD1_CONTROL 0x6024
926#define DC_HPD2_CONTROL 0x6030
927#define DC_HPD3_CONTROL 0x603c
928#define DC_HPD4_CONTROL 0x6048
929#define DC_HPD5_CONTROL 0x6054
930#define DC_HPD6_CONTROL 0x6060
931# define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
932# define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
933# define DC_HPDx_EN (1 << 28)
934
935#define DPG_PIPE_STUTTER_CONTROL 0x6cd4
936# define STUTTER_ENABLE (1 << 0)
937
938/* DCE8 FMT blocks */
939#define FMT_DYNAMIC_EXP_CNTL 0x6fb4
940# define FMT_DYNAMIC_EXP_EN (1 << 0)
941# define FMT_DYNAMIC_EXP_MODE (1 << 4)
942 /* 0 = 10bit -> 12bit, 1 = 8bit -> 12bit */
943#define FMT_CONTROL 0x6fb8
944# define FMT_PIXEL_ENCODING (1 << 16)
945 /* 0 = RGB 4:4:4 or YCbCr 4:4:4, 1 = YCbCr 4:2:2 */
946#define FMT_BIT_DEPTH_CONTROL 0x6fc8
947# define FMT_TRUNCATE_EN (1 << 0)
948# define FMT_TRUNCATE_MODE (1 << 1)
949# define FMT_TRUNCATE_DEPTH(x) ((x) << 4) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
950# define FMT_SPATIAL_DITHER_EN (1 << 8)
951# define FMT_SPATIAL_DITHER_MODE(x) ((x) << 9)
952# define FMT_SPATIAL_DITHER_DEPTH(x) ((x) << 11) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
953# define FMT_FRAME_RANDOM_ENABLE (1 << 13)
954# define FMT_RGB_RANDOM_ENABLE (1 << 14)
955# define FMT_HIGHPASS_RANDOM_ENABLE (1 << 15)
956# define FMT_TEMPORAL_DITHER_EN (1 << 16)
957# define FMT_TEMPORAL_DITHER_DEPTH(x) ((x) << 17) /* 0 - 18bpp, 1 - 24bpp, 2 - 30bpp */
958# define FMT_TEMPORAL_DITHER_OFFSET(x) ((x) << 21)
959# define FMT_TEMPORAL_LEVEL (1 << 24)
960# define FMT_TEMPORAL_DITHER_RESET (1 << 25)
961# define FMT_25FRC_SEL(x) ((x) << 26)
962# define FMT_50FRC_SEL(x) ((x) << 28)
963# define FMT_75FRC_SEL(x) ((x) << 30)
964#define FMT_CLAMP_CONTROL 0x6fe4
965# define FMT_CLAMP_DATA_EN (1 << 0)
966# define FMT_CLAMP_COLOR_FORMAT(x) ((x) << 16)
967# define FMT_CLAMP_6BPC 0
968# define FMT_CLAMP_8BPC 1
969# define FMT_CLAMP_10BPC 2
970
971#define GRBM_CNTL 0x8000
972#define GRBM_READ_TIMEOUT(x) ((x) << 0)
973
974#define GRBM_STATUS2 0x8008
975#define ME0PIPE1_CMDFIFO_AVAIL_MASK 0x0000000F
976#define ME0PIPE1_CF_RQ_PENDING (1 << 4)
977#define ME0PIPE1_PF_RQ_PENDING (1 << 5)
978#define ME1PIPE0_RQ_PENDING (1 << 6)
979#define ME1PIPE1_RQ_PENDING (1 << 7)
980#define ME1PIPE2_RQ_PENDING (1 << 8)
981#define ME1PIPE3_RQ_PENDING (1 << 9)
982#define ME2PIPE0_RQ_PENDING (1 << 10)
983#define ME2PIPE1_RQ_PENDING (1 << 11)
984#define ME2PIPE2_RQ_PENDING (1 << 12)
985#define ME2PIPE3_RQ_PENDING (1 << 13)
986#define RLC_RQ_PENDING (1 << 14)
987#define RLC_BUSY (1 << 24)
988#define TC_BUSY (1 << 25)
989#define CPF_BUSY (1 << 28)
990#define CPC_BUSY (1 << 29)
991#define CPG_BUSY (1 << 30)
992
993#define GRBM_STATUS 0x8010
994#define ME0PIPE0_CMDFIFO_AVAIL_MASK 0x0000000F
995#define SRBM_RQ_PENDING (1 << 5)
996#define ME0PIPE0_CF_RQ_PENDING (1 << 7)
997#define ME0PIPE0_PF_RQ_PENDING (1 << 8)
998#define GDS_DMA_RQ_PENDING (1 << 9)
999#define DB_CLEAN (1 << 12)
1000#define CB_CLEAN (1 << 13)
1001#define TA_BUSY (1 << 14)
1002#define GDS_BUSY (1 << 15)
1003#define WD_BUSY_NO_DMA (1 << 16)
1004#define VGT_BUSY (1 << 17)
1005#define IA_BUSY_NO_DMA (1 << 18)
1006#define IA_BUSY (1 << 19)
1007#define SX_BUSY (1 << 20)
1008#define WD_BUSY (1 << 21)
1009#define SPI_BUSY (1 << 22)
1010#define BCI_BUSY (1 << 23)
1011#define SC_BUSY (1 << 24)
1012#define PA_BUSY (1 << 25)
1013#define DB_BUSY (1 << 26)
1014#define CP_COHERENCY_BUSY (1 << 28)
1015#define CP_BUSY (1 << 29)
1016#define CB_BUSY (1 << 30)
1017#define GUI_ACTIVE (1 << 31)
1018#define GRBM_STATUS_SE0 0x8014
1019#define GRBM_STATUS_SE1 0x8018
1020#define GRBM_STATUS_SE2 0x8038
1021#define GRBM_STATUS_SE3 0x803C
1022#define SE_DB_CLEAN (1 << 1)
1023#define SE_CB_CLEAN (1 << 2)
1024#define SE_BCI_BUSY (1 << 22)
1025#define SE_VGT_BUSY (1 << 23)
1026#define SE_PA_BUSY (1 << 24)
1027#define SE_TA_BUSY (1 << 25)
1028#define SE_SX_BUSY (1 << 26)
1029#define SE_SPI_BUSY (1 << 27)
1030#define SE_SC_BUSY (1 << 29)
1031#define SE_DB_BUSY (1 << 30)
1032#define SE_CB_BUSY (1 << 31)
1033
1034#define GRBM_SOFT_RESET 0x8020
1035#define SOFT_RESET_CP (1 << 0) /* All CP blocks */
1036#define SOFT_RESET_RLC (1 << 2) /* RLC */
1037#define SOFT_RESET_GFX (1 << 16) /* GFX */
1038#define SOFT_RESET_CPF (1 << 17) /* CP fetcher shared by gfx and compute */
1039#define SOFT_RESET_CPC (1 << 18) /* CP Compute (MEC1/2) */
1040#define SOFT_RESET_CPG (1 << 19) /* CP GFX (PFP, ME, CE) */
1041
1042#define GRBM_INT_CNTL 0x8060
1043# define RDERR_INT_ENABLE (1 << 0)
1044# define GUI_IDLE_INT_ENABLE (1 << 19)
1045
1046#define CP_CPC_STATUS 0x8210
1047#define CP_CPC_BUSY_STAT 0x8214
1048#define CP_CPC_STALLED_STAT1 0x8218
1049#define CP_CPF_STATUS 0x821c
1050#define CP_CPF_BUSY_STAT 0x8220
1051#define CP_CPF_STALLED_STAT1 0x8224
1052
1053#define CP_MEC_CNTL 0x8234
1054#define MEC_ME2_HALT (1 << 28)
1055#define MEC_ME1_HALT (1 << 30)
1056
1057#define CP_MEC_CNTL 0x8234
1058#define MEC_ME2_HALT (1 << 28)
1059#define MEC_ME1_HALT (1 << 30)
1060
1061#define CP_STALLED_STAT3 0x8670
1062#define CP_STALLED_STAT1 0x8674
1063#define CP_STALLED_STAT2 0x8678
1064
1065#define CP_STAT 0x8680
1066
1067#define CP_ME_CNTL 0x86D8
1068#define CP_CE_HALT (1 << 24)
1069#define CP_PFP_HALT (1 << 26)
1070#define CP_ME_HALT (1 << 28)
1071
1072#define CP_RB0_RPTR 0x8700
1073#define CP_RB_WPTR_DELAY 0x8704
1074#define CP_RB_WPTR_POLL_CNTL 0x8708
1075#define IDLE_POLL_COUNT(x) ((x) << 16)
1076#define IDLE_POLL_COUNT_MASK (0xffff << 16)
1077
1078#define CP_MEQ_THRESHOLDS 0x8764
1079#define MEQ1_START(x) ((x) << 0)
1080#define MEQ2_START(x) ((x) << 8)
1081
1082#define VGT_VTX_VECT_EJECT_REG 0x88B0
1083
1084#define VGT_CACHE_INVALIDATION 0x88C4
1085#define CACHE_INVALIDATION(x) ((x) << 0)
1086#define VC_ONLY 0
1087#define TC_ONLY 1
1088#define VC_AND_TC 2
1089#define AUTO_INVLD_EN(x) ((x) << 6)
1090#define NO_AUTO 0
1091#define ES_AUTO 1
1092#define GS_AUTO 2
1093#define ES_AND_GS_AUTO 3
1094
1095#define VGT_GS_VERTEX_REUSE 0x88D4
1096
1097#define CC_GC_SHADER_ARRAY_CONFIG 0x89bc
1098#define INACTIVE_CUS_MASK 0xFFFF0000
1099#define INACTIVE_CUS_SHIFT 16
1100#define GC_USER_SHADER_ARRAY_CONFIG 0x89c0
1101
1102#define PA_CL_ENHANCE 0x8A14
1103#define CLIP_VTX_REORDER_ENA (1 << 0)
1104#define NUM_CLIP_SEQ(x) ((x) << 1)
1105
1106#define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
1107#define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
1108#define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
1109
1110#define PA_SC_FIFO_SIZE 0x8BCC
1111#define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0)
1112#define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6)
1113#define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15)
1114#define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23)
1115
1116#define PA_SC_ENHANCE 0x8BF0
1117#define ENABLE_PA_SC_OUT_OF_ORDER (1 << 0)
1118#define DISABLE_PA_SC_GUIDANCE (1 << 13)
1119
1120#define SQ_CONFIG 0x8C00
1121
1122#define SH_MEM_BASES 0x8C28
1123/* if PTR32, these are the bases for scratch and lds */
1124#define PRIVATE_BASE(x) ((x) << 0) /* scratch */
1125#define SHARED_BASE(x) ((x) << 16) /* LDS */
1126#define SH_MEM_APE1_BASE 0x8C2C
1127/* if PTR32, this is the base location of GPUVM */
1128#define SH_MEM_APE1_LIMIT 0x8C30
1129/* if PTR32, this is the upper limit of GPUVM */
1130#define SH_MEM_CONFIG 0x8C34
1131#define PTR32 (1 << 0)
1132#define ALIGNMENT_MODE(x) ((x) << 2)
1133#define SH_MEM_ALIGNMENT_MODE_DWORD 0
1134#define SH_MEM_ALIGNMENT_MODE_DWORD_STRICT 1
1135#define SH_MEM_ALIGNMENT_MODE_STRICT 2
1136#define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3
1137#define DEFAULT_MTYPE(x) ((x) << 4)
1138#define APE1_MTYPE(x) ((x) << 7)
1139
1140#define SX_DEBUG_1 0x9060
1141
1142#define SPI_CONFIG_CNTL 0x9100
1143
1144#define SPI_CONFIG_CNTL_1 0x913C
1145#define VTX_DONE_DELAY(x) ((x) << 0)
1146#define INTERP_ONE_PRIM_PER_ROW (1 << 4)
1147
1148#define TA_CNTL_AUX 0x9508
1149
1150#define DB_DEBUG 0x9830
1151#define DB_DEBUG2 0x9834
1152#define DB_DEBUG3 0x9838
1153
1154#define CC_RB_BACKEND_DISABLE 0x98F4
1155#define BACKEND_DISABLE(x) ((x) << 16)
1156#define GB_ADDR_CONFIG 0x98F8
1157#define NUM_PIPES(x) ((x) << 0)
1158#define NUM_PIPES_MASK 0x00000007
1159#define NUM_PIPES_SHIFT 0
1160#define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
1161#define PIPE_INTERLEAVE_SIZE_MASK 0x00000070
1162#define PIPE_INTERLEAVE_SIZE_SHIFT 4
1163#define NUM_SHADER_ENGINES(x) ((x) << 12)
1164#define NUM_SHADER_ENGINES_MASK 0x00003000
1165#define NUM_SHADER_ENGINES_SHIFT 12
1166#define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
1167#define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000
1168#define SHADER_ENGINE_TILE_SIZE_SHIFT 16
1169#define ROW_SIZE(x) ((x) << 28)
1170#define ROW_SIZE_MASK 0x30000000
1171#define ROW_SIZE_SHIFT 28
1172
1173#define GB_TILE_MODE0 0x9910
1174# define ARRAY_MODE(x) ((x) << 2)
1175# define ARRAY_LINEAR_GENERAL 0
1176# define ARRAY_LINEAR_ALIGNED 1
1177# define ARRAY_1D_TILED_THIN1 2
1178# define ARRAY_2D_TILED_THIN1 4
1179# define ARRAY_PRT_TILED_THIN1 5
1180# define ARRAY_PRT_2D_TILED_THIN1 6
1181# define PIPE_CONFIG(x) ((x) << 6)
1182# define ADDR_SURF_P2 0
1183# define ADDR_SURF_P4_8x16 4
1184# define ADDR_SURF_P4_16x16 5
1185# define ADDR_SURF_P4_16x32 6
1186# define ADDR_SURF_P4_32x32 7
1187# define ADDR_SURF_P8_16x16_8x16 8
1188# define ADDR_SURF_P8_16x32_8x16 9
1189# define ADDR_SURF_P8_32x32_8x16 10
1190# define ADDR_SURF_P8_16x32_16x16 11
1191# define ADDR_SURF_P8_32x32_16x16 12
1192# define ADDR_SURF_P8_32x32_16x32 13
1193# define ADDR_SURF_P8_32x64_32x32 14
1194# define ADDR_SURF_P16_32x32_8x16 16
1195# define ADDR_SURF_P16_32x32_16x16 17
1196# define TILE_SPLIT(x) ((x) << 11)
1197# define ADDR_SURF_TILE_SPLIT_64B 0
1198# define ADDR_SURF_TILE_SPLIT_128B 1
1199# define ADDR_SURF_TILE_SPLIT_256B 2
1200# define ADDR_SURF_TILE_SPLIT_512B 3
1201# define ADDR_SURF_TILE_SPLIT_1KB 4
1202# define ADDR_SURF_TILE_SPLIT_2KB 5
1203# define ADDR_SURF_TILE_SPLIT_4KB 6
1204# define MICRO_TILE_MODE_NEW(x) ((x) << 22)
1205# define ADDR_SURF_DISPLAY_MICRO_TILING 0
1206# define ADDR_SURF_THIN_MICRO_TILING 1
1207# define ADDR_SURF_DEPTH_MICRO_TILING 2
1208# define ADDR_SURF_ROTATED_MICRO_TILING 3
1209# define SAMPLE_SPLIT(x) ((x) << 25)
1210# define ADDR_SURF_SAMPLE_SPLIT_1 0
1211# define ADDR_SURF_SAMPLE_SPLIT_2 1
1212# define ADDR_SURF_SAMPLE_SPLIT_4 2
1213# define ADDR_SURF_SAMPLE_SPLIT_8 3
1214
1215#define GB_MACROTILE_MODE0 0x9990
1216# define BANK_WIDTH(x) ((x) << 0)
1217# define ADDR_SURF_BANK_WIDTH_1 0
1218# define ADDR_SURF_BANK_WIDTH_2 1
1219# define ADDR_SURF_BANK_WIDTH_4 2
1220# define ADDR_SURF_BANK_WIDTH_8 3
1221# define BANK_HEIGHT(x) ((x) << 2)
1222# define ADDR_SURF_BANK_HEIGHT_1 0
1223# define ADDR_SURF_BANK_HEIGHT_2 1
1224# define ADDR_SURF_BANK_HEIGHT_4 2
1225# define ADDR_SURF_BANK_HEIGHT_8 3
1226# define MACRO_TILE_ASPECT(x) ((x) << 4)
1227# define ADDR_SURF_MACRO_ASPECT_1 0
1228# define ADDR_SURF_MACRO_ASPECT_2 1
1229# define ADDR_SURF_MACRO_ASPECT_4 2
1230# define ADDR_SURF_MACRO_ASPECT_8 3
1231# define NUM_BANKS(x) ((x) << 6)
1232# define ADDR_SURF_2_BANK 0
1233# define ADDR_SURF_4_BANK 1
1234# define ADDR_SURF_8_BANK 2
1235# define ADDR_SURF_16_BANK 3
1236
1237#define CB_HW_CONTROL 0x9A10
1238
1239#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
1240#define BACKEND_DISABLE_MASK 0x00FF0000
1241#define BACKEND_DISABLE_SHIFT 16
1242
1243#define TCP_CHAN_STEER_LO 0xac0c
1244#define TCP_CHAN_STEER_HI 0xac10
1245
1246#define TC_CFG_L1_LOAD_POLICY0 0xAC68
1247#define TC_CFG_L1_LOAD_POLICY1 0xAC6C
1248#define TC_CFG_L1_STORE_POLICY 0xAC70
1249#define TC_CFG_L2_LOAD_POLICY0 0xAC74
1250#define TC_CFG_L2_LOAD_POLICY1 0xAC78
1251#define TC_CFG_L2_STORE_POLICY0 0xAC7C
1252#define TC_CFG_L2_STORE_POLICY1 0xAC80
1253#define TC_CFG_L2_ATOMIC_POLICY 0xAC84
1254#define TC_CFG_L1_VOLATILE 0xAC88
1255#define TC_CFG_L2_VOLATILE 0xAC8C
1256
1257#define CP_RB0_BASE 0xC100
1258#define CP_RB0_CNTL 0xC104
1259#define RB_BUFSZ(x) ((x) << 0)
1260#define RB_BLKSZ(x) ((x) << 8)
1261#define BUF_SWAP_32BIT (2 << 16)
1262#define RB_NO_UPDATE (1 << 27)
1263#define RB_RPTR_WR_ENA (1 << 31)
1264
1265#define CP_RB0_RPTR_ADDR 0xC10C
1266#define RB_RPTR_SWAP_32BIT (2 << 0)
1267#define CP_RB0_RPTR_ADDR_HI 0xC110
1268#define CP_RB0_WPTR 0xC114
1269
1270#define CP_DEVICE_ID 0xC12C
1271#define CP_ENDIAN_SWAP 0xC140
1272#define CP_RB_VMID 0xC144
1273
1274#define CP_PFP_UCODE_ADDR 0xC150
1275#define CP_PFP_UCODE_DATA 0xC154
1276#define CP_ME_RAM_RADDR 0xC158
1277#define CP_ME_RAM_WADDR 0xC15C
1278#define CP_ME_RAM_DATA 0xC160
1279
1280#define CP_CE_UCODE_ADDR 0xC168
1281#define CP_CE_UCODE_DATA 0xC16C
1282#define CP_MEC_ME1_UCODE_ADDR 0xC170
1283#define CP_MEC_ME1_UCODE_DATA 0xC174
1284#define CP_MEC_ME2_UCODE_ADDR 0xC178
1285#define CP_MEC_ME2_UCODE_DATA 0xC17C
1286
1287#define CP_INT_CNTL_RING0 0xC1A8
1288# define CNTX_BUSY_INT_ENABLE (1 << 19)
1289# define CNTX_EMPTY_INT_ENABLE (1 << 20)
1290# define PRIV_INSTR_INT_ENABLE (1 << 22)
1291# define PRIV_REG_INT_ENABLE (1 << 23)
1292# define TIME_STAMP_INT_ENABLE (1 << 26)
1293# define CP_RINGID2_INT_ENABLE (1 << 29)
1294# define CP_RINGID1_INT_ENABLE (1 << 30)
1295# define CP_RINGID0_INT_ENABLE (1 << 31)
1296
1297#define CP_INT_STATUS_RING0 0xC1B4
1298# define PRIV_INSTR_INT_STAT (1 << 22)
1299# define PRIV_REG_INT_STAT (1 << 23)
1300# define TIME_STAMP_INT_STAT (1 << 26)
1301# define CP_RINGID2_INT_STAT (1 << 29)
1302# define CP_RINGID1_INT_STAT (1 << 30)
1303# define CP_RINGID0_INT_STAT (1 << 31)
1304
1305#define CP_MEM_SLP_CNTL 0xC1E4
1306# define CP_MEM_LS_EN (1 << 0)
1307
1308#define CP_CPF_DEBUG 0xC200
1309
1310#define CP_PQ_WPTR_POLL_CNTL 0xC20C
1311#define WPTR_POLL_EN (1 << 31)
1312
1313#define CP_ME1_PIPE0_INT_CNTL 0xC214
1314#define CP_ME1_PIPE1_INT_CNTL 0xC218
1315#define CP_ME1_PIPE2_INT_CNTL 0xC21C
1316#define CP_ME1_PIPE3_INT_CNTL 0xC220
1317#define CP_ME2_PIPE0_INT_CNTL 0xC224
1318#define CP_ME2_PIPE1_INT_CNTL 0xC228
1319#define CP_ME2_PIPE2_INT_CNTL 0xC22C
1320#define CP_ME2_PIPE3_INT_CNTL 0xC230
1321# define DEQUEUE_REQUEST_INT_ENABLE (1 << 13)
1322# define WRM_POLL_TIMEOUT_INT_ENABLE (1 << 17)
1323# define PRIV_REG_INT_ENABLE (1 << 23)
1324# define TIME_STAMP_INT_ENABLE (1 << 26)
1325# define GENERIC2_INT_ENABLE (1 << 29)
1326# define GENERIC1_INT_ENABLE (1 << 30)
1327# define GENERIC0_INT_ENABLE (1 << 31)
1328#define CP_ME1_PIPE0_INT_STATUS 0xC214
1329#define CP_ME1_PIPE1_INT_STATUS 0xC218
1330#define CP_ME1_PIPE2_INT_STATUS 0xC21C
1331#define CP_ME1_PIPE3_INT_STATUS 0xC220
1332#define CP_ME2_PIPE0_INT_STATUS 0xC224
1333#define CP_ME2_PIPE1_INT_STATUS 0xC228
1334#define CP_ME2_PIPE2_INT_STATUS 0xC22C
1335#define CP_ME2_PIPE3_INT_STATUS 0xC230
1336# define DEQUEUE_REQUEST_INT_STATUS (1 << 13)
1337# define WRM_POLL_TIMEOUT_INT_STATUS (1 << 17)
1338# define PRIV_REG_INT_STATUS (1 << 23)
1339# define TIME_STAMP_INT_STATUS (1 << 26)
1340# define GENERIC2_INT_STATUS (1 << 29)
1341# define GENERIC1_INT_STATUS (1 << 30)
1342# define GENERIC0_INT_STATUS (1 << 31)
1343
1344#define CP_MAX_CONTEXT 0xC2B8
1345
1346#define CP_RB0_BASE_HI 0xC2C4
1347
1348#define RLC_CNTL 0xC300
1349# define RLC_ENABLE (1 << 0)
1350
1351#define RLC_MC_CNTL 0xC30C
1352
1353#define RLC_MEM_SLP_CNTL 0xC318
1354# define RLC_MEM_LS_EN (1 << 0)
1355
1356#define RLC_LB_CNTR_MAX 0xC348
1357
1358#define RLC_LB_CNTL 0xC364
1359# define LOAD_BALANCE_ENABLE (1 << 0)
1360
1361#define RLC_LB_CNTR_INIT 0xC36C
1362
1363#define RLC_SAVE_AND_RESTORE_BASE 0xC374
1364#define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */
1365#define RLC_CP_TABLE_RESTORE 0xC378 /* APU */
1366#define RLC_PG_DELAY_2 0xC37C
1367
1368#define RLC_GPM_UCODE_ADDR 0xC388
1369#define RLC_GPM_UCODE_DATA 0xC38C
1370#define RLC_GPU_CLOCK_COUNT_LSB 0xC390
1371#define RLC_GPU_CLOCK_COUNT_MSB 0xC394
1372#define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398
1373#define RLC_UCODE_CNTL 0xC39C
1374
1375#define RLC_GPM_STAT 0xC400
1376# define RLC_GPM_BUSY (1 << 0)
1377# define GFX_POWER_STATUS (1 << 1)
1378# define GFX_CLOCK_STATUS (1 << 2)
1379
1380#define RLC_PG_CNTL 0xC40C
1381# define GFX_PG_ENABLE (1 << 0)
1382# define GFX_PG_SRC (1 << 1)
1383# define DYN_PER_CU_PG_ENABLE (1 << 2)
1384# define STATIC_PER_CU_PG_ENABLE (1 << 3)
1385# define DISABLE_GDS_PG (1 << 13)
1386# define DISABLE_CP_PG (1 << 15)
1387# define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17)
1388# define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18)
1389
1390#define RLC_CGTT_MGCG_OVERRIDE 0xC420
1391#define RLC_CGCG_CGLS_CTRL 0xC424
1392# define CGCG_EN (1 << 0)
1393# define CGLS_EN (1 << 1)
1394
1395#define RLC_PG_DELAY 0xC434
1396
1397#define RLC_LB_INIT_CU_MASK 0xC43C
1398
1399#define RLC_LB_PARAMS 0xC444
1400
1401#define RLC_PG_AO_CU_MASK 0xC44C
1402
1403#define RLC_MAX_PG_CU 0xC450
1404# define MAX_PU_CU(x) ((x) << 0)
1405# define MAX_PU_CU_MASK (0xff << 0)
1406#define RLC_AUTO_PG_CTRL 0xC454
1407# define AUTO_PG_EN (1 << 0)
1408# define GRBM_REG_SGIT(x) ((x) << 3)
1409# define GRBM_REG_SGIT_MASK (0xffff << 3)
1410
1411#define RLC_SERDES_WR_CU_MASTER_MASK 0xC474
1412#define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478
1413#define RLC_SERDES_WR_CTRL 0xC47C
1414#define BPM_ADDR(x) ((x) << 0)
1415#define BPM_ADDR_MASK (0xff << 0)
1416#define CGLS_ENABLE (1 << 16)
1417#define CGCG_OVERRIDE_0 (1 << 20)
1418#define MGCG_OVERRIDE_0 (1 << 22)
1419#define MGCG_OVERRIDE_1 (1 << 23)
1420
1421#define RLC_SERDES_CU_MASTER_BUSY 0xC484
1422#define RLC_SERDES_NONCU_MASTER_BUSY 0xC488
1423# define SE_MASTER_BUSY_MASK 0x0000ffff
1424# define GC_MASTER_BUSY (1 << 16)
1425# define TC0_MASTER_BUSY (1 << 17)
1426# define TC1_MASTER_BUSY (1 << 18)
1427
1428#define RLC_GPM_SCRATCH_ADDR 0xC4B0
1429#define RLC_GPM_SCRATCH_DATA 0xC4B4
1430
1431#define RLC_GPR_REG2 0xC4E8
1432#define REQ 0x00000001
1433#define MESSAGE(x) ((x) << 1)
1434#define MESSAGE_MASK 0x0000001e
1435#define MSG_ENTER_RLC_SAFE_MODE 1
1436#define MSG_EXIT_RLC_SAFE_MODE 0
1437
1438#define CP_HPD_EOP_BASE_ADDR 0xC904
1439#define CP_HPD_EOP_BASE_ADDR_HI 0xC908
1440#define CP_HPD_EOP_VMID 0xC90C
1441#define CP_HPD_EOP_CONTROL 0xC910
1442#define EOP_SIZE(x) ((x) << 0)
1443#define EOP_SIZE_MASK (0x3f << 0)
1444#define CP_MQD_BASE_ADDR 0xC914
1445#define CP_MQD_BASE_ADDR_HI 0xC918
1446#define CP_HQD_ACTIVE 0xC91C
1447#define CP_HQD_VMID 0xC920
1448
1449#define CP_HQD_PQ_BASE 0xC934
1450#define CP_HQD_PQ_BASE_HI 0xC938
1451#define CP_HQD_PQ_RPTR 0xC93C
1452#define CP_HQD_PQ_RPTR_REPORT_ADDR 0xC940
1453#define CP_HQD_PQ_RPTR_REPORT_ADDR_HI 0xC944
1454#define CP_HQD_PQ_WPTR_POLL_ADDR 0xC948
1455#define CP_HQD_PQ_WPTR_POLL_ADDR_HI 0xC94C
1456#define CP_HQD_PQ_DOORBELL_CONTROL 0xC950
1457#define DOORBELL_OFFSET(x) ((x) << 2)
1458#define DOORBELL_OFFSET_MASK (0x1fffff << 2)
1459#define DOORBELL_SOURCE (1 << 28)
1460#define DOORBELL_SCHD_HIT (1 << 29)
1461#define DOORBELL_EN (1 << 30)
1462#define DOORBELL_HIT (1 << 31)
1463#define CP_HQD_PQ_WPTR 0xC954
1464#define CP_HQD_PQ_CONTROL 0xC958
1465#define QUEUE_SIZE(x) ((x) << 0)
1466#define QUEUE_SIZE_MASK (0x3f << 0)
1467#define RPTR_BLOCK_SIZE(x) ((x) << 8)
1468#define RPTR_BLOCK_SIZE_MASK (0x3f << 8)
1469#define PQ_VOLATILE (1 << 26)
1470#define NO_UPDATE_RPTR (1 << 27)
1471#define UNORD_DISPATCH (1 << 28)
1472#define ROQ_PQ_IB_FLIP (1 << 29)
1473#define PRIV_STATE (1 << 30)
1474#define KMD_QUEUE (1 << 31)
1475
1476#define CP_HQD_DEQUEUE_REQUEST 0xC974
1477
1478#define CP_MQD_CONTROL 0xC99C
1479#define MQD_VMID(x) ((x) << 0)
1480#define MQD_VMID_MASK (0xf << 0)
1481
1482#define DB_RENDER_CONTROL 0x28000
1483
1484#define PA_SC_RASTER_CONFIG 0x28350
1485# define RASTER_CONFIG_RB_MAP_0 0
1486# define RASTER_CONFIG_RB_MAP_1 1
1487# define RASTER_CONFIG_RB_MAP_2 2
1488# define RASTER_CONFIG_RB_MAP_3 3
1489#define PKR_MAP(x) ((x) << 8)
1490
1491#define VGT_EVENT_INITIATOR 0x28a90
1492# define SAMPLE_STREAMOUTSTATS1 (1 << 0)
1493# define SAMPLE_STREAMOUTSTATS2 (2 << 0)
1494# define SAMPLE_STREAMOUTSTATS3 (3 << 0)
1495# define CACHE_FLUSH_TS (4 << 0)
1496# define CACHE_FLUSH (6 << 0)
1497# define CS_PARTIAL_FLUSH (7 << 0)
1498# define VGT_STREAMOUT_RESET (10 << 0)
1499# define END_OF_PIPE_INCR_DE (11 << 0)
1500# define END_OF_PIPE_IB_END (12 << 0)
1501# define RST_PIX_CNT (13 << 0)
1502# define VS_PARTIAL_FLUSH (15 << 0)
1503# define PS_PARTIAL_FLUSH (16 << 0)
1504# define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0)
1505# define ZPASS_DONE (21 << 0)
1506# define CACHE_FLUSH_AND_INV_EVENT (22 << 0)
1507# define PERFCOUNTER_START (23 << 0)
1508# define PERFCOUNTER_STOP (24 << 0)
1509# define PIPELINESTAT_START (25 << 0)
1510# define PIPELINESTAT_STOP (26 << 0)
1511# define PERFCOUNTER_SAMPLE (27 << 0)
1512# define SAMPLE_PIPELINESTAT (30 << 0)
1513# define SO_VGT_STREAMOUT_FLUSH (31 << 0)
1514# define SAMPLE_STREAMOUTSTATS (32 << 0)
1515# define RESET_VTX_CNT (33 << 0)
1516# define VGT_FLUSH (36 << 0)
1517# define BOTTOM_OF_PIPE_TS (40 << 0)
1518# define DB_CACHE_FLUSH_AND_INV (42 << 0)
1519# define FLUSH_AND_INV_DB_DATA_TS (43 << 0)
1520# define FLUSH_AND_INV_DB_META (44 << 0)
1521# define FLUSH_AND_INV_CB_DATA_TS (45 << 0)
1522# define FLUSH_AND_INV_CB_META (46 << 0)
1523# define CS_DONE (47 << 0)
1524# define PS_DONE (48 << 0)
1525# define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0)
1526# define THREAD_TRACE_START (51 << 0)
1527# define THREAD_TRACE_STOP (52 << 0)
1528# define THREAD_TRACE_FLUSH (54 << 0)
1529# define THREAD_TRACE_FINISH (55 << 0)
1530# define PIXEL_PIPE_STAT_CONTROL (56 << 0)
1531# define PIXEL_PIPE_STAT_DUMP (57 << 0)
1532# define PIXEL_PIPE_STAT_RESET (58 << 0)
1533
1534#define SCRATCH_REG0 0x30100
1535#define SCRATCH_REG1 0x30104
1536#define SCRATCH_REG2 0x30108
1537#define SCRATCH_REG3 0x3010C
1538#define SCRATCH_REG4 0x30110
1539#define SCRATCH_REG5 0x30114
1540#define SCRATCH_REG6 0x30118
1541#define SCRATCH_REG7 0x3011C
1542
1543#define SCRATCH_UMSK 0x30140
1544#define SCRATCH_ADDR 0x30144
1545
1546#define CP_SEM_WAIT_TIMER 0x301BC
1547
1548#define CP_SEM_INCOMPLETE_TIMER_CNTL 0x301C8
1549
1550#define CP_WAIT_REG_MEM_TIMEOUT 0x301D0
1551
1552#define GRBM_GFX_INDEX 0x30800
1553#define INSTANCE_INDEX(x) ((x) << 0)
1554#define SH_INDEX(x) ((x) << 8)
1555#define SE_INDEX(x) ((x) << 16)
1556#define SH_BROADCAST_WRITES (1 << 29)
1557#define INSTANCE_BROADCAST_WRITES (1 << 30)
1558#define SE_BROADCAST_WRITES (1 << 31)
1559
1560#define VGT_ESGS_RING_SIZE 0x30900
1561#define VGT_GSVS_RING_SIZE 0x30904
1562#define VGT_PRIMITIVE_TYPE 0x30908
1563#define VGT_INDEX_TYPE 0x3090C
1564
1565#define VGT_NUM_INDICES 0x30930
1566#define VGT_NUM_INSTANCES 0x30934
1567#define VGT_TF_RING_SIZE 0x30938
1568#define VGT_HS_OFFCHIP_PARAM 0x3093C
1569#define VGT_TF_MEMORY_BASE 0x30940
1570
1571#define PA_SU_LINE_STIPPLE_VALUE 0x30a00
1572#define PA_SC_LINE_STIPPLE_STATE 0x30a04
1573
1574#define SQC_CACHES 0x30d20
1575
1576#define CP_PERFMON_CNTL 0x36020
1577
1578#define CGTS_SM_CTRL_REG 0x3c000
1579#define SM_MODE(x) ((x) << 17)
1580#define SM_MODE_MASK (0x7 << 17)
1581#define SM_MODE_ENABLE (1 << 20)
1582#define CGTS_OVERRIDE (1 << 21)
1583#define CGTS_LS_OVERRIDE (1 << 22)
1584#define ON_MONITOR_ADD_EN (1 << 23)
1585#define ON_MONITOR_ADD(x) ((x) << 24)
1586#define ON_MONITOR_ADD_MASK (0xff << 24)
1587
1588#define CGTS_TCC_DISABLE 0x3c00c
1589#define CGTS_USER_TCC_DISABLE 0x3c010
1590#define TCC_DISABLE_MASK 0xFFFF0000
1591#define TCC_DISABLE_SHIFT 16
1592
1593#define CB_CGTT_SCLK_CTRL 0x3c2a0
1594
1595/*
1596 * PM4
1597 */
1598#define PACKET_TYPE0 0
1599#define PACKET_TYPE1 1
1600#define PACKET_TYPE2 2
1601#define PACKET_TYPE3 3
1602
1603#define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
1604#define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
1605#define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
1606#define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
1607#define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
1608 (((reg) >> 2) & 0xFFFF) | \
1609 ((n) & 0x3FFF) << 16)
1610#define CP_PACKET2 0x80000000
1611#define PACKET2_PAD_SHIFT 0
1612#define PACKET2_PAD_MASK (0x3fffffff << 0)
1613
1614#define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
1615
1616#define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
1617 (((op) & 0xFF) << 8) | \
1618 ((n) & 0x3FFF) << 16)
1619
1620#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
1621
1622/* Packet 3 types */
1623#define PACKET3_NOP 0x10
1624#define PACKET3_SET_BASE 0x11
1625#define PACKET3_BASE_INDEX(x) ((x) << 0)
1626#define CE_PARTITION_BASE 3
1627#define PACKET3_CLEAR_STATE 0x12
1628#define PACKET3_INDEX_BUFFER_SIZE 0x13
1629#define PACKET3_DISPATCH_DIRECT 0x15
1630#define PACKET3_DISPATCH_INDIRECT 0x16
1631#define PACKET3_ATOMIC_GDS 0x1D
1632#define PACKET3_ATOMIC_MEM 0x1E
1633#define PACKET3_OCCLUSION_QUERY 0x1F
1634#define PACKET3_SET_PREDICATION 0x20
1635#define PACKET3_REG_RMW 0x21
1636#define PACKET3_COND_EXEC 0x22
1637#define PACKET3_PRED_EXEC 0x23
1638#define PACKET3_DRAW_INDIRECT 0x24
1639#define PACKET3_DRAW_INDEX_INDIRECT 0x25
1640#define PACKET3_INDEX_BASE 0x26
1641#define PACKET3_DRAW_INDEX_2 0x27
1642#define PACKET3_CONTEXT_CONTROL 0x28
1643#define PACKET3_INDEX_TYPE 0x2A
1644#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
1645#define PACKET3_DRAW_INDEX_AUTO 0x2D
1646#define PACKET3_NUM_INSTANCES 0x2F
1647#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
1648#define PACKET3_INDIRECT_BUFFER_CONST 0x33
1649#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
1650#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
1651#define PACKET3_DRAW_PREAMBLE 0x36
1652#define PACKET3_WRITE_DATA 0x37
1653#define WRITE_DATA_DST_SEL(x) ((x) << 8)
1654 /* 0 - register
1655 * 1 - memory (sync - via GRBM)
1656 * 2 - gl2
1657 * 3 - gds
1658 * 4 - reserved
1659 * 5 - memory (async - direct)
1660 */
1661#define WR_ONE_ADDR (1 << 16)
1662#define WR_CONFIRM (1 << 20)
1663#define WRITE_DATA_CACHE_POLICY(x) ((x) << 25)
1664 /* 0 - LRU
1665 * 1 - Stream
1666 */
1667#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
1668 /* 0 - me
1669 * 1 - pfp
1670 * 2 - ce
1671 */
1672#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
1673#define PACKET3_MEM_SEMAPHORE 0x39
1674# define PACKET3_SEM_USE_MAILBOX (0x1 << 16)
1675# define PACKET3_SEM_SEL_SIGNAL_TYPE (0x1 << 20) /* 0 = increment, 1 = write 1 */
1676# define PACKET3_SEM_CLIENT_CODE ((x) << 24) /* 0 = CP, 1 = CB, 2 = DB */
1677# define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
1678# define PACKET3_SEM_SEL_WAIT (0x7 << 29)
1679#define PACKET3_COPY_DW 0x3B
1680#define PACKET3_WAIT_REG_MEM 0x3C
1681#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
1682 /* 0 - always
1683 * 1 - <
1684 * 2 - <=
1685 * 3 - ==
1686 * 4 - !=
1687 * 5 - >=
1688 * 6 - >
1689 */
1690#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
1691 /* 0 - reg
1692 * 1 - mem
1693 */
1694#define WAIT_REG_MEM_OPERATION(x) ((x) << 6)
1695 /* 0 - wait_reg_mem
1696 * 1 - wr_wait_wr_reg
1697 */
1698#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
1699 /* 0 - me
1700 * 1 - pfp
1701 */
1702#define PACKET3_INDIRECT_BUFFER 0x3F
1703#define INDIRECT_BUFFER_TCL2_VOLATILE (1 << 22)
1704#define INDIRECT_BUFFER_VALID (1 << 23)
1705#define INDIRECT_BUFFER_CACHE_POLICY(x) ((x) << 28)
1706 /* 0 - LRU
1707 * 1 - Stream
1708 * 2 - Bypass
1709 */
1710#define PACKET3_COPY_DATA 0x40
1711#define PACKET3_PFP_SYNC_ME 0x42
1712#define PACKET3_SURFACE_SYNC 0x43
1713# define PACKET3_DEST_BASE_0_ENA (1 << 0)
1714# define PACKET3_DEST_BASE_1_ENA (1 << 1)
1715# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
1716# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
1717# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
1718# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
1719# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
1720# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
1721# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
1722# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
1723# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
1724# define PACKET3_TCL1_VOL_ACTION_ENA (1 << 15)
1725# define PACKET3_TC_VOL_ACTION_ENA (1 << 16) /* L2 */
1726# define PACKET3_TC_WB_ACTION_ENA (1 << 18) /* L2 */
1727# define PACKET3_DEST_BASE_2_ENA (1 << 19)
1728# define PACKET3_DEST_BASE_3_ENA (1 << 21)
1729# define PACKET3_TCL1_ACTION_ENA (1 << 22)
1730# define PACKET3_TC_ACTION_ENA (1 << 23) /* L2 */
1731# define PACKET3_CB_ACTION_ENA (1 << 25)
1732# define PACKET3_DB_ACTION_ENA (1 << 26)
1733# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
1734# define PACKET3_SH_KCACHE_VOL_ACTION_ENA (1 << 28)
1735# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
1736#define PACKET3_COND_WRITE 0x45
1737#define PACKET3_EVENT_WRITE 0x46
1738#define EVENT_TYPE(x) ((x) << 0)
1739#define EVENT_INDEX(x) ((x) << 8)
1740 /* 0 - any non-TS event
1741 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
1742 * 2 - SAMPLE_PIPELINESTAT
1743 * 3 - SAMPLE_STREAMOUTSTAT*
1744 * 4 - *S_PARTIAL_FLUSH
1745 * 5 - EOP events
1746 * 6 - EOS events
1747 */
1748#define PACKET3_EVENT_WRITE_EOP 0x47
1749#define EOP_TCL1_VOL_ACTION_EN (1 << 12)
1750#define EOP_TC_VOL_ACTION_EN (1 << 13) /* L2 */
1751#define EOP_TC_WB_ACTION_EN (1 << 15) /* L2 */
1752#define EOP_TCL1_ACTION_EN (1 << 16)
1753#define EOP_TC_ACTION_EN (1 << 17) /* L2 */
1754#define EOP_CACHE_POLICY(x) ((x) << 25)
1755 /* 0 - LRU
1756 * 1 - Stream
1757 * 2 - Bypass
1758 */
1759#define EOP_TCL2_VOLATILE (1 << 27)
1760#define DATA_SEL(x) ((x) << 29)
1761 /* 0 - discard
1762 * 1 - send low 32bit data
1763 * 2 - send 64bit data
1764 * 3 - send 64bit GPU counter value
1765 * 4 - send 64bit sys counter value
1766 */
1767#define INT_SEL(x) ((x) << 24)
1768 /* 0 - none
1769 * 1 - interrupt only (DATA_SEL = 0)
1770 * 2 - interrupt when data write is confirmed
1771 */
1772#define DST_SEL(x) ((x) << 16)
1773 /* 0 - MC
1774 * 1 - TC/L2
1775 */
1776#define PACKET3_EVENT_WRITE_EOS 0x48
1777#define PACKET3_RELEASE_MEM 0x49
1778#define PACKET3_PREAMBLE_CNTL 0x4A
1779# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
1780# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
1781#define PACKET3_DMA_DATA 0x50
1782/* 1. header
1783 * 2. CONTROL
1784 * 3. SRC_ADDR_LO or DATA [31:0]
1785 * 4. SRC_ADDR_HI [31:0]
1786 * 5. DST_ADDR_LO [31:0]
1787 * 6. DST_ADDR_HI [7:0]
1788 * 7. COMMAND [30:21] | BYTE_COUNT [20:0]
1789 */
1790/* CONTROL */
1791# define PACKET3_DMA_DATA_ENGINE(x) ((x) << 0)
1792 /* 0 - ME
1793 * 1 - PFP
1794 */
1795# define PACKET3_DMA_DATA_SRC_CACHE_POLICY(x) ((x) << 13)
1796 /* 0 - LRU
1797 * 1 - Stream
1798 * 2 - Bypass
1799 */
1800# define PACKET3_DMA_DATA_SRC_VOLATILE (1 << 15)
1801# define PACKET3_DMA_DATA_DST_SEL(x) ((x) << 20)
1802 /* 0 - DST_ADDR using DAS
1803 * 1 - GDS
1804 * 3 - DST_ADDR using L2
1805 */
1806# define PACKET3_DMA_DATA_DST_CACHE_POLICY(x) ((x) << 25)
1807 /* 0 - LRU
1808 * 1 - Stream
1809 * 2 - Bypass
1810 */
1811# define PACKET3_DMA_DATA_DST_VOLATILE (1 << 27)
1812# define PACKET3_DMA_DATA_SRC_SEL(x) ((x) << 29)
1813 /* 0 - SRC_ADDR using SAS
1814 * 1 - GDS
1815 * 2 - DATA
1816 * 3 - SRC_ADDR using L2
1817 */
1818# define PACKET3_DMA_DATA_CP_SYNC (1 << 31)
1819/* COMMAND */
1820# define PACKET3_DMA_DATA_DIS_WC (1 << 21)
1821# define PACKET3_DMA_DATA_CMD_SRC_SWAP(x) ((x) << 22)
1822 /* 0 - none
1823 * 1 - 8 in 16
1824 * 2 - 8 in 32
1825 * 3 - 8 in 64
1826 */
1827# define PACKET3_DMA_DATA_CMD_DST_SWAP(x) ((x) << 24)
1828 /* 0 - none
1829 * 1 - 8 in 16
1830 * 2 - 8 in 32
1831 * 3 - 8 in 64
1832 */
1833# define PACKET3_DMA_DATA_CMD_SAS (1 << 26)
1834 /* 0 - memory
1835 * 1 - register
1836 */
1837# define PACKET3_DMA_DATA_CMD_DAS (1 << 27)
1838 /* 0 - memory
1839 * 1 - register
1840 */
1841# define PACKET3_DMA_DATA_CMD_SAIC (1 << 28)
1842# define PACKET3_DMA_DATA_CMD_DAIC (1 << 29)
1843# define PACKET3_DMA_DATA_CMD_RAW_WAIT (1 << 30)
1844#define PACKET3_AQUIRE_MEM 0x58
1845#define PACKET3_REWIND 0x59
1846#define PACKET3_LOAD_UCONFIG_REG 0x5E
1847#define PACKET3_LOAD_SH_REG 0x5F
1848#define PACKET3_LOAD_CONFIG_REG 0x60
1849#define PACKET3_LOAD_CONTEXT_REG 0x61
1850#define PACKET3_SET_CONFIG_REG 0x68
1851#define PACKET3_SET_CONFIG_REG_START 0x00008000
1852#define PACKET3_SET_CONFIG_REG_END 0x0000b000
1853#define PACKET3_SET_CONTEXT_REG 0x69
1854#define PACKET3_SET_CONTEXT_REG_START 0x00028000
1855#define PACKET3_SET_CONTEXT_REG_END 0x00029000
1856#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
1857#define PACKET3_SET_SH_REG 0x76
1858#define PACKET3_SET_SH_REG_START 0x0000b000
1859#define PACKET3_SET_SH_REG_END 0x0000c000
1860#define PACKET3_SET_SH_REG_OFFSET 0x77
1861#define PACKET3_SET_QUEUE_REG 0x78
1862#define PACKET3_SET_UCONFIG_REG 0x79
1863#define PACKET3_SET_UCONFIG_REG_START 0x00030000
1864#define PACKET3_SET_UCONFIG_REG_END 0x00031000
1865#define PACKET3_SCRATCH_RAM_WRITE 0x7D
1866#define PACKET3_SCRATCH_RAM_READ 0x7E
1867#define PACKET3_LOAD_CONST_RAM 0x80
1868#define PACKET3_WRITE_CONST_RAM 0x81
1869#define PACKET3_DUMP_CONST_RAM 0x83
1870#define PACKET3_INCREMENT_CE_COUNTER 0x84
1871#define PACKET3_INCREMENT_DE_COUNTER 0x85
1872#define PACKET3_WAIT_ON_CE_COUNTER 0x86
1873#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
1874#define PACKET3_SWITCH_BUFFER 0x8B
1875
1876/* SDMA - first instance at 0xd000, second at 0xd800 */
1877#define SDMA0_REGISTER_OFFSET 0x0 /* not a register */
1878#define SDMA1_REGISTER_OFFSET 0x800 /* not a register */
1879
1880#define SDMA0_UCODE_ADDR 0xD000
1881#define SDMA0_UCODE_DATA 0xD004
1882#define SDMA0_POWER_CNTL 0xD008
1883#define SDMA0_CLK_CTRL 0xD00C
1884
1885#define SDMA0_CNTL 0xD010
1886# define TRAP_ENABLE (1 << 0)
1887# define SEM_INCOMPLETE_INT_ENABLE (1 << 1)
1888# define SEM_WAIT_INT_ENABLE (1 << 2)
1889# define DATA_SWAP_ENABLE (1 << 3)
1890# define FENCE_SWAP_ENABLE (1 << 4)
1891# define AUTO_CTXSW_ENABLE (1 << 18)
1892# define CTXEMPTY_INT_ENABLE (1 << 28)
1893
1894#define SDMA0_TILING_CONFIG 0xD018
1895
1896#define SDMA0_SEM_INCOMPLETE_TIMER_CNTL 0xD020
1897#define SDMA0_SEM_WAIT_FAIL_TIMER_CNTL 0xD024
1898
1899#define SDMA0_STATUS_REG 0xd034
1900# define SDMA_IDLE (1 << 0)
1901
1902#define SDMA0_ME_CNTL 0xD048
1903# define SDMA_HALT (1 << 0)
1904
1905#define SDMA0_GFX_RB_CNTL 0xD200
1906# define SDMA_RB_ENABLE (1 << 0)
1907# define SDMA_RB_SIZE(x) ((x) << 1) /* log2 */
1908# define SDMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */
1909# define SDMA_RPTR_WRITEBACK_ENABLE (1 << 12)
1910# define SDMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */
1911# define SDMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */
1912#define SDMA0_GFX_RB_BASE 0xD204
1913#define SDMA0_GFX_RB_BASE_HI 0xD208
1914#define SDMA0_GFX_RB_RPTR 0xD20C
1915#define SDMA0_GFX_RB_WPTR 0xD210
1916
1917#define SDMA0_GFX_RB_RPTR_ADDR_HI 0xD220
1918#define SDMA0_GFX_RB_RPTR_ADDR_LO 0xD224
1919#define SDMA0_GFX_IB_CNTL 0xD228
1920# define SDMA_IB_ENABLE (1 << 0)
1921# define SDMA_IB_SWAP_ENABLE (1 << 4)
1922# define SDMA_SWITCH_INSIDE_IB (1 << 8)
1923# define SDMA_CMD_VMID(x) ((x) << 16)
1924
1925#define SDMA0_GFX_VIRTUAL_ADDR 0xD29C
1926#define SDMA0_GFX_APE1_CNTL 0xD2A0
1927
1928#define SDMA_PACKET(op, sub_op, e) ((((e) & 0xFFFF) << 16) | \
1929 (((sub_op) & 0xFF) << 8) | \
1930 (((op) & 0xFF) << 0))
1931/* sDMA opcodes */
1932#define SDMA_OPCODE_NOP 0
1933#define SDMA_OPCODE_COPY 1
1934# define SDMA_COPY_SUB_OPCODE_LINEAR 0
1935# define SDMA_COPY_SUB_OPCODE_TILED 1
1936# define SDMA_COPY_SUB_OPCODE_SOA 3
1937# define SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW 4
1938# define SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW 5
1939# define SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW 6
1940#define SDMA_OPCODE_WRITE 2
1941# define SDMA_WRITE_SUB_OPCODE_LINEAR 0
1942# define SDMA_WRTIE_SUB_OPCODE_TILED 1
1943#define SDMA_OPCODE_INDIRECT_BUFFER 4
1944#define SDMA_OPCODE_FENCE 5
1945#define SDMA_OPCODE_TRAP 6
1946#define SDMA_OPCODE_SEMAPHORE 7
1947# define SDMA_SEMAPHORE_EXTRA_O (1 << 13)
1948 /* 0 - increment
1949 * 1 - write 1
1950 */
1951# define SDMA_SEMAPHORE_EXTRA_S (1 << 14)
1952 /* 0 - wait
1953 * 1 - signal
1954 */
1955# define SDMA_SEMAPHORE_EXTRA_M (1 << 15)
1956 /* mailbox */
1957#define SDMA_OPCODE_POLL_REG_MEM 8
1958# define SDMA_POLL_REG_MEM_EXTRA_OP(x) ((x) << 10)
1959 /* 0 - wait_reg_mem
1960 * 1 - wr_wait_wr_reg
1961 */
1962# define SDMA_POLL_REG_MEM_EXTRA_FUNC(x) ((x) << 12)
1963 /* 0 - always
1964 * 1 - <
1965 * 2 - <=
1966 * 3 - ==
1967 * 4 - !=
1968 * 5 - >=
1969 * 6 - >
1970 */
1971# define SDMA_POLL_REG_MEM_EXTRA_M (1 << 15)
1972 /* 0 = register
1973 * 1 = memory
1974 */
1975#define SDMA_OPCODE_COND_EXEC 9
1976#define SDMA_OPCODE_CONSTANT_FILL 11
1977# define SDMA_CONSTANT_FILL_EXTRA_SIZE(x) ((x) << 14)
1978 /* 0 = byte fill
1979 * 2 = DW fill
1980 */
1981#define SDMA_OPCODE_GENERATE_PTE_PDE 12
1982#define SDMA_OPCODE_TIMESTAMP 13
1983# define SDMA_TIMESTAMP_SUB_OPCODE_SET_LOCAL 0
1984# define SDMA_TIMESTAMP_SUB_OPCODE_GET_LOCAL 1
1985# define SDMA_TIMESTAMP_SUB_OPCODE_GET_GLOBAL 2
1986#define SDMA_OPCODE_SRBM_WRITE 14
1987# define SDMA_SRBM_WRITE_EXTRA_BYTE_ENABLE(x) ((x) << 12)
1988 /* byte mask */
1989
1990/* UVD */
1991
1992#define UVD_UDEC_ADDR_CONFIG 0xef4c
1993#define UVD_UDEC_DB_ADDR_CONFIG 0xef50
1994#define UVD_UDEC_DBW_ADDR_CONFIG 0xef54
1995
1996#define UVD_LMI_EXT40_ADDR 0xf498
1997#define UVD_LMI_ADDR_EXT 0xf594
1998#define UVD_VCPU_CACHE_OFFSET0 0xf608
1999#define UVD_VCPU_CACHE_SIZE0 0xf60c
2000#define UVD_VCPU_CACHE_OFFSET1 0xf610
2001#define UVD_VCPU_CACHE_SIZE1 0xf614
2002#define UVD_VCPU_CACHE_OFFSET2 0xf618
2003#define UVD_VCPU_CACHE_SIZE2 0xf61c
2004
2005#define UVD_RBC_RB_RPTR 0xf690
2006#define UVD_RBC_RB_WPTR 0xf694
2007
2008#define UVD_CGC_CTRL 0xF4B0
2009# define DCM (1 << 0)
2010# define CG_DT(x) ((x) << 2)
2011# define CG_DT_MASK (0xf << 2)
2012# define CLK_OD(x) ((x) << 6)
2013# define CLK_OD_MASK (0x1f << 6)
2014
2015/* UVD clocks */
2016
2017#define CG_DCLK_CNTL 0xC050009C
2018# define DCLK_DIVIDER_MASK 0x7f
2019# define DCLK_DIR_CNTL_EN (1 << 8)
2020#define CG_DCLK_STATUS 0xC05000A0
2021# define DCLK_STATUS (1 << 0)
2022#define CG_VCLK_CNTL 0xC05000A4
2023#define CG_VCLK_STATUS 0xC05000A8
2024
2025/* UVD CTX indirect */
2026#define UVD_CGC_MEM_CTRL 0xC0
2027
2028/* VCE */
2029
2030#define VCE_VCPU_CACHE_OFFSET0 0x20024
2031#define VCE_VCPU_CACHE_SIZE0 0x20028
2032#define VCE_VCPU_CACHE_OFFSET1 0x2002c
2033#define VCE_VCPU_CACHE_SIZE1 0x20030
2034#define VCE_VCPU_CACHE_OFFSET2 0x20034
2035#define VCE_VCPU_CACHE_SIZE2 0x20038
2036#define VCE_RB_RPTR2 0x20178
2037#define VCE_RB_WPTR2 0x2017c
2038#define VCE_RB_RPTR 0x2018c
2039#define VCE_RB_WPTR 0x20190
2040#define VCE_CLOCK_GATING_A 0x202f8
2041# define CGC_CLK_GATE_DLY_TIMER_MASK (0xf << 0)
2042# define CGC_CLK_GATE_DLY_TIMER(x) ((x) << 0)
2043# define CGC_CLK_GATER_OFF_DLY_TIMER_MASK (0xff << 4)
2044# define CGC_CLK_GATER_OFF_DLY_TIMER(x) ((x) << 4)
2045# define CGC_UENC_WAIT_AWAKE (1 << 18)
2046#define VCE_CLOCK_GATING_B 0x202fc
2047#define VCE_CGTT_CLK_OVERRIDE 0x207a0
2048#define VCE_UENC_CLOCK_GATING 0x207bc
2049# define CLOCK_ON_DELAY_MASK (0xf << 0)
2050# define CLOCK_ON_DELAY(x) ((x) << 0)
2051# define CLOCK_OFF_DELAY_MASK (0xff << 4)
2052# define CLOCK_OFF_DELAY(x) ((x) << 4)
2053#define VCE_UENC_REG_CLOCK_GATING 0x207c0
2054#define VCE_SYS_INT_EN 0x21300
2055# define VCE_SYS_INT_TRAP_INTERRUPT_EN (1 << 3)
2056#define VCE_LMI_CTRL2 0x21474
2057#define VCE_LMI_CTRL 0x21498
2058#define VCE_LMI_VM_CTRL 0x214a0
2059#define VCE_LMI_SWAP_CNTL 0x214b4
2060#define VCE_LMI_SWAP_CNTL1 0x214b8
2061#define VCE_LMI_CACHE_CTRL 0x214f4
2062
2063#define VCE_CMD_NO_OP 0x00000000
2064#define VCE_CMD_END 0x00000001
2065#define VCE_CMD_IB 0x00000002
2066#define VCE_CMD_FENCE 0x00000003
2067#define VCE_CMD_TRAP 0x00000004
2068#define VCE_CMD_IB_AUTO 0x00000005
2069#define VCE_CMD_SEMAPHORE 0x00000006
2070
2071#endif