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1/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24#include "i915_drv.h"
25#include "intel_drv.h"
26
27#define FORCEWAKE_ACK_TIMEOUT_MS 2
28
29#define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__))
30#define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__))
31
32#define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__))
33#define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__))
34
35#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
36#define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__))
37
38#define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__))
39#define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__))
40
41#define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__)
42
43static void
44assert_device_not_suspended(struct drm_i915_private *dev_priv)
45{
46 WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended,
47 "Device suspended\n");
48}
49
50static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
51{
52 u32 gt_thread_status_mask;
53
54 if (IS_HASWELL(dev_priv->dev))
55 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
56 else
57 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
58
59 /* w/a for a sporadic read returning 0 by waiting for the GT
60 * thread to wake up.
61 */
62 if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
63 DRM_ERROR("GT thread status wait timed out\n");
64}
65
66static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
67{
68 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
69 /* something from same cacheline, but !FORCEWAKE */
70 __raw_posting_read(dev_priv, ECOBUS);
71}
72
73static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
74 int fw_engine)
75{
76 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
77 FORCEWAKE_ACK_TIMEOUT_MS))
78 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
79
80 __raw_i915_write32(dev_priv, FORCEWAKE, 1);
81 /* something from same cacheline, but !FORCEWAKE */
82 __raw_posting_read(dev_priv, ECOBUS);
83
84 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1),
85 FORCEWAKE_ACK_TIMEOUT_MS))
86 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
87
88 /* WaRsForcewakeWaitTC0:snb */
89 __gen6_gt_wait_for_thread_c0(dev_priv);
90}
91
92static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
93{
94 __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
95 /* something from same cacheline, but !FORCEWAKE_MT */
96 __raw_posting_read(dev_priv, ECOBUS);
97}
98
99static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
100 int fw_engine)
101{
102 u32 forcewake_ack;
103
104 if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev))
105 forcewake_ack = FORCEWAKE_ACK_HSW;
106 else
107 forcewake_ack = FORCEWAKE_MT_ACK;
108
109 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0,
110 FORCEWAKE_ACK_TIMEOUT_MS))
111 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
112
113 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
114 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
115 /* something from same cacheline, but !FORCEWAKE_MT */
116 __raw_posting_read(dev_priv, ECOBUS);
117
118 if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL),
119 FORCEWAKE_ACK_TIMEOUT_MS))
120 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
121
122 /* WaRsForcewakeWaitTC0:ivb,hsw */
123 if (INTEL_INFO(dev_priv->dev)->gen < 8)
124 __gen6_gt_wait_for_thread_c0(dev_priv);
125}
126
127static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
128{
129 u32 gtfifodbg;
130
131 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
132 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
133 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
134}
135
136static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
137 int fw_engine)
138{
139 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
140 /* something from same cacheline, but !FORCEWAKE */
141 __raw_posting_read(dev_priv, ECOBUS);
142 gen6_gt_check_fifodbg(dev_priv);
143}
144
145static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
146 int fw_engine)
147{
148 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
149 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
150 /* something from same cacheline, but !FORCEWAKE_MT */
151 __raw_posting_read(dev_priv, ECOBUS);
152
153 if (IS_GEN7(dev_priv->dev))
154 gen6_gt_check_fifodbg(dev_priv);
155}
156
157static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
158{
159 int ret = 0;
160
161 /* On VLV, FIFO will be shared by both SW and HW.
162 * So, we need to read the FREE_ENTRIES everytime */
163 if (IS_VALLEYVIEW(dev_priv->dev))
164 dev_priv->uncore.fifo_count =
165 __raw_i915_read32(dev_priv, GTFIFOCTL) &
166 GT_FIFO_FREE_ENTRIES_MASK;
167
168 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
169 int loop = 500;
170 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
171 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
172 udelay(10);
173 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
174 }
175 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
176 ++ret;
177 dev_priv->uncore.fifo_count = fifo;
178 }
179 dev_priv->uncore.fifo_count--;
180
181 return ret;
182}
183
184static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
185{
186 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
187 _MASKED_BIT_DISABLE(0xffff));
188 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
189 _MASKED_BIT_DISABLE(0xffff));
190 /* something from same cacheline, but !FORCEWAKE_VLV */
191 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
192}
193
194static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
195 int fw_engine)
196{
197 /* Check for Render Engine */
198 if (FORCEWAKE_RENDER & fw_engine) {
199 if (wait_for_atomic((__raw_i915_read32(dev_priv,
200 FORCEWAKE_ACK_VLV) &
201 FORCEWAKE_KERNEL) == 0,
202 FORCEWAKE_ACK_TIMEOUT_MS))
203 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
204
205 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
206 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
207
208 if (wait_for_atomic((__raw_i915_read32(dev_priv,
209 FORCEWAKE_ACK_VLV) &
210 FORCEWAKE_KERNEL),
211 FORCEWAKE_ACK_TIMEOUT_MS))
212 DRM_ERROR("Timed out: waiting for Render to ack.\n");
213 }
214
215 /* Check for Media Engine */
216 if (FORCEWAKE_MEDIA & fw_engine) {
217 if (wait_for_atomic((__raw_i915_read32(dev_priv,
218 FORCEWAKE_ACK_MEDIA_VLV) &
219 FORCEWAKE_KERNEL) == 0,
220 FORCEWAKE_ACK_TIMEOUT_MS))
221 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
222
223 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
224 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
225
226 if (wait_for_atomic((__raw_i915_read32(dev_priv,
227 FORCEWAKE_ACK_MEDIA_VLV) &
228 FORCEWAKE_KERNEL),
229 FORCEWAKE_ACK_TIMEOUT_MS))
230 DRM_ERROR("Timed out: waiting for media to ack.\n");
231 }
232
233 /* WaRsForcewakeWaitTC0:vlv */
234 __gen6_gt_wait_for_thread_c0(dev_priv);
235
236}
237
238static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
239 int fw_engine)
240{
241
242 /* Check for Render Engine */
243 if (FORCEWAKE_RENDER & fw_engine)
244 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
245 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
246
247
248 /* Check for Media Engine */
249 if (FORCEWAKE_MEDIA & fw_engine)
250 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
251 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
252
253 /* The below doubles as a POSTING_READ */
254 gen6_gt_check_fifodbg(dev_priv);
255
256}
257
258void vlv_force_wake_get(struct drm_i915_private *dev_priv,
259 int fw_engine)
260{
261 unsigned long irqflags;
262
263 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
264
265 if (fw_engine & FORCEWAKE_RENDER &&
266 dev_priv->uncore.fw_rendercount++ != 0)
267 fw_engine &= ~FORCEWAKE_RENDER;
268 if (fw_engine & FORCEWAKE_MEDIA &&
269 dev_priv->uncore.fw_mediacount++ != 0)
270 fw_engine &= ~FORCEWAKE_MEDIA;
271
272 if (fw_engine)
273 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine);
274
275 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
276}
277
278void vlv_force_wake_put(struct drm_i915_private *dev_priv,
279 int fw_engine)
280{
281 unsigned long irqflags;
282
283 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
284
285 if (fw_engine & FORCEWAKE_RENDER) {
286 WARN_ON(!dev_priv->uncore.fw_rendercount);
287 if (--dev_priv->uncore.fw_rendercount != 0)
288 fw_engine &= ~FORCEWAKE_RENDER;
289 }
290
291 if (fw_engine & FORCEWAKE_MEDIA) {
292 WARN_ON(!dev_priv->uncore.fw_mediacount);
293 if (--dev_priv->uncore.fw_mediacount != 0)
294 fw_engine &= ~FORCEWAKE_MEDIA;
295 }
296
297 if (fw_engine)
298 dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine);
299
300 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
301}
302
303static void gen6_force_wake_timer(unsigned long arg)
304{
305 struct drm_i915_private *dev_priv = (void *)arg;
306 unsigned long irqflags;
307
308 assert_device_not_suspended(dev_priv);
309
310 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
311 WARN_ON(!dev_priv->uncore.forcewake_count);
312
313 if (--dev_priv->uncore.forcewake_count == 0)
314 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
315 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
316
317 intel_runtime_pm_put(dev_priv);
318}
319
320static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore)
321{
322 struct drm_i915_private *dev_priv = dev->dev_private;
323 unsigned long irqflags;
324
325 del_timer_sync(&dev_priv->uncore.force_wake_timer);
326
327 /* Hold uncore.lock across reset to prevent any register access
328 * with forcewake not set correctly
329 */
330 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
331
332 if (IS_VALLEYVIEW(dev))
333 vlv_force_wake_reset(dev_priv);
334 else if (IS_GEN6(dev) || IS_GEN7(dev))
335 __gen6_gt_force_wake_reset(dev_priv);
336
337 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev))
338 __gen7_gt_force_wake_mt_reset(dev_priv);
339
340 if (restore) { /* If reset with a user forcewake, try to restore */
341 unsigned fw = 0;
342
343 if (IS_VALLEYVIEW(dev)) {
344 if (dev_priv->uncore.fw_rendercount)
345 fw |= FORCEWAKE_RENDER;
346
347 if (dev_priv->uncore.fw_mediacount)
348 fw |= FORCEWAKE_MEDIA;
349 } else {
350 if (dev_priv->uncore.forcewake_count)
351 fw = FORCEWAKE_ALL;
352 }
353
354 if (fw)
355 dev_priv->uncore.funcs.force_wake_get(dev_priv, fw);
356
357 if (IS_GEN6(dev) || IS_GEN7(dev))
358 dev_priv->uncore.fifo_count =
359 __raw_i915_read32(dev_priv, GTFIFOCTL) &
360 GT_FIFO_FREE_ENTRIES_MASK;
361 } else {
362 dev_priv->uncore.forcewake_count = 0;
363 dev_priv->uncore.fw_rendercount = 0;
364 dev_priv->uncore.fw_mediacount = 0;
365 }
366
367 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
368}
369
370void intel_uncore_early_sanitize(struct drm_device *dev)
371{
372 struct drm_i915_private *dev_priv = dev->dev_private;
373
374 if (HAS_FPGA_DBG_UNCLAIMED(dev))
375 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
376
377 if (IS_HASWELL(dev) &&
378 (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) {
379 /* The docs do not explain exactly how the calculation can be
380 * made. It is somewhat guessable, but for now, it's always
381 * 128MB.
382 * NB: We can't write IDICR yet because we do not have gt funcs
383 * set up */
384 dev_priv->ellc_size = 128;
385 DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size);
386 }
387
388 /* clear out old GT FIFO errors */
389 if (IS_GEN6(dev) || IS_GEN7(dev))
390 __raw_i915_write32(dev_priv, GTFIFODBG,
391 __raw_i915_read32(dev_priv, GTFIFODBG));
392
393 intel_uncore_forcewake_reset(dev, false);
394}
395
396void intel_uncore_sanitize(struct drm_device *dev)
397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 u32 reg_val;
400
401 /* BIOS often leaves RC6 enabled, but disable it for hw init */
402 intel_disable_gt_powersave(dev);
403
404 /* Turn off power gate, require especially for the BIOS less system */
405 if (IS_VALLEYVIEW(dev)) {
406
407 mutex_lock(&dev_priv->rps.hw_lock);
408 reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS);
409
410 if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) |
411 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) |
412 PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D)))
413 vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0);
414
415 mutex_unlock(&dev_priv->rps.hw_lock);
416
417 }
418}
419
420/*
421 * Generally this is called implicitly by the register read function. However,
422 * if some sequence requires the GT to not power down then this function should
423 * be called at the beginning of the sequence followed by a call to
424 * gen6_gt_force_wake_put() at the end of the sequence.
425 */
426void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
427{
428 unsigned long irqflags;
429
430 if (!dev_priv->uncore.funcs.force_wake_get)
431 return;
432
433 intel_runtime_pm_get(dev_priv);
434
435 /* Redirect to VLV specific routine */
436 if (IS_VALLEYVIEW(dev_priv->dev))
437 return vlv_force_wake_get(dev_priv, fw_engine);
438
439 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
440 if (dev_priv->uncore.forcewake_count++ == 0)
441 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
442 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
443}
444
445/*
446 * see gen6_gt_force_wake_get()
447 */
448void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
449{
450 unsigned long irqflags;
451 bool delayed = false;
452
453 if (!dev_priv->uncore.funcs.force_wake_put)
454 return;
455
456 /* Redirect to VLV specific routine */
457 if (IS_VALLEYVIEW(dev_priv->dev)) {
458 vlv_force_wake_put(dev_priv, fw_engine);
459 goto out;
460 }
461
462
463 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
464 WARN_ON(!dev_priv->uncore.forcewake_count);
465
466 if (--dev_priv->uncore.forcewake_count == 0) {
467 dev_priv->uncore.forcewake_count++;
468 delayed = true;
469 mod_timer_pinned(&dev_priv->uncore.force_wake_timer,
470 jiffies + 1);
471 }
472 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
473
474out:
475 if (!delayed)
476 intel_runtime_pm_put(dev_priv);
477}
478
479void assert_force_wake_inactive(struct drm_i915_private *dev_priv)
480{
481 if (!dev_priv->uncore.funcs.force_wake_get)
482 return;
483
484 WARN_ON(dev_priv->uncore.forcewake_count > 0);
485}
486
487/* We give fast paths for the really cool registers */
488#define NEEDS_FORCE_WAKE(dev_priv, reg) \
489 ((reg) < 0x40000 && (reg) != FORCEWAKE)
490
491static void
492ilk_dummy_write(struct drm_i915_private *dev_priv)
493{
494 /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up
495 * the chip from rc6 before touching it for real. MI_MODE is masked,
496 * hence harmless to write 0 into. */
497 __raw_i915_write32(dev_priv, MI_MODE, 0);
498}
499
500static void
501hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
502{
503 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
504 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
505 reg);
506 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
507 }
508}
509
510static void
511hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
512{
513 if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) {
514 DRM_ERROR("Unclaimed write to %x\n", reg);
515 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
516 }
517}
518
519#define REG_READ_HEADER(x) \
520 unsigned long irqflags; \
521 u##x val = 0; \
522 assert_device_not_suspended(dev_priv); \
523 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
524
525#define REG_READ_FOOTER \
526 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
527 trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \
528 return val
529
530#define __gen4_read(x) \
531static u##x \
532gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
533 REG_READ_HEADER(x); \
534 val = __raw_i915_read##x(dev_priv, reg); \
535 REG_READ_FOOTER; \
536}
537
538#define __gen5_read(x) \
539static u##x \
540gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
541 REG_READ_HEADER(x); \
542 ilk_dummy_write(dev_priv); \
543 val = __raw_i915_read##x(dev_priv, reg); \
544 REG_READ_FOOTER; \
545}
546
547#define __gen6_read(x) \
548static u##x \
549gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
550 REG_READ_HEADER(x); \
551 if (dev_priv->uncore.forcewake_count == 0 && \
552 NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
553 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
554 FORCEWAKE_ALL); \
555 val = __raw_i915_read##x(dev_priv, reg); \
556 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
557 FORCEWAKE_ALL); \
558 } else { \
559 val = __raw_i915_read##x(dev_priv, reg); \
560 } \
561 REG_READ_FOOTER; \
562}
563
564#define __vlv_read(x) \
565static u##x \
566vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
567 unsigned fwengine = 0; \
568 REG_READ_HEADER(x); \
569 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
570 if (dev_priv->uncore.fw_rendercount == 0) \
571 fwengine = FORCEWAKE_RENDER; \
572 } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
573 if (dev_priv->uncore.fw_mediacount == 0) \
574 fwengine = FORCEWAKE_MEDIA; \
575 } \
576 if (fwengine) \
577 dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \
578 val = __raw_i915_read##x(dev_priv, reg); \
579 if (fwengine) \
580 dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \
581 REG_READ_FOOTER; \
582}
583
584
585__vlv_read(8)
586__vlv_read(16)
587__vlv_read(32)
588__vlv_read(64)
589__gen6_read(8)
590__gen6_read(16)
591__gen6_read(32)
592__gen6_read(64)
593__gen5_read(8)
594__gen5_read(16)
595__gen5_read(32)
596__gen5_read(64)
597__gen4_read(8)
598__gen4_read(16)
599__gen4_read(32)
600__gen4_read(64)
601
602#undef __vlv_read
603#undef __gen6_read
604#undef __gen5_read
605#undef __gen4_read
606#undef REG_READ_FOOTER
607#undef REG_READ_HEADER
608
609#define REG_WRITE_HEADER \
610 unsigned long irqflags; \
611 trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \
612 assert_device_not_suspended(dev_priv); \
613 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags)
614
615#define REG_WRITE_FOOTER \
616 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags)
617
618#define __gen4_write(x) \
619static void \
620gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
621 REG_WRITE_HEADER; \
622 __raw_i915_write##x(dev_priv, reg, val); \
623 REG_WRITE_FOOTER; \
624}
625
626#define __gen5_write(x) \
627static void \
628gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
629 REG_WRITE_HEADER; \
630 ilk_dummy_write(dev_priv); \
631 __raw_i915_write##x(dev_priv, reg, val); \
632 REG_WRITE_FOOTER; \
633}
634
635#define __gen6_write(x) \
636static void \
637gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
638 u32 __fifo_ret = 0; \
639 REG_WRITE_HEADER; \
640 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
641 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
642 } \
643 __raw_i915_write##x(dev_priv, reg, val); \
644 if (unlikely(__fifo_ret)) { \
645 gen6_gt_check_fifodbg(dev_priv); \
646 } \
647 REG_WRITE_FOOTER; \
648}
649
650#define __hsw_write(x) \
651static void \
652hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
653 u32 __fifo_ret = 0; \
654 REG_WRITE_HEADER; \
655 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
656 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
657 } \
658 hsw_unclaimed_reg_clear(dev_priv, reg); \
659 __raw_i915_write##x(dev_priv, reg, val); \
660 if (unlikely(__fifo_ret)) { \
661 gen6_gt_check_fifodbg(dev_priv); \
662 } \
663 hsw_unclaimed_reg_check(dev_priv, reg); \
664 REG_WRITE_FOOTER; \
665}
666
667static const u32 gen8_shadowed_regs[] = {
668 FORCEWAKE_MT,
669 GEN6_RPNSWREQ,
670 GEN6_RC_VIDEO_FREQ,
671 RING_TAIL(RENDER_RING_BASE),
672 RING_TAIL(GEN6_BSD_RING_BASE),
673 RING_TAIL(VEBOX_RING_BASE),
674 RING_TAIL(BLT_RING_BASE),
675 /* TODO: Other registers are not yet used */
676};
677
678static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg)
679{
680 int i;
681 for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++)
682 if (reg == gen8_shadowed_regs[i])
683 return true;
684
685 return false;
686}
687
688#define __gen8_write(x) \
689static void \
690gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \
691 REG_WRITE_HEADER; \
692 if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \
693 if (dev_priv->uncore.forcewake_count == 0) \
694 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
695 FORCEWAKE_ALL); \
696 __raw_i915_write##x(dev_priv, reg, val); \
697 if (dev_priv->uncore.forcewake_count == 0) \
698 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
699 FORCEWAKE_ALL); \
700 } else { \
701 __raw_i915_write##x(dev_priv, reg, val); \
702 } \
703 REG_WRITE_FOOTER; \
704}
705
706__gen8_write(8)
707__gen8_write(16)
708__gen8_write(32)
709__gen8_write(64)
710__hsw_write(8)
711__hsw_write(16)
712__hsw_write(32)
713__hsw_write(64)
714__gen6_write(8)
715__gen6_write(16)
716__gen6_write(32)
717__gen6_write(64)
718__gen5_write(8)
719__gen5_write(16)
720__gen5_write(32)
721__gen5_write(64)
722__gen4_write(8)
723__gen4_write(16)
724__gen4_write(32)
725__gen4_write(64)
726
727#undef __gen8_write
728#undef __hsw_write
729#undef __gen6_write
730#undef __gen5_write
731#undef __gen4_write
732#undef REG_WRITE_FOOTER
733#undef REG_WRITE_HEADER
734
735void intel_uncore_init(struct drm_device *dev)
736{
737 struct drm_i915_private *dev_priv = dev->dev_private;
738
739 setup_timer(&dev_priv->uncore.force_wake_timer,
740 gen6_force_wake_timer, (unsigned long)dev_priv);
741
742 intel_uncore_early_sanitize(dev);
743
744 if (IS_VALLEYVIEW(dev)) {
745 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
746 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
747 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
748 dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get;
749 dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put;
750 } else if (IS_IVYBRIDGE(dev)) {
751 u32 ecobus;
752
753 /* IVB configs may use multi-threaded forcewake */
754
755 /* A small trick here - if the bios hasn't configured
756 * MT forcewake, and if the device is in RC6, then
757 * force_wake_mt_get will not wake the device and the
758 * ECOBUS read will return zero. Which will be
759 * (correctly) interpreted by the test below as MT
760 * forcewake being disabled.
761 */
762 mutex_lock(&dev->struct_mutex);
763 __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
764 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
765 __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
766 mutex_unlock(&dev->struct_mutex);
767
768 if (ecobus & FORCEWAKE_MT_ENABLE) {
769 dev_priv->uncore.funcs.force_wake_get =
770 __gen7_gt_force_wake_mt_get;
771 dev_priv->uncore.funcs.force_wake_put =
772 __gen7_gt_force_wake_mt_put;
773 } else {
774 DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n");
775 DRM_INFO("when using vblank-synced partial screen updates.\n");
776 dev_priv->uncore.funcs.force_wake_get =
777 __gen6_gt_force_wake_get;
778 dev_priv->uncore.funcs.force_wake_put =
779 __gen6_gt_force_wake_put;
780 }
781 } else if (IS_GEN6(dev)) {
782 dev_priv->uncore.funcs.force_wake_get =
783 __gen6_gt_force_wake_get;
784 dev_priv->uncore.funcs.force_wake_put =
785 __gen6_gt_force_wake_put;
786 }
787
788 switch (INTEL_INFO(dev)->gen) {
789 default:
790 dev_priv->uncore.funcs.mmio_writeb = gen8_write8;
791 dev_priv->uncore.funcs.mmio_writew = gen8_write16;
792 dev_priv->uncore.funcs.mmio_writel = gen8_write32;
793 dev_priv->uncore.funcs.mmio_writeq = gen8_write64;
794 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
795 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
796 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
797 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
798 break;
799 case 7:
800 case 6:
801 if (IS_HASWELL(dev)) {
802 dev_priv->uncore.funcs.mmio_writeb = hsw_write8;
803 dev_priv->uncore.funcs.mmio_writew = hsw_write16;
804 dev_priv->uncore.funcs.mmio_writel = hsw_write32;
805 dev_priv->uncore.funcs.mmio_writeq = hsw_write64;
806 } else {
807 dev_priv->uncore.funcs.mmio_writeb = gen6_write8;
808 dev_priv->uncore.funcs.mmio_writew = gen6_write16;
809 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
810 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
811 }
812
813 if (IS_VALLEYVIEW(dev)) {
814 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
815 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
816 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
817 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
818 } else {
819 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
820 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
821 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
822 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
823 }
824 break;
825 case 5:
826 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
827 dev_priv->uncore.funcs.mmio_writew = gen5_write16;
828 dev_priv->uncore.funcs.mmio_writel = gen5_write32;
829 dev_priv->uncore.funcs.mmio_writeq = gen5_write64;
830 dev_priv->uncore.funcs.mmio_readb = gen5_read8;
831 dev_priv->uncore.funcs.mmio_readw = gen5_read16;
832 dev_priv->uncore.funcs.mmio_readl = gen5_read32;
833 dev_priv->uncore.funcs.mmio_readq = gen5_read64;
834 break;
835 case 4:
836 case 3:
837 case 2:
838 dev_priv->uncore.funcs.mmio_writeb = gen4_write8;
839 dev_priv->uncore.funcs.mmio_writew = gen4_write16;
840 dev_priv->uncore.funcs.mmio_writel = gen4_write32;
841 dev_priv->uncore.funcs.mmio_writeq = gen4_write64;
842 dev_priv->uncore.funcs.mmio_readb = gen4_read8;
843 dev_priv->uncore.funcs.mmio_readw = gen4_read16;
844 dev_priv->uncore.funcs.mmio_readl = gen4_read32;
845 dev_priv->uncore.funcs.mmio_readq = gen4_read64;
846 break;
847 }
848}
849
850void intel_uncore_fini(struct drm_device *dev)
851{
852 /* Paranoia: make sure we have disabled everything before we exit. */
853 intel_uncore_sanitize(dev);
854 intel_uncore_forcewake_reset(dev, false);
855}
856
857static const struct register_whitelist {
858 uint64_t offset;
859 uint32_t size;
860 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
861} whitelist[] = {
862 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 },
863};
864
865int i915_reg_read_ioctl(struct drm_device *dev,
866 void *data, struct drm_file *file)
867{
868 struct drm_i915_private *dev_priv = dev->dev_private;
869 struct drm_i915_reg_read *reg = data;
870 struct register_whitelist const *entry = whitelist;
871 int i, ret = 0;
872
873 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
874 if (entry->offset == reg->offset &&
875 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
876 break;
877 }
878
879 if (i == ARRAY_SIZE(whitelist))
880 return -EINVAL;
881
882 intel_runtime_pm_get(dev_priv);
883
884 switch (entry->size) {
885 case 8:
886 reg->val = I915_READ64(reg->offset);
887 break;
888 case 4:
889 reg->val = I915_READ(reg->offset);
890 break;
891 case 2:
892 reg->val = I915_READ16(reg->offset);
893 break;
894 case 1:
895 reg->val = I915_READ8(reg->offset);
896 break;
897 default:
898 WARN_ON(1);
899 ret = -EINVAL;
900 goto out;
901 }
902
903out:
904 intel_runtime_pm_put(dev_priv);
905 return ret;
906}
907
908int i915_get_reset_stats_ioctl(struct drm_device *dev,
909 void *data, struct drm_file *file)
910{
911 struct drm_i915_private *dev_priv = dev->dev_private;
912 struct drm_i915_reset_stats *args = data;
913 struct i915_ctx_hang_stats *hs;
914 struct i915_hw_context *ctx;
915 int ret;
916
917 if (args->flags || args->pad)
918 return -EINVAL;
919
920 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
921 return -EPERM;
922
923 ret = mutex_lock_interruptible(&dev->struct_mutex);
924 if (ret)
925 return ret;
926
927 ctx = i915_gem_context_get(file->driver_priv, args->ctx_id);
928 if (IS_ERR(ctx)) {
929 mutex_unlock(&dev->struct_mutex);
930 return PTR_ERR(ctx);
931 }
932 hs = &ctx->hang_stats;
933
934 if (capable(CAP_SYS_ADMIN))
935 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
936 else
937 args->reset_count = 0;
938
939 args->batch_active = hs->batch_active;
940 args->batch_pending = hs->batch_pending;
941
942 mutex_unlock(&dev->struct_mutex);
943
944 return 0;
945}
946
947static int i965_reset_complete(struct drm_device *dev)
948{
949 u8 gdrst;
950 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
951 return (gdrst & GRDOM_RESET_ENABLE) == 0;
952}
953
954static int i965_do_reset(struct drm_device *dev)
955{
956 int ret;
957
958 /*
959 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
960 * well as the reset bit (GR/bit 0). Setting the GR bit
961 * triggers the reset; when done, the hardware will clear it.
962 */
963 pci_write_config_byte(dev->pdev, I965_GDRST,
964 GRDOM_RENDER | GRDOM_RESET_ENABLE);
965 ret = wait_for(i965_reset_complete(dev), 500);
966 if (ret)
967 return ret;
968
969 /* We can't reset render&media without also resetting display ... */
970 pci_write_config_byte(dev->pdev, I965_GDRST,
971 GRDOM_MEDIA | GRDOM_RESET_ENABLE);
972
973 ret = wait_for(i965_reset_complete(dev), 500);
974 if (ret)
975 return ret;
976
977 pci_write_config_byte(dev->pdev, I965_GDRST, 0);
978
979 return 0;
980}
981
982static int ironlake_do_reset(struct drm_device *dev)
983{
984 struct drm_i915_private *dev_priv = dev->dev_private;
985 u32 gdrst;
986 int ret;
987
988 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
989 gdrst &= ~GRDOM_MASK;
990 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
991 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
992 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
993 if (ret)
994 return ret;
995
996 /* We can't reset render&media without also resetting display ... */
997 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
998 gdrst &= ~GRDOM_MASK;
999 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
1000 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
1001 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
1002}
1003
1004static int gen6_do_reset(struct drm_device *dev)
1005{
1006 struct drm_i915_private *dev_priv = dev->dev_private;
1007 int ret;
1008
1009 /* Reset the chip */
1010
1011 /* GEN6_GDRST is not in the gt power well, no need to check
1012 * for fifo space for the write or forcewake the chip for
1013 * the read
1014 */
1015 __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL);
1016
1017 /* Spin waiting for the device to ack the reset request */
1018 ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
1019
1020 intel_uncore_forcewake_reset(dev, true);
1021
1022 return ret;
1023}
1024
1025int intel_gpu_reset(struct drm_device *dev)
1026{
1027 switch (INTEL_INFO(dev)->gen) {
1028 case 8:
1029 case 7:
1030 case 6: return gen6_do_reset(dev);
1031 case 5: return ironlake_do_reset(dev);
1032 case 4: return i965_do_reset(dev);
1033 default: return -ENODEV;
1034 }
1035}
1036
1037void intel_uncore_check_errors(struct drm_device *dev)
1038{
1039 struct drm_i915_private *dev_priv = dev->dev_private;
1040
1041 if (HAS_FPGA_DBG_UNCLAIMED(dev) &&
1042 (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1043 DRM_ERROR("Unclaimed register before interrupt\n");
1044 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1045 }
1046}