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1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/kernel.h>
18#include <linux/slab.h>
19#include <linux/pci.h>
20#include <linux/gpio.h>
21
22#define PCI_VENDOR_ID_ROHM 0x10DB
23
24struct ioh_reg_comn {
25 u32 ien;
26 u32 istatus;
27 u32 idisp;
28 u32 iclr;
29 u32 imask;
30 u32 imaskclr;
31 u32 po;
32 u32 pi;
33 u32 pm;
34 u32 im_0;
35 u32 im_1;
36 u32 reserved;
37};
38
39struct ioh_regs {
40 struct ioh_reg_comn regs[8];
41 u32 reserve1[16];
42 u32 ioh_sel_reg[4];
43 u32 reserve2[11];
44 u32 srst;
45};
46
47/**
48 * struct ioh_gpio_reg_data - The register store data.
49 * @po_reg: To store contents of PO register.
50 * @pm_reg: To store contents of PM register.
51 */
52struct ioh_gpio_reg_data {
53 u32 po_reg;
54 u32 pm_reg;
55};
56
57/**
58 * struct ioh_gpio - GPIO private data structure.
59 * @base: PCI base address of Memory mapped I/O register.
60 * @reg: Memory mapped IOH GPIO register list.
61 * @dev: Pointer to device structure.
62 * @gpio: Data for GPIO infrastructure.
63 * @ioh_gpio_reg: Memory mapped Register data is saved here
64 * when suspend.
65 * @ch: Indicate GPIO channel
66 */
67struct ioh_gpio {
68 void __iomem *base;
69 struct ioh_regs __iomem *reg;
70 struct device *dev;
71 struct gpio_chip gpio;
72 struct ioh_gpio_reg_data ioh_gpio_reg;
73 struct mutex lock;
74 int ch;
75};
76
77static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
78
79static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
80{
81 u32 reg_val;
82 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
83
84 mutex_lock(&chip->lock);
85 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
86 if (val)
87 reg_val |= (1 << nr);
88 else
89 reg_val &= ~(1 << nr);
90
91 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
92 mutex_unlock(&chip->lock);
93}
94
95static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
96{
97 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
98
99 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
100}
101
102static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
103 int val)
104{
105 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
106 u32 pm;
107 u32 reg_val;
108
109 mutex_lock(&chip->lock);
110 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
111 ((1 << num_ports[chip->ch]) - 1);
112 pm |= (1 << nr);
113 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
114
115 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
116 if (val)
117 reg_val |= (1 << nr);
118 else
119 reg_val &= ~(1 << nr);
120 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
121
122 mutex_unlock(&chip->lock);
123
124 return 0;
125}
126
127static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
128{
129 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
130 u32 pm;
131
132 mutex_lock(&chip->lock);
133 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
134 ((1 << num_ports[chip->ch]) - 1);
135 pm &= ~(1 << nr);
136 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
137 mutex_unlock(&chip->lock);
138
139 return 0;
140}
141
142#ifdef CONFIG_PM
143/*
144 * Save register configuration and disable interrupts.
145 */
146static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
147{
148 chip->ioh_gpio_reg.po_reg = ioread32(&chip->reg->regs[chip->ch].po);
149 chip->ioh_gpio_reg.pm_reg = ioread32(&chip->reg->regs[chip->ch].pm);
150}
151
152/*
153 * This function restores the register configuration of the GPIO device.
154 */
155static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
156{
157 /* to store contents of PO register */
158 iowrite32(chip->ioh_gpio_reg.po_reg, &chip->reg->regs[chip->ch].po);
159 /* to store contents of PM register */
160 iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
161}
162#endif
163
164static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
165{
166 struct gpio_chip *gpio = &chip->gpio;
167
168 gpio->label = dev_name(chip->dev);
169 gpio->owner = THIS_MODULE;
170 gpio->direction_input = ioh_gpio_direction_input;
171 gpio->get = ioh_gpio_get;
172 gpio->direction_output = ioh_gpio_direction_output;
173 gpio->set = ioh_gpio_set;
174 gpio->dbg_show = NULL;
175 gpio->base = -1;
176 gpio->ngpio = num_port;
177 gpio->can_sleep = 0;
178}
179
180static int __devinit ioh_gpio_probe(struct pci_dev *pdev,
181 const struct pci_device_id *id)
182{
183 int ret;
184 int i;
185 struct ioh_gpio *chip;
186 void __iomem *base;
187 void __iomem *chip_save;
188
189 ret = pci_enable_device(pdev);
190 if (ret) {
191 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
192 goto err_pci_enable;
193 }
194
195 ret = pci_request_regions(pdev, KBUILD_MODNAME);
196 if (ret) {
197 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
198 goto err_request_regions;
199 }
200
201 base = pci_iomap(pdev, 1, 0);
202 if (base == 0) {
203 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
204 ret = -ENOMEM;
205 goto err_iomap;
206 }
207
208 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
209 if (chip_save == NULL) {
210 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
211 ret = -ENOMEM;
212 goto err_kzalloc;
213 }
214
215 chip = chip_save;
216 for (i = 0; i < 8; i++, chip++) {
217 chip->dev = &pdev->dev;
218 chip->base = base;
219 chip->reg = chip->base;
220 chip->ch = i;
221 mutex_init(&chip->lock);
222 ioh_gpio_setup(chip, num_ports[i]);
223 ret = gpiochip_add(&chip->gpio);
224 if (ret) {
225 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
226 goto err_gpiochip_add;
227 }
228 }
229
230 chip = chip_save;
231 pci_set_drvdata(pdev, chip);
232
233 return 0;
234
235err_gpiochip_add:
236 while (--i >= 0) {
237 chip--;
238 ret = gpiochip_remove(&chip->gpio);
239 if (ret)
240 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
241 }
242 kfree(chip_save);
243
244err_kzalloc:
245 pci_iounmap(pdev, base);
246
247err_iomap:
248 pci_release_regions(pdev);
249
250err_request_regions:
251 pci_disable_device(pdev);
252
253err_pci_enable:
254
255 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
256 return ret;
257}
258
259static void __devexit ioh_gpio_remove(struct pci_dev *pdev)
260{
261 int err;
262 int i;
263 struct ioh_gpio *chip = pci_get_drvdata(pdev);
264 void __iomem *chip_save;
265
266 chip_save = chip;
267 for (i = 0; i < 8; i++, chip++) {
268 err = gpiochip_remove(&chip->gpio);
269 if (err)
270 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
271 }
272
273 chip = chip_save;
274 pci_iounmap(pdev, chip->base);
275 pci_release_regions(pdev);
276 pci_disable_device(pdev);
277 kfree(chip);
278}
279
280#ifdef CONFIG_PM
281static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
282{
283 s32 ret;
284 struct ioh_gpio *chip = pci_get_drvdata(pdev);
285
286 ioh_gpio_save_reg_conf(chip);
287 ioh_gpio_restore_reg_conf(chip);
288
289 ret = pci_save_state(pdev);
290 if (ret) {
291 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
292 return ret;
293 }
294 pci_disable_device(pdev);
295 pci_set_power_state(pdev, PCI_D0);
296 ret = pci_enable_wake(pdev, PCI_D0, 1);
297 if (ret)
298 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
299
300 return 0;
301}
302
303static int ioh_gpio_resume(struct pci_dev *pdev)
304{
305 s32 ret;
306 struct ioh_gpio *chip = pci_get_drvdata(pdev);
307
308 ret = pci_enable_wake(pdev, PCI_D0, 0);
309
310 pci_set_power_state(pdev, PCI_D0);
311 ret = pci_enable_device(pdev);
312 if (ret) {
313 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
314 return ret;
315 }
316 pci_restore_state(pdev);
317
318 iowrite32(0x01, &chip->reg->srst);
319 iowrite32(0x00, &chip->reg->srst);
320 ioh_gpio_restore_reg_conf(chip);
321
322 return 0;
323}
324#else
325#define ioh_gpio_suspend NULL
326#define ioh_gpio_resume NULL
327#endif
328
329static DEFINE_PCI_DEVICE_TABLE(ioh_gpio_pcidev_id) = {
330 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
331 { 0, }
332};
333MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
334
335static struct pci_driver ioh_gpio_driver = {
336 .name = "ml_ioh_gpio",
337 .id_table = ioh_gpio_pcidev_id,
338 .probe = ioh_gpio_probe,
339 .remove = __devexit_p(ioh_gpio_remove),
340 .suspend = ioh_gpio_suspend,
341 .resume = ioh_gpio_resume
342};
343
344static int __init ioh_gpio_pci_init(void)
345{
346 return pci_register_driver(&ioh_gpio_driver);
347}
348module_init(ioh_gpio_pci_init);
349
350static void __exit ioh_gpio_pci_exit(void)
351{
352 pci_unregister_driver(&ioh_gpio_driver);
353}
354module_exit(ioh_gpio_pci_exit);
355
356MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
357MODULE_LICENSE("GPL");
1/*
2 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
16 */
17#include <linux/module.h>
18#include <linux/kernel.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/gpio.h>
22#include <linux/interrupt.h>
23#include <linux/irq.h>
24
25#define IOH_EDGE_FALLING 0
26#define IOH_EDGE_RISING BIT(0)
27#define IOH_LEVEL_L BIT(1)
28#define IOH_LEVEL_H (BIT(0) | BIT(1))
29#define IOH_EDGE_BOTH BIT(2)
30#define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2))
31
32#define IOH_IRQ_BASE 0
33
34#define PCI_VENDOR_ID_ROHM 0x10DB
35
36struct ioh_reg_comn {
37 u32 ien;
38 u32 istatus;
39 u32 idisp;
40 u32 iclr;
41 u32 imask;
42 u32 imaskclr;
43 u32 po;
44 u32 pi;
45 u32 pm;
46 u32 im_0;
47 u32 im_1;
48 u32 reserved;
49};
50
51struct ioh_regs {
52 struct ioh_reg_comn regs[8];
53 u32 reserve1[16];
54 u32 ioh_sel_reg[4];
55 u32 reserve2[11];
56 u32 srst;
57};
58
59/**
60 * struct ioh_gpio_reg_data - The register store data.
61 * @ien_reg To store contents of interrupt enable register.
62 * @imask_reg: To store contents of interrupt mask regist
63 * @po_reg: To store contents of PO register.
64 * @pm_reg: To store contents of PM register.
65 * @im0_reg: To store contents of interrupt mode regist0
66 * @im1_reg: To store contents of interrupt mode regist1
67 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3
68 */
69struct ioh_gpio_reg_data {
70 u32 ien_reg;
71 u32 imask_reg;
72 u32 po_reg;
73 u32 pm_reg;
74 u32 im0_reg;
75 u32 im1_reg;
76 u32 use_sel_reg;
77};
78
79/**
80 * struct ioh_gpio - GPIO private data structure.
81 * @base: PCI base address of Memory mapped I/O register.
82 * @reg: Memory mapped IOH GPIO register list.
83 * @dev: Pointer to device structure.
84 * @gpio: Data for GPIO infrastructure.
85 * @ioh_gpio_reg: Memory mapped Register data is saved here
86 * when suspend.
87 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM
88 * @ch: Indicate GPIO channel
89 * @irq_base: Save base of IRQ number for interrupt
90 * @spinlock: Used for register access protection
91 */
92struct ioh_gpio {
93 void __iomem *base;
94 struct ioh_regs __iomem *reg;
95 struct device *dev;
96 struct gpio_chip gpio;
97 struct ioh_gpio_reg_data ioh_gpio_reg;
98 u32 gpio_use_sel;
99 int ch;
100 int irq_base;
101 spinlock_t spinlock;
102};
103
104static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12};
105
106static void ioh_gpio_set(struct gpio_chip *gpio, unsigned nr, int val)
107{
108 u32 reg_val;
109 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
110 unsigned long flags;
111
112 spin_lock_irqsave(&chip->spinlock, flags);
113 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
114 if (val)
115 reg_val |= (1 << nr);
116 else
117 reg_val &= ~(1 << nr);
118
119 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
120 spin_unlock_irqrestore(&chip->spinlock, flags);
121}
122
123static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr)
124{
125 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
126
127 return ioread32(&chip->reg->regs[chip->ch].pi) & (1 << nr);
128}
129
130static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr,
131 int val)
132{
133 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
134 u32 pm;
135 u32 reg_val;
136 unsigned long flags;
137
138 spin_lock_irqsave(&chip->spinlock, flags);
139 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
140 ((1 << num_ports[chip->ch]) - 1);
141 pm |= (1 << nr);
142 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
143
144 reg_val = ioread32(&chip->reg->regs[chip->ch].po);
145 if (val)
146 reg_val |= (1 << nr);
147 else
148 reg_val &= ~(1 << nr);
149 iowrite32(reg_val, &chip->reg->regs[chip->ch].po);
150
151 spin_unlock_irqrestore(&chip->spinlock, flags);
152
153 return 0;
154}
155
156static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr)
157{
158 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
159 u32 pm;
160 unsigned long flags;
161
162 spin_lock_irqsave(&chip->spinlock, flags);
163 pm = ioread32(&chip->reg->regs[chip->ch].pm) &
164 ((1 << num_ports[chip->ch]) - 1);
165 pm &= ~(1 << nr);
166 iowrite32(pm, &chip->reg->regs[chip->ch].pm);
167 spin_unlock_irqrestore(&chip->spinlock, flags);
168
169 return 0;
170}
171
172#ifdef CONFIG_PM
173/*
174 * Save register configuration and disable interrupts.
175 */
176static void ioh_gpio_save_reg_conf(struct ioh_gpio *chip)
177{
178 int i;
179
180 for (i = 0; i < 8; i ++, chip++) {
181 chip->ioh_gpio_reg.po_reg =
182 ioread32(&chip->reg->regs[chip->ch].po);
183 chip->ioh_gpio_reg.pm_reg =
184 ioread32(&chip->reg->regs[chip->ch].pm);
185 chip->ioh_gpio_reg.ien_reg =
186 ioread32(&chip->reg->regs[chip->ch].ien);
187 chip->ioh_gpio_reg.imask_reg =
188 ioread32(&chip->reg->regs[chip->ch].imask);
189 chip->ioh_gpio_reg.im0_reg =
190 ioread32(&chip->reg->regs[chip->ch].im_0);
191 chip->ioh_gpio_reg.im1_reg =
192 ioread32(&chip->reg->regs[chip->ch].im_1);
193 if (i < 4)
194 chip->ioh_gpio_reg.use_sel_reg =
195 ioread32(&chip->reg->ioh_sel_reg[i]);
196 }
197}
198
199/*
200 * This function restores the register configuration of the GPIO device.
201 */
202static void ioh_gpio_restore_reg_conf(struct ioh_gpio *chip)
203{
204 int i;
205
206 for (i = 0; i < 8; i ++, chip++) {
207 iowrite32(chip->ioh_gpio_reg.po_reg,
208 &chip->reg->regs[chip->ch].po);
209 iowrite32(chip->ioh_gpio_reg.pm_reg,
210 &chip->reg->regs[chip->ch].pm);
211 iowrite32(chip->ioh_gpio_reg.ien_reg,
212 &chip->reg->regs[chip->ch].ien);
213 iowrite32(chip->ioh_gpio_reg.imask_reg,
214 &chip->reg->regs[chip->ch].imask);
215 iowrite32(chip->ioh_gpio_reg.im0_reg,
216 &chip->reg->regs[chip->ch].im_0);
217 iowrite32(chip->ioh_gpio_reg.im1_reg,
218 &chip->reg->regs[chip->ch].im_1);
219 if (i < 4)
220 iowrite32(chip->ioh_gpio_reg.use_sel_reg,
221 &chip->reg->ioh_sel_reg[i]);
222 }
223}
224#endif
225
226static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset)
227{
228 struct ioh_gpio *chip = container_of(gpio, struct ioh_gpio, gpio);
229 return chip->irq_base + offset;
230}
231
232static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
233{
234 struct gpio_chip *gpio = &chip->gpio;
235
236 gpio->label = dev_name(chip->dev);
237 gpio->owner = THIS_MODULE;
238 gpio->direction_input = ioh_gpio_direction_input;
239 gpio->get = ioh_gpio_get;
240 gpio->direction_output = ioh_gpio_direction_output;
241 gpio->set = ioh_gpio_set;
242 gpio->dbg_show = NULL;
243 gpio->base = -1;
244 gpio->ngpio = num_port;
245 gpio->can_sleep = false;
246 gpio->to_irq = ioh_gpio_to_irq;
247}
248
249static int ioh_irq_type(struct irq_data *d, unsigned int type)
250{
251 u32 im;
252 void __iomem *im_reg;
253 u32 ien;
254 u32 im_pos;
255 int ch;
256 unsigned long flags;
257 u32 val;
258 int irq = d->irq;
259 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
260 struct ioh_gpio *chip = gc->private;
261
262 ch = irq - chip->irq_base;
263 if (irq <= chip->irq_base + 7) {
264 im_reg = &chip->reg->regs[chip->ch].im_0;
265 im_pos = ch;
266 } else {
267 im_reg = &chip->reg->regs[chip->ch].im_1;
268 im_pos = ch - 8;
269 }
270 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n",
271 __func__, irq, type, ch, im_pos, type);
272
273 spin_lock_irqsave(&chip->spinlock, flags);
274
275 switch (type) {
276 case IRQ_TYPE_EDGE_RISING:
277 val = IOH_EDGE_RISING;
278 break;
279 case IRQ_TYPE_EDGE_FALLING:
280 val = IOH_EDGE_FALLING;
281 break;
282 case IRQ_TYPE_EDGE_BOTH:
283 val = IOH_EDGE_BOTH;
284 break;
285 case IRQ_TYPE_LEVEL_HIGH:
286 val = IOH_LEVEL_H;
287 break;
288 case IRQ_TYPE_LEVEL_LOW:
289 val = IOH_LEVEL_L;
290 break;
291 case IRQ_TYPE_PROBE:
292 goto end;
293 default:
294 dev_warn(chip->dev, "%s: unknown type(%dd)",
295 __func__, type);
296 goto end;
297 }
298
299 /* Set interrupt mode */
300 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4));
301 iowrite32(im | (val << (im_pos * 4)), im_reg);
302
303 /* iclr */
304 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);
305
306 /* IMASKCLR */
307 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);
308
309 /* Enable interrupt */
310 ien = ioread32(&chip->reg->regs[chip->ch].ien);
311 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);
312end:
313 spin_unlock_irqrestore(&chip->spinlock, flags);
314
315 return 0;
316}
317
318static void ioh_irq_unmask(struct irq_data *d)
319{
320 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
321 struct ioh_gpio *chip = gc->private;
322
323 iowrite32(1 << (d->irq - chip->irq_base),
324 &chip->reg->regs[chip->ch].imaskclr);
325}
326
327static void ioh_irq_mask(struct irq_data *d)
328{
329 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
330 struct ioh_gpio *chip = gc->private;
331
332 iowrite32(1 << (d->irq - chip->irq_base),
333 &chip->reg->regs[chip->ch].imask);
334}
335
336static void ioh_irq_disable(struct irq_data *d)
337{
338 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
339 struct ioh_gpio *chip = gc->private;
340 unsigned long flags;
341 u32 ien;
342
343 spin_lock_irqsave(&chip->spinlock, flags);
344 ien = ioread32(&chip->reg->regs[chip->ch].ien);
345 ien &= ~(1 << (d->irq - chip->irq_base));
346 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
347 spin_unlock_irqrestore(&chip->spinlock, flags);
348}
349
350static void ioh_irq_enable(struct irq_data *d)
351{
352 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
353 struct ioh_gpio *chip = gc->private;
354 unsigned long flags;
355 u32 ien;
356
357 spin_lock_irqsave(&chip->spinlock, flags);
358 ien = ioread32(&chip->reg->regs[chip->ch].ien);
359 ien |= 1 << (d->irq - chip->irq_base);
360 iowrite32(ien, &chip->reg->regs[chip->ch].ien);
361 spin_unlock_irqrestore(&chip->spinlock, flags);
362}
363
364static irqreturn_t ioh_gpio_handler(int irq, void *dev_id)
365{
366 struct ioh_gpio *chip = dev_id;
367 u32 reg_val;
368 int i, j;
369 int ret = IRQ_NONE;
370
371 for (i = 0; i < 8; i++, chip++) {
372 reg_val = ioread32(&chip->reg->regs[i].istatus);
373 for (j = 0; j < num_ports[i]; j++) {
374 if (reg_val & BIT(j)) {
375 dev_dbg(chip->dev,
376 "%s:[%d]:irq=%d status=0x%x\n",
377 __func__, j, irq, reg_val);
378 iowrite32(BIT(j),
379 &chip->reg->regs[chip->ch].iclr);
380 generic_handle_irq(chip->irq_base + j);
381 ret = IRQ_HANDLED;
382 }
383 }
384 }
385 return ret;
386}
387
388static void ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip,
389 unsigned int irq_start, unsigned int num)
390{
391 struct irq_chip_generic *gc;
392 struct irq_chip_type *ct;
393
394 gc = irq_alloc_generic_chip("ioh_gpio", 1, irq_start, chip->base,
395 handle_simple_irq);
396 gc->private = chip;
397 ct = gc->chip_types;
398
399 ct->chip.irq_mask = ioh_irq_mask;
400 ct->chip.irq_unmask = ioh_irq_unmask;
401 ct->chip.irq_set_type = ioh_irq_type;
402 ct->chip.irq_disable = ioh_irq_disable;
403 ct->chip.irq_enable = ioh_irq_enable;
404
405 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
406 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
407}
408
409static int ioh_gpio_probe(struct pci_dev *pdev,
410 const struct pci_device_id *id)
411{
412 int ret;
413 int i, j;
414 struct ioh_gpio *chip;
415 void __iomem *base;
416 void *chip_save;
417 int irq_base;
418
419 ret = pci_enable_device(pdev);
420 if (ret) {
421 dev_err(&pdev->dev, "%s : pci_enable_device failed", __func__);
422 goto err_pci_enable;
423 }
424
425 ret = pci_request_regions(pdev, KBUILD_MODNAME);
426 if (ret) {
427 dev_err(&pdev->dev, "pci_request_regions failed-%d", ret);
428 goto err_request_regions;
429 }
430
431 base = pci_iomap(pdev, 1, 0);
432 if (!base) {
433 dev_err(&pdev->dev, "%s : pci_iomap failed", __func__);
434 ret = -ENOMEM;
435 goto err_iomap;
436 }
437
438 chip_save = kzalloc(sizeof(*chip) * 8, GFP_KERNEL);
439 if (chip_save == NULL) {
440 dev_err(&pdev->dev, "%s : kzalloc failed", __func__);
441 ret = -ENOMEM;
442 goto err_kzalloc;
443 }
444
445 chip = chip_save;
446 for (i = 0; i < 8; i++, chip++) {
447 chip->dev = &pdev->dev;
448 chip->base = base;
449 chip->reg = chip->base;
450 chip->ch = i;
451 spin_lock_init(&chip->spinlock);
452 ioh_gpio_setup(chip, num_ports[i]);
453 ret = gpiochip_add(&chip->gpio);
454 if (ret) {
455 dev_err(&pdev->dev, "IOH gpio: Failed to register GPIO\n");
456 goto err_gpiochip_add;
457 }
458 }
459
460 chip = chip_save;
461 for (j = 0; j < 8; j++, chip++) {
462 irq_base = irq_alloc_descs(-1, IOH_IRQ_BASE, num_ports[j],
463 NUMA_NO_NODE);
464 if (irq_base < 0) {
465 dev_warn(&pdev->dev,
466 "ml_ioh_gpio: Failed to get IRQ base num\n");
467 chip->irq_base = -1;
468 ret = irq_base;
469 goto err_irq_alloc_descs;
470 }
471 chip->irq_base = irq_base;
472 ioh_gpio_alloc_generic_chip(chip, irq_base, num_ports[j]);
473 }
474
475 chip = chip_save;
476 ret = request_irq(pdev->irq, ioh_gpio_handler,
477 IRQF_SHARED, KBUILD_MODNAME, chip);
478 if (ret != 0) {
479 dev_err(&pdev->dev,
480 "%s request_irq failed\n", __func__);
481 goto err_request_irq;
482 }
483
484 pci_set_drvdata(pdev, chip);
485
486 return 0;
487
488err_request_irq:
489 chip = chip_save;
490err_irq_alloc_descs:
491 while (--j >= 0) {
492 chip--;
493 irq_free_descs(chip->irq_base, num_ports[j]);
494 }
495
496 chip = chip_save;
497err_gpiochip_add:
498 while (--i >= 0) {
499 chip--;
500 if (gpiochip_remove(&chip->gpio))
501 dev_err(&pdev->dev, "Failed gpiochip_remove(%d)\n", i);
502 }
503 kfree(chip_save);
504
505err_kzalloc:
506 pci_iounmap(pdev, base);
507
508err_iomap:
509 pci_release_regions(pdev);
510
511err_request_regions:
512 pci_disable_device(pdev);
513
514err_pci_enable:
515
516 dev_err(&pdev->dev, "%s Failed returns %d\n", __func__, ret);
517 return ret;
518}
519
520static void ioh_gpio_remove(struct pci_dev *pdev)
521{
522 int err;
523 int i;
524 struct ioh_gpio *chip = pci_get_drvdata(pdev);
525 void *chip_save;
526
527 chip_save = chip;
528
529 free_irq(pdev->irq, chip);
530
531 for (i = 0; i < 8; i++, chip++) {
532 irq_free_descs(chip->irq_base, num_ports[i]);
533 err = gpiochip_remove(&chip->gpio);
534 if (err)
535 dev_err(&pdev->dev, "Failed gpiochip_remove\n");
536 }
537
538 chip = chip_save;
539 pci_iounmap(pdev, chip->base);
540 pci_release_regions(pdev);
541 pci_disable_device(pdev);
542 kfree(chip);
543}
544
545#ifdef CONFIG_PM
546static int ioh_gpio_suspend(struct pci_dev *pdev, pm_message_t state)
547{
548 s32 ret;
549 struct ioh_gpio *chip = pci_get_drvdata(pdev);
550 unsigned long flags;
551
552 spin_lock_irqsave(&chip->spinlock, flags);
553 ioh_gpio_save_reg_conf(chip);
554 spin_unlock_irqrestore(&chip->spinlock, flags);
555
556 ret = pci_save_state(pdev);
557 if (ret) {
558 dev_err(&pdev->dev, "pci_save_state Failed-%d\n", ret);
559 return ret;
560 }
561 pci_disable_device(pdev);
562 pci_set_power_state(pdev, PCI_D0);
563 ret = pci_enable_wake(pdev, PCI_D0, 1);
564 if (ret)
565 dev_err(&pdev->dev, "pci_enable_wake Failed -%d\n", ret);
566
567 return 0;
568}
569
570static int ioh_gpio_resume(struct pci_dev *pdev)
571{
572 s32 ret;
573 struct ioh_gpio *chip = pci_get_drvdata(pdev);
574 unsigned long flags;
575
576 ret = pci_enable_wake(pdev, PCI_D0, 0);
577
578 pci_set_power_state(pdev, PCI_D0);
579 ret = pci_enable_device(pdev);
580 if (ret) {
581 dev_err(&pdev->dev, "pci_enable_device Failed-%d ", ret);
582 return ret;
583 }
584 pci_restore_state(pdev);
585
586 spin_lock_irqsave(&chip->spinlock, flags);
587 iowrite32(0x01, &chip->reg->srst);
588 iowrite32(0x00, &chip->reg->srst);
589 ioh_gpio_restore_reg_conf(chip);
590 spin_unlock_irqrestore(&chip->spinlock, flags);
591
592 return 0;
593}
594#else
595#define ioh_gpio_suspend NULL
596#define ioh_gpio_resume NULL
597#endif
598
599static const struct pci_device_id ioh_gpio_pcidev_id[] = {
600 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) },
601 { 0, }
602};
603MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id);
604
605static struct pci_driver ioh_gpio_driver = {
606 .name = "ml_ioh_gpio",
607 .id_table = ioh_gpio_pcidev_id,
608 .probe = ioh_gpio_probe,
609 .remove = ioh_gpio_remove,
610 .suspend = ioh_gpio_suspend,
611 .resume = ioh_gpio_resume
612};
613
614module_pci_driver(ioh_gpio_driver);
615
616MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver");
617MODULE_LICENSE("GPL");