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1/*
2 * GPIO controller driver for Intel Lynxpoint PCH chipset>
3 * Copyright (c) 2012, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/init.h>
25#include <linux/types.h>
26#include <linux/bitops.h>
27#include <linux/interrupt.h>
28#include <linux/irq.h>
29#include <linux/gpio.h>
30#include <linux/irqdomain.h>
31#include <linux/slab.h>
32#include <linux/acpi.h>
33#include <linux/platform_device.h>
34#include <linux/pm_runtime.h>
35#include <linux/io.h>
36
37/* LynxPoint chipset has support for 94 gpio pins */
38
39#define LP_NUM_GPIO 94
40
41/* Bitmapped register offsets */
42#define LP_ACPI_OWNED 0x00 /* Bitmap, set by bios, 0: pin reserved for ACPI */
43#define LP_GC 0x7C /* set APIC IRQ to IRQ14 or IRQ15 for all pins */
44#define LP_INT_STAT 0x80
45#define LP_INT_ENABLE 0x90
46
47/* Each pin has two 32 bit config registers, starting at 0x100 */
48#define LP_CONFIG1 0x100
49#define LP_CONFIG2 0x104
50
51/* LP_CONFIG1 reg bits */
52#define OUT_LVL_BIT BIT(31)
53#define IN_LVL_BIT BIT(30)
54#define TRIG_SEL_BIT BIT(4) /* 0: Edge, 1: Level */
55#define INT_INV_BIT BIT(3) /* Invert interrupt triggering */
56#define DIR_BIT BIT(2) /* 0: Output, 1: Input */
57#define USE_SEL_BIT BIT(0) /* 0: Native, 1: GPIO */
58
59/* LP_CONFIG2 reg bits */
60#define GPINDIS_BIT BIT(2) /* disable input sensing */
61#define GPIWP_BIT (BIT(0) | BIT(1)) /* weak pull options */
62
63struct lp_gpio {
64 struct gpio_chip chip;
65 struct irq_domain *domain;
66 struct platform_device *pdev;
67 spinlock_t lock;
68 unsigned long reg_base;
69};
70
71/*
72 * Lynxpoint gpios are controlled through both bitmapped registers and
73 * per gpio specific registers. The bitmapped registers are in chunks of
74 * 3 x 32bit registers to cover all 94 gpios
75 *
76 * per gpio specific registers consist of two 32bit registers per gpio
77 * (LP_CONFIG1 and LP_CONFIG2), with 94 gpios there's a total of
78 * 188 config registes.
79 *
80 * A simplified view of the register layout look like this:
81 *
82 * LP_ACPI_OWNED[31:0] gpio ownerships for gpios 0-31 (bitmapped registers)
83 * LP_ACPI_OWNED[63:32] gpio ownerships for gpios 32-63
84 * LP_ACPI_OWNED[94:64] gpio ownerships for gpios 63-94
85 * ...
86 * LP_INT_ENABLE[31:0] ...
87 * LP_INT_ENABLE[63:31] ...
88 * LP_INT_ENABLE[94:64] ...
89 * LP0_CONFIG1 (gpio 0) config1 reg for gpio 0 (per gpio registers)
90 * LP0_CONFIG2 (gpio 0) config2 reg for gpio 0
91 * LP1_CONFIG1 (gpio 1) config1 reg for gpio 1
92 * LP1_CONFIG2 (gpio 1) config2 reg for gpio 1
93 * LP2_CONFIG1 (gpio 2) ...
94 * LP2_CONFIG2 (gpio 2) ...
95 * ...
96 * LP94_CONFIG1 (gpio 94) ...
97 * LP94_CONFIG2 (gpio 94) ...
98 */
99
100static unsigned long lp_gpio_reg(struct gpio_chip *chip, unsigned offset,
101 int reg)
102{
103 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
104 int reg_offset;
105
106 if (reg == LP_CONFIG1 || reg == LP_CONFIG2)
107 /* per gpio specific config registers */
108 reg_offset = offset * 8;
109 else
110 /* bitmapped registers */
111 reg_offset = (offset / 32) * 4;
112
113 return lg->reg_base + reg + reg_offset;
114}
115
116static int lp_gpio_request(struct gpio_chip *chip, unsigned offset)
117{
118 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
119 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
120 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
121 unsigned long acpi_use = lp_gpio_reg(chip, offset, LP_ACPI_OWNED);
122
123 pm_runtime_get(&lg->pdev->dev); /* should we put if failed */
124
125 /* Fail if BIOS reserved pin for ACPI use */
126 if (!(inl(acpi_use) & BIT(offset % 32))) {
127 dev_err(&lg->pdev->dev, "gpio %d reserved for ACPI\n", offset);
128 return -EBUSY;
129 }
130 /* Fail if pin is in alternate function mode (not GPIO mode) */
131 if (!(inl(reg) & USE_SEL_BIT))
132 return -ENODEV;
133
134 /* enable input sensing */
135 outl(inl(conf2) & ~GPINDIS_BIT, conf2);
136
137
138 return 0;
139}
140
141static void lp_gpio_free(struct gpio_chip *chip, unsigned offset)
142{
143 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
144 unsigned long conf2 = lp_gpio_reg(chip, offset, LP_CONFIG2);
145
146 /* disable input sensing */
147 outl(inl(conf2) | GPINDIS_BIT, conf2);
148
149 pm_runtime_put(&lg->pdev->dev);
150}
151
152static int lp_irq_type(struct irq_data *d, unsigned type)
153{
154 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
155 u32 hwirq = irqd_to_hwirq(d);
156 unsigned long flags;
157 u32 value;
158 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_CONFIG1);
159
160 if (hwirq >= lg->chip.ngpio)
161 return -EINVAL;
162
163 spin_lock_irqsave(&lg->lock, flags);
164 value = inl(reg);
165
166 /* set both TRIG_SEL and INV bits to 0 for rising edge */
167 if (type & IRQ_TYPE_EDGE_RISING)
168 value &= ~(TRIG_SEL_BIT | INT_INV_BIT);
169
170 /* TRIG_SEL bit 0, INV bit 1 for falling edge */
171 if (type & IRQ_TYPE_EDGE_FALLING)
172 value = (value | INT_INV_BIT) & ~TRIG_SEL_BIT;
173
174 /* TRIG_SEL bit 1, INV bit 0 for level low */
175 if (type & IRQ_TYPE_LEVEL_LOW)
176 value = (value | TRIG_SEL_BIT) & ~INT_INV_BIT;
177
178 /* TRIG_SEL bit 1, INV bit 1 for level high */
179 if (type & IRQ_TYPE_LEVEL_HIGH)
180 value |= TRIG_SEL_BIT | INT_INV_BIT;
181
182 outl(value, reg);
183 spin_unlock_irqrestore(&lg->lock, flags);
184
185 return 0;
186}
187
188static int lp_gpio_get(struct gpio_chip *chip, unsigned offset)
189{
190 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
191 return !!(inl(reg) & IN_LVL_BIT);
192}
193
194static void lp_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
195{
196 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
197 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
198 unsigned long flags;
199
200 spin_lock_irqsave(&lg->lock, flags);
201
202 if (value)
203 outl(inl(reg) | OUT_LVL_BIT, reg);
204 else
205 outl(inl(reg) & ~OUT_LVL_BIT, reg);
206
207 spin_unlock_irqrestore(&lg->lock, flags);
208}
209
210static int lp_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
211{
212 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
213 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
214 unsigned long flags;
215
216 spin_lock_irqsave(&lg->lock, flags);
217 outl(inl(reg) | DIR_BIT, reg);
218 spin_unlock_irqrestore(&lg->lock, flags);
219
220 return 0;
221}
222
223static int lp_gpio_direction_output(struct gpio_chip *chip,
224 unsigned offset, int value)
225{
226 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
227 unsigned long reg = lp_gpio_reg(chip, offset, LP_CONFIG1);
228 unsigned long flags;
229
230 lp_gpio_set(chip, offset, value);
231
232 spin_lock_irqsave(&lg->lock, flags);
233 outl(inl(reg) & ~DIR_BIT, reg);
234 spin_unlock_irqrestore(&lg->lock, flags);
235
236 return 0;
237}
238
239static int lp_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
240{
241 struct lp_gpio *lg = container_of(chip, struct lp_gpio, chip);
242 return irq_create_mapping(lg->domain, offset);
243}
244
245static void lp_gpio_irq_handler(unsigned hwirq, struct irq_desc *desc)
246{
247 struct irq_data *data = irq_desc_get_irq_data(desc);
248 struct lp_gpio *lg = irq_data_get_irq_handler_data(data);
249 struct irq_chip *chip = irq_data_get_irq_chip(data);
250 u32 base, pin, mask;
251 unsigned long reg, ena, pending;
252
253 /* check from GPIO controller which pin triggered the interrupt */
254 for (base = 0; base < lg->chip.ngpio; base += 32) {
255 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
256 ena = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
257
258 while ((pending = (inl(reg) & inl(ena)))) {
259 unsigned irq;
260
261 pin = __ffs(pending);
262 mask = BIT(pin);
263 /* Clear before handling so we don't lose an edge */
264 outl(mask, reg);
265 irq = irq_find_mapping(lg->domain, base + pin);
266 generic_handle_irq(irq);
267 }
268 }
269 chip->irq_eoi(data);
270}
271
272static void lp_irq_unmask(struct irq_data *d)
273{
274}
275
276static void lp_irq_mask(struct irq_data *d)
277{
278}
279
280static void lp_irq_enable(struct irq_data *d)
281{
282 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
283 u32 hwirq = irqd_to_hwirq(d);
284 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
285 unsigned long flags;
286
287 spin_lock_irqsave(&lg->lock, flags);
288 outl(inl(reg) | BIT(hwirq % 32), reg);
289 spin_unlock_irqrestore(&lg->lock, flags);
290}
291
292static void lp_irq_disable(struct irq_data *d)
293{
294 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
295 u32 hwirq = irqd_to_hwirq(d);
296 unsigned long reg = lp_gpio_reg(&lg->chip, hwirq, LP_INT_ENABLE);
297 unsigned long flags;
298
299 spin_lock_irqsave(&lg->lock, flags);
300 outl(inl(reg) & ~BIT(hwirq % 32), reg);
301 spin_unlock_irqrestore(&lg->lock, flags);
302}
303
304static int lp_irq_reqres(struct irq_data *d)
305{
306 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
307
308 if (gpio_lock_as_irq(&lg->chip, irqd_to_hwirq(d))) {
309 dev_err(lg->chip.dev,
310 "unable to lock HW IRQ %lu for IRQ\n",
311 irqd_to_hwirq(d));
312 return -EINVAL;
313 }
314 return 0;
315}
316
317static void lp_irq_relres(struct irq_data *d)
318{
319 struct lp_gpio *lg = irq_data_get_irq_chip_data(d);
320
321 gpio_unlock_as_irq(&lg->chip, irqd_to_hwirq(d));
322}
323
324static struct irq_chip lp_irqchip = {
325 .name = "LP-GPIO",
326 .irq_mask = lp_irq_mask,
327 .irq_unmask = lp_irq_unmask,
328 .irq_enable = lp_irq_enable,
329 .irq_disable = lp_irq_disable,
330 .irq_set_type = lp_irq_type,
331 .irq_request_resources = lp_irq_reqres,
332 .irq_release_resources = lp_irq_relres,
333 .flags = IRQCHIP_SKIP_SET_WAKE,
334};
335
336static void lp_gpio_irq_init_hw(struct lp_gpio *lg)
337{
338 unsigned long reg;
339 unsigned base;
340
341 for (base = 0; base < lg->chip.ngpio; base += 32) {
342 /* disable gpio pin interrupts */
343 reg = lp_gpio_reg(&lg->chip, base, LP_INT_ENABLE);
344 outl(0, reg);
345 /* Clear interrupt status register */
346 reg = lp_gpio_reg(&lg->chip, base, LP_INT_STAT);
347 outl(0xffffffff, reg);
348 }
349}
350
351static int lp_gpio_irq_map(struct irq_domain *d, unsigned int irq,
352 irq_hw_number_t hwirq)
353{
354 struct lp_gpio *lg = d->host_data;
355
356 irq_set_chip_and_handler(irq, &lp_irqchip, handle_simple_irq);
357 irq_set_chip_data(irq, lg);
358 irq_set_irq_type(irq, IRQ_TYPE_NONE);
359
360 return 0;
361}
362
363static const struct irq_domain_ops lp_gpio_irq_ops = {
364 .map = lp_gpio_irq_map,
365};
366
367static int lp_gpio_probe(struct platform_device *pdev)
368{
369 struct lp_gpio *lg;
370 struct gpio_chip *gc;
371 struct resource *io_rc, *irq_rc;
372 struct device *dev = &pdev->dev;
373 unsigned long reg_len;
374 unsigned hwirq;
375 int ret = -ENODEV;
376
377 lg = devm_kzalloc(dev, sizeof(struct lp_gpio), GFP_KERNEL);
378 if (!lg) {
379 dev_err(dev, "can't allocate lp_gpio chip data\n");
380 return -ENOMEM;
381 }
382
383 lg->pdev = pdev;
384 platform_set_drvdata(pdev, lg);
385
386 io_rc = platform_get_resource(pdev, IORESOURCE_IO, 0);
387 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
388
389 if (!io_rc) {
390 dev_err(dev, "missing IO resources\n");
391 return -EINVAL;
392 }
393
394 lg->reg_base = io_rc->start;
395 reg_len = resource_size(io_rc);
396
397 if (!devm_request_region(dev, lg->reg_base, reg_len, "lp-gpio")) {
398 dev_err(dev, "failed requesting IO region 0x%x\n",
399 (unsigned int)lg->reg_base);
400 return -EBUSY;
401 }
402
403 spin_lock_init(&lg->lock);
404
405 gc = &lg->chip;
406 gc->label = dev_name(dev);
407 gc->owner = THIS_MODULE;
408 gc->request = lp_gpio_request;
409 gc->free = lp_gpio_free;
410 gc->direction_input = lp_gpio_direction_input;
411 gc->direction_output = lp_gpio_direction_output;
412 gc->get = lp_gpio_get;
413 gc->set = lp_gpio_set;
414 gc->base = -1;
415 gc->ngpio = LP_NUM_GPIO;
416 gc->can_sleep = false;
417 gc->dev = dev;
418
419 /* set up interrupts */
420 if (irq_rc && irq_rc->start) {
421 hwirq = irq_rc->start;
422 gc->to_irq = lp_gpio_to_irq;
423
424 lg->domain = irq_domain_add_linear(NULL, LP_NUM_GPIO,
425 &lp_gpio_irq_ops, lg);
426 if (!lg->domain)
427 return -ENXIO;
428
429 lp_gpio_irq_init_hw(lg);
430
431 irq_set_handler_data(hwirq, lg);
432 irq_set_chained_handler(hwirq, lp_gpio_irq_handler);
433 }
434
435 ret = gpiochip_add(gc);
436 if (ret) {
437 dev_err(dev, "failed adding lp-gpio chip\n");
438 return ret;
439 }
440 pm_runtime_enable(dev);
441
442 return 0;
443}
444
445static int lp_gpio_runtime_suspend(struct device *dev)
446{
447 return 0;
448}
449
450static int lp_gpio_runtime_resume(struct device *dev)
451{
452 return 0;
453}
454
455static const struct dev_pm_ops lp_gpio_pm_ops = {
456 .runtime_suspend = lp_gpio_runtime_suspend,
457 .runtime_resume = lp_gpio_runtime_resume,
458};
459
460static const struct acpi_device_id lynxpoint_gpio_acpi_match[] = {
461 { "INT33C7", 0 },
462 { "INT3437", 0 },
463 { }
464};
465MODULE_DEVICE_TABLE(acpi, lynxpoint_gpio_acpi_match);
466
467static int lp_gpio_remove(struct platform_device *pdev)
468{
469 struct lp_gpio *lg = platform_get_drvdata(pdev);
470 int err;
471 pm_runtime_disable(&pdev->dev);
472 err = gpiochip_remove(&lg->chip);
473 if (err)
474 dev_warn(&pdev->dev, "failed to remove gpio_chip.\n");
475 return 0;
476}
477
478static struct platform_driver lp_gpio_driver = {
479 .probe = lp_gpio_probe,
480 .remove = lp_gpio_remove,
481 .driver = {
482 .name = "lp_gpio",
483 .owner = THIS_MODULE,
484 .pm = &lp_gpio_pm_ops,
485 .acpi_match_table = ACPI_PTR(lynxpoint_gpio_acpi_match),
486 },
487};
488
489static int __init lp_gpio_init(void)
490{
491 return platform_driver_register(&lp_gpio_driver);
492}
493
494static void __exit lp_gpio_exit(void)
495{
496 platform_driver_unregister(&lp_gpio_driver);
497}
498
499subsys_initcall(lp_gpio_init);
500module_exit(lp_gpio_exit);
501
502MODULE_AUTHOR("Mathias Nyman (Intel)");
503MODULE_DESCRIPTION("GPIO interface for Intel Lynxpoint");
504MODULE_LICENSE("GPL");
505MODULE_ALIAS("platform:lp_gpio");