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1/*
2 * This file contains driver for the Cadence Triple Timer Counter Rev 06
3 *
4 * Copyright (C) 2011-2013 Xilinx
5 *
6 * based on arch/mips/kernel/time.c timer driver
7 *
8 * This software is licensed under the terms of the GNU General Public
9 * License version 2, as published by the Free Software Foundation, and
10 * may be copied, distributed, and modified under those terms.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk.h>
19#include <linux/clk-provider.h>
20#include <linux/interrupt.h>
21#include <linux/clockchips.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/slab.h>
25#include <linux/sched_clock.h>
26
27/*
28 * This driver configures the 2 16-bit count-up timers as follows:
29 *
30 * T1: Timer 1, clocksource for generic timekeeping
31 * T2: Timer 2, clockevent source for hrtimers
32 * T3: Timer 3, <unused>
33 *
34 * The input frequency to the timer module for emulation is 2.5MHz which is
35 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
36 * the timers are clocked at 78.125KHz (12.8 us resolution).
37
38 * The input frequency to the timer module in silicon is configurable and
39 * obtained from device tree. The pre-scaler of 32 is used.
40 */
41
42/*
43 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
44 * and use same offsets for Timer 2
45 */
46#define TTC_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
47#define TTC_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
48#define TTC_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
49#define TTC_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
50#define TTC_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
51#define TTC_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
52
53#define TTC_CNT_CNTRL_DISABLE_MASK 0x1
54
55#define TTC_CLK_CNTRL_CSRC_MASK (1 << 5) /* clock source */
56#define TTC_CLK_CNTRL_PSV_MASK 0x1e
57#define TTC_CLK_CNTRL_PSV_SHIFT 1
58
59/*
60 * Setup the timers to use pre-scaling, using a fixed value for now that will
61 * work across most input frequency, but it may need to be more dynamic
62 */
63#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
64#define PRESCALE 2048 /* The exponent must match this */
65#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
66#define CLK_CNTRL_PRESCALE_EN 1
67#define CNT_CNTRL_RESET (1 << 4)
68
69#define MAX_F_ERR 50
70
71/**
72 * struct ttc_timer - This definition defines local timer structure
73 *
74 * @base_addr: Base address of timer
75 * @freq: Timer input clock frequency
76 * @clk: Associated clock source
77 * @clk_rate_change_nb Notifier block for clock rate changes
78 */
79struct ttc_timer {
80 void __iomem *base_addr;
81 unsigned long freq;
82 struct clk *clk;
83 struct notifier_block clk_rate_change_nb;
84};
85
86#define to_ttc_timer(x) \
87 container_of(x, struct ttc_timer, clk_rate_change_nb)
88
89struct ttc_timer_clocksource {
90 u32 scale_clk_ctrl_reg_old;
91 u32 scale_clk_ctrl_reg_new;
92 struct ttc_timer ttc;
93 struct clocksource cs;
94};
95
96#define to_ttc_timer_clksrc(x) \
97 container_of(x, struct ttc_timer_clocksource, cs)
98
99struct ttc_timer_clockevent {
100 struct ttc_timer ttc;
101 struct clock_event_device ce;
102};
103
104#define to_ttc_timer_clkevent(x) \
105 container_of(x, struct ttc_timer_clockevent, ce)
106
107static void __iomem *ttc_sched_clock_val_reg;
108
109/**
110 * ttc_set_interval - Set the timer interval value
111 *
112 * @timer: Pointer to the timer instance
113 * @cycles: Timer interval ticks
114 **/
115static void ttc_set_interval(struct ttc_timer *timer,
116 unsigned long cycles)
117{
118 u32 ctrl_reg;
119
120 /* Disable the counter, set the counter value and re-enable counter */
121 ctrl_reg = __raw_readl(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
122 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
123 __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
124
125 __raw_writel(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
126
127 /*
128 * Reset the counter (0x10) so that it starts from 0, one-shot
129 * mode makes this needed for timing to be right.
130 */
131 ctrl_reg |= CNT_CNTRL_RESET;
132 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
133 __raw_writel(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
134}
135
136/**
137 * ttc_clock_event_interrupt - Clock event timer interrupt handler
138 *
139 * @irq: IRQ number of the Timer
140 * @dev_id: void pointer to the ttc_timer instance
141 *
142 * returns: Always IRQ_HANDLED - success
143 **/
144static irqreturn_t ttc_clock_event_interrupt(int irq, void *dev_id)
145{
146 struct ttc_timer_clockevent *ttce = dev_id;
147 struct ttc_timer *timer = &ttce->ttc;
148
149 /* Acknowledge the interrupt and call event handler */
150 __raw_readl(timer->base_addr + TTC_ISR_OFFSET);
151
152 ttce->ce.event_handler(&ttce->ce);
153
154 return IRQ_HANDLED;
155}
156
157/**
158 * __ttc_clocksource_read - Reads the timer counter register
159 *
160 * returns: Current timer counter register value
161 **/
162static cycle_t __ttc_clocksource_read(struct clocksource *cs)
163{
164 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
165
166 return (cycle_t)__raw_readl(timer->base_addr +
167 TTC_COUNT_VAL_OFFSET);
168}
169
170static u64 notrace ttc_sched_clock_read(void)
171{
172 return __raw_readl(ttc_sched_clock_val_reg);
173}
174
175/**
176 * ttc_set_next_event - Sets the time interval for next event
177 *
178 * @cycles: Timer interval ticks
179 * @evt: Address of clock event instance
180 *
181 * returns: Always 0 - success
182 **/
183static int ttc_set_next_event(unsigned long cycles,
184 struct clock_event_device *evt)
185{
186 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
187 struct ttc_timer *timer = &ttce->ttc;
188
189 ttc_set_interval(timer, cycles);
190 return 0;
191}
192
193/**
194 * ttc_set_mode - Sets the mode of timer
195 *
196 * @mode: Mode to be set
197 * @evt: Address of clock event instance
198 **/
199static void ttc_set_mode(enum clock_event_mode mode,
200 struct clock_event_device *evt)
201{
202 struct ttc_timer_clockevent *ttce = to_ttc_timer_clkevent(evt);
203 struct ttc_timer *timer = &ttce->ttc;
204 u32 ctrl_reg;
205
206 switch (mode) {
207 case CLOCK_EVT_MODE_PERIODIC:
208 ttc_set_interval(timer, DIV_ROUND_CLOSEST(ttce->ttc.freq,
209 PRESCALE * HZ));
210 break;
211 case CLOCK_EVT_MODE_ONESHOT:
212 case CLOCK_EVT_MODE_UNUSED:
213 case CLOCK_EVT_MODE_SHUTDOWN:
214 ctrl_reg = __raw_readl(timer->base_addr +
215 TTC_CNT_CNTRL_OFFSET);
216 ctrl_reg |= TTC_CNT_CNTRL_DISABLE_MASK;
217 __raw_writel(ctrl_reg,
218 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
219 break;
220 case CLOCK_EVT_MODE_RESUME:
221 ctrl_reg = __raw_readl(timer->base_addr +
222 TTC_CNT_CNTRL_OFFSET);
223 ctrl_reg &= ~TTC_CNT_CNTRL_DISABLE_MASK;
224 __raw_writel(ctrl_reg,
225 timer->base_addr + TTC_CNT_CNTRL_OFFSET);
226 break;
227 }
228}
229
230static int ttc_rate_change_clocksource_cb(struct notifier_block *nb,
231 unsigned long event, void *data)
232{
233 struct clk_notifier_data *ndata = data;
234 struct ttc_timer *ttc = to_ttc_timer(nb);
235 struct ttc_timer_clocksource *ttccs = container_of(ttc,
236 struct ttc_timer_clocksource, ttc);
237
238 switch (event) {
239 case PRE_RATE_CHANGE:
240 {
241 u32 psv;
242 unsigned long factor, rate_low, rate_high;
243
244 if (ndata->new_rate > ndata->old_rate) {
245 factor = DIV_ROUND_CLOSEST(ndata->new_rate,
246 ndata->old_rate);
247 rate_low = ndata->old_rate;
248 rate_high = ndata->new_rate;
249 } else {
250 factor = DIV_ROUND_CLOSEST(ndata->old_rate,
251 ndata->new_rate);
252 rate_low = ndata->new_rate;
253 rate_high = ndata->old_rate;
254 }
255
256 if (!is_power_of_2(factor))
257 return NOTIFY_BAD;
258
259 if (abs(rate_high - (factor * rate_low)) > MAX_F_ERR)
260 return NOTIFY_BAD;
261
262 factor = __ilog2_u32(factor);
263
264 /*
265 * store timer clock ctrl register so we can restore it in case
266 * of an abort.
267 */
268 ttccs->scale_clk_ctrl_reg_old =
269 __raw_readl(ttccs->ttc.base_addr +
270 TTC_CLK_CNTRL_OFFSET);
271
272 psv = (ttccs->scale_clk_ctrl_reg_old &
273 TTC_CLK_CNTRL_PSV_MASK) >>
274 TTC_CLK_CNTRL_PSV_SHIFT;
275 if (ndata->new_rate < ndata->old_rate)
276 psv -= factor;
277 else
278 psv += factor;
279
280 /* prescaler within legal range? */
281 if (psv & ~(TTC_CLK_CNTRL_PSV_MASK >> TTC_CLK_CNTRL_PSV_SHIFT))
282 return NOTIFY_BAD;
283
284 ttccs->scale_clk_ctrl_reg_new = ttccs->scale_clk_ctrl_reg_old &
285 ~TTC_CLK_CNTRL_PSV_MASK;
286 ttccs->scale_clk_ctrl_reg_new |= psv << TTC_CLK_CNTRL_PSV_SHIFT;
287
288
289 /* scale down: adjust divider in post-change notification */
290 if (ndata->new_rate < ndata->old_rate)
291 return NOTIFY_DONE;
292
293 /* scale up: adjust divider now - before frequency change */
294 __raw_writel(ttccs->scale_clk_ctrl_reg_new,
295 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
296 break;
297 }
298 case POST_RATE_CHANGE:
299 /* scale up: pre-change notification did the adjustment */
300 if (ndata->new_rate > ndata->old_rate)
301 return NOTIFY_OK;
302
303 /* scale down: adjust divider now - after frequency change */
304 __raw_writel(ttccs->scale_clk_ctrl_reg_new,
305 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
306 break;
307
308 case ABORT_RATE_CHANGE:
309 /* we have to undo the adjustment in case we scale up */
310 if (ndata->new_rate < ndata->old_rate)
311 return NOTIFY_OK;
312
313 /* restore original register value */
314 __raw_writel(ttccs->scale_clk_ctrl_reg_old,
315 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
316 /* fall through */
317 default:
318 return NOTIFY_DONE;
319 }
320
321 return NOTIFY_DONE;
322}
323
324static void __init ttc_setup_clocksource(struct clk *clk, void __iomem *base)
325{
326 struct ttc_timer_clocksource *ttccs;
327 int err;
328
329 ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
330 if (WARN_ON(!ttccs))
331 return;
332
333 ttccs->ttc.clk = clk;
334
335 err = clk_prepare_enable(ttccs->ttc.clk);
336 if (WARN_ON(err)) {
337 kfree(ttccs);
338 return;
339 }
340
341 ttccs->ttc.freq = clk_get_rate(ttccs->ttc.clk);
342
343 ttccs->ttc.clk_rate_change_nb.notifier_call =
344 ttc_rate_change_clocksource_cb;
345 ttccs->ttc.clk_rate_change_nb.next = NULL;
346 if (clk_notifier_register(ttccs->ttc.clk,
347 &ttccs->ttc.clk_rate_change_nb))
348 pr_warn("Unable to register clock notifier.\n");
349
350 ttccs->ttc.base_addr = base;
351 ttccs->cs.name = "ttc_clocksource";
352 ttccs->cs.rating = 200;
353 ttccs->cs.read = __ttc_clocksource_read;
354 ttccs->cs.mask = CLOCKSOURCE_MASK(16);
355 ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
356
357 /*
358 * Setup the clock source counter to be an incrementing counter
359 * with no interrupt and it rolls over at 0xFFFF. Pre-scale
360 * it by 32 also. Let it start running now.
361 */
362 __raw_writel(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
363 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
364 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
365 __raw_writel(CNT_CNTRL_RESET,
366 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
367
368 err = clocksource_register_hz(&ttccs->cs, ttccs->ttc.freq / PRESCALE);
369 if (WARN_ON(err)) {
370 kfree(ttccs);
371 return;
372 }
373
374 ttc_sched_clock_val_reg = base + TTC_COUNT_VAL_OFFSET;
375 sched_clock_register(ttc_sched_clock_read, 16, ttccs->ttc.freq / PRESCALE);
376}
377
378static int ttc_rate_change_clockevent_cb(struct notifier_block *nb,
379 unsigned long event, void *data)
380{
381 struct clk_notifier_data *ndata = data;
382 struct ttc_timer *ttc = to_ttc_timer(nb);
383 struct ttc_timer_clockevent *ttcce = container_of(ttc,
384 struct ttc_timer_clockevent, ttc);
385
386 switch (event) {
387 case POST_RATE_CHANGE:
388 /* update cached frequency */
389 ttc->freq = ndata->new_rate;
390
391 clockevents_update_freq(&ttcce->ce, ndata->new_rate / PRESCALE);
392
393 /* fall through */
394 case PRE_RATE_CHANGE:
395 case ABORT_RATE_CHANGE:
396 default:
397 return NOTIFY_DONE;
398 }
399}
400
401static void __init ttc_setup_clockevent(struct clk *clk,
402 void __iomem *base, u32 irq)
403{
404 struct ttc_timer_clockevent *ttcce;
405 int err;
406
407 ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
408 if (WARN_ON(!ttcce))
409 return;
410
411 ttcce->ttc.clk = clk;
412
413 err = clk_prepare_enable(ttcce->ttc.clk);
414 if (WARN_ON(err)) {
415 kfree(ttcce);
416 return;
417 }
418
419 ttcce->ttc.clk_rate_change_nb.notifier_call =
420 ttc_rate_change_clockevent_cb;
421 ttcce->ttc.clk_rate_change_nb.next = NULL;
422 if (clk_notifier_register(ttcce->ttc.clk,
423 &ttcce->ttc.clk_rate_change_nb))
424 pr_warn("Unable to register clock notifier.\n");
425 ttcce->ttc.freq = clk_get_rate(ttcce->ttc.clk);
426
427 ttcce->ttc.base_addr = base;
428 ttcce->ce.name = "ttc_clockevent";
429 ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
430 ttcce->ce.set_next_event = ttc_set_next_event;
431 ttcce->ce.set_mode = ttc_set_mode;
432 ttcce->ce.rating = 200;
433 ttcce->ce.irq = irq;
434 ttcce->ce.cpumask = cpu_possible_mask;
435
436 /*
437 * Setup the clock event timer to be an interval timer which
438 * is prescaled by 32 using the interval interrupt. Leave it
439 * disabled for now.
440 */
441 __raw_writel(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
442 __raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
443 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
444 __raw_writel(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);
445
446 err = request_irq(irq, ttc_clock_event_interrupt,
447 IRQF_TIMER, ttcce->ce.name, ttcce);
448 if (WARN_ON(err)) {
449 kfree(ttcce);
450 return;
451 }
452
453 clockevents_config_and_register(&ttcce->ce,
454 ttcce->ttc.freq / PRESCALE, 1, 0xfffe);
455}
456
457/**
458 * ttc_timer_init - Initialize the timer
459 *
460 * Initializes the timer hardware and register the clock source and clock event
461 * timers with Linux kernal timer framework
462 */
463static void __init ttc_timer_init(struct device_node *timer)
464{
465 unsigned int irq;
466 void __iomem *timer_baseaddr;
467 struct clk *clk_cs, *clk_ce;
468 static int initialized;
469 int clksel;
470
471 if (initialized)
472 return;
473
474 initialized = 1;
475
476 /*
477 * Get the 1st Triple Timer Counter (TTC) block from the device tree
478 * and use it. Note that the event timer uses the interrupt and it's the
479 * 2nd TTC hence the irq_of_parse_and_map(,1)
480 */
481 timer_baseaddr = of_iomap(timer, 0);
482 if (!timer_baseaddr) {
483 pr_err("ERROR: invalid timer base address\n");
484 BUG();
485 }
486
487 irq = irq_of_parse_and_map(timer, 1);
488 if (irq <= 0) {
489 pr_err("ERROR: invalid interrupt number\n");
490 BUG();
491 }
492
493 clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
494 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
495 clk_cs = of_clk_get(timer, clksel);
496 if (IS_ERR(clk_cs)) {
497 pr_err("ERROR: timer input clock not found\n");
498 BUG();
499 }
500
501 clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
502 clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
503 clk_ce = of_clk_get(timer, clksel);
504 if (IS_ERR(clk_ce)) {
505 pr_err("ERROR: timer input clock not found\n");
506 BUG();
507 }
508
509 ttc_setup_clocksource(clk_cs, timer_baseaddr);
510 ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
511
512 pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
513}
514
515CLOCKSOURCE_OF_DECLARE(ttc, "cdns,ttc", ttc_timer_init);