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1/*
2 * omap-rng.c - RNG driver for TI OMAP CPU family
3 *
4 * Author: Deepak Saxena <dsaxena@plexity.net>
5 *
6 * Copyright 2005 (c) MontaVista Software, Inc.
7 *
8 * Mostly based on original driver:
9 *
10 * Copyright (C) 2005 Nokia Corporation
11 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/random.h>
21#include <linux/clk.h>
22#include <linux/err.h>
23#include <linux/platform_device.h>
24#include <linux/hw_random.h>
25#include <linux/delay.h>
26
27#include <asm/io.h>
28
29#define RNG_OUT_REG 0x00 /* Output register */
30#define RNG_STAT_REG 0x04 /* Status register
31 [0] = STAT_BUSY */
32#define RNG_ALARM_REG 0x24 /* Alarm register
33 [7:0] = ALARM_COUNTER */
34#define RNG_CONFIG_REG 0x28 /* Configuration register
35 [11:6] = RESET_COUNT
36 [5:3] = RING2_DELAY
37 [2:0] = RING1_DELAY */
38#define RNG_REV_REG 0x3c /* Revision register
39 [7:0] = REV_NB */
40#define RNG_MASK_REG 0x40 /* Mask and reset register
41 [2] = IT_EN
42 [1] = SOFTRESET
43 [0] = AUTOIDLE */
44#define RNG_SYSSTATUS 0x44 /* System status
45 [0] = RESETDONE */
46
47static void __iomem *rng_base;
48static struct clk *rng_ick;
49static struct platform_device *rng_dev;
50
51static inline u32 omap_rng_read_reg(int reg)
52{
53 return __raw_readl(rng_base + reg);
54}
55
56static inline void omap_rng_write_reg(int reg, u32 val)
57{
58 __raw_writel(val, rng_base + reg);
59}
60
61static int omap_rng_data_present(struct hwrng *rng, int wait)
62{
63 int data, i;
64
65 for (i = 0; i < 20; i++) {
66 data = omap_rng_read_reg(RNG_STAT_REG) ? 0 : 1;
67 if (data || !wait)
68 break;
69 /* RNG produces data fast enough (2+ MBit/sec, even
70 * during "rngtest" loads, that these delays don't
71 * seem to trigger. We *could* use the RNG IRQ, but
72 * that'd be higher overhead ... so why bother?
73 */
74 udelay(10);
75 }
76 return data;
77}
78
79static int omap_rng_data_read(struct hwrng *rng, u32 *data)
80{
81 *data = omap_rng_read_reg(RNG_OUT_REG);
82
83 return 4;
84}
85
86static struct hwrng omap_rng_ops = {
87 .name = "omap",
88 .data_present = omap_rng_data_present,
89 .data_read = omap_rng_data_read,
90};
91
92static int __devinit omap_rng_probe(struct platform_device *pdev)
93{
94 struct resource *res;
95 int ret;
96
97 /*
98 * A bit ugly, and it will never actually happen but there can
99 * be only one RNG and this catches any bork
100 */
101 if (rng_dev)
102 return -EBUSY;
103
104 if (cpu_is_omap24xx()) {
105 rng_ick = clk_get(&pdev->dev, "ick");
106 if (IS_ERR(rng_ick)) {
107 dev_err(&pdev->dev, "Could not get rng_ick\n");
108 ret = PTR_ERR(rng_ick);
109 return ret;
110 } else
111 clk_enable(rng_ick);
112 }
113
114 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
115
116 if (!res) {
117 ret = -ENOENT;
118 goto err_region;
119 }
120
121 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
122 ret = -EBUSY;
123 goto err_region;
124 }
125
126 dev_set_drvdata(&pdev->dev, res);
127 rng_base = ioremap(res->start, resource_size(res));
128 if (!rng_base) {
129 ret = -ENOMEM;
130 goto err_ioremap;
131 }
132
133 ret = hwrng_register(&omap_rng_ops);
134 if (ret)
135 goto err_register;
136
137 dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
138 omap_rng_read_reg(RNG_REV_REG));
139 omap_rng_write_reg(RNG_MASK_REG, 0x1);
140
141 rng_dev = pdev;
142
143 return 0;
144
145err_register:
146 iounmap(rng_base);
147 rng_base = NULL;
148err_ioremap:
149 release_mem_region(res->start, resource_size(res));
150err_region:
151 if (cpu_is_omap24xx()) {
152 clk_disable(rng_ick);
153 clk_put(rng_ick);
154 }
155 return ret;
156}
157
158static int __exit omap_rng_remove(struct platform_device *pdev)
159{
160 struct resource *res = dev_get_drvdata(&pdev->dev);
161
162 hwrng_unregister(&omap_rng_ops);
163
164 omap_rng_write_reg(RNG_MASK_REG, 0x0);
165
166 iounmap(rng_base);
167
168 if (cpu_is_omap24xx()) {
169 clk_disable(rng_ick);
170 clk_put(rng_ick);
171 }
172
173 release_mem_region(res->start, resource_size(res));
174 rng_base = NULL;
175
176 return 0;
177}
178
179#ifdef CONFIG_PM
180
181static int omap_rng_suspend(struct platform_device *pdev, pm_message_t message)
182{
183 omap_rng_write_reg(RNG_MASK_REG, 0x0);
184 return 0;
185}
186
187static int omap_rng_resume(struct platform_device *pdev)
188{
189 omap_rng_write_reg(RNG_MASK_REG, 0x1);
190 return 0;
191}
192
193#else
194
195#define omap_rng_suspend NULL
196#define omap_rng_resume NULL
197
198#endif
199
200/* work with hotplug and coldplug */
201MODULE_ALIAS("platform:omap_rng");
202
203static struct platform_driver omap_rng_driver = {
204 .driver = {
205 .name = "omap_rng",
206 .owner = THIS_MODULE,
207 },
208 .probe = omap_rng_probe,
209 .remove = __exit_p(omap_rng_remove),
210 .suspend = omap_rng_suspend,
211 .resume = omap_rng_resume
212};
213
214static int __init omap_rng_init(void)
215{
216 if (!cpu_is_omap16xx() && !cpu_is_omap24xx())
217 return -ENODEV;
218
219 return platform_driver_register(&omap_rng_driver);
220}
221
222static void __exit omap_rng_exit(void)
223{
224 platform_driver_unregister(&omap_rng_driver);
225}
226
227module_init(omap_rng_init);
228module_exit(omap_rng_exit);
229
230MODULE_AUTHOR("Deepak Saxena (and others)");
231MODULE_LICENSE("GPL");
1/*
2 * omap-rng.c - RNG driver for TI OMAP CPU family
3 *
4 * Author: Deepak Saxena <dsaxena@plexity.net>
5 *
6 * Copyright 2005 (c) MontaVista Software, Inc.
7 *
8 * Mostly based on original driver:
9 *
10 * Copyright (C) 2005 Nokia Corporation
11 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
12 *
13 * This file is licensed under the terms of the GNU General Public
14 * License version 2. This program is licensed "as is" without any
15 * warranty of any kind, whether express or implied.
16 */
17
18#include <linux/module.h>
19#include <linux/init.h>
20#include <linux/random.h>
21#include <linux/err.h>
22#include <linux/platform_device.h>
23#include <linux/hw_random.h>
24#include <linux/delay.h>
25#include <linux/slab.h>
26#include <linux/pm_runtime.h>
27#include <linux/of.h>
28#include <linux/of_device.h>
29#include <linux/of_address.h>
30#include <linux/interrupt.h>
31
32#include <asm/io.h>
33
34#define RNG_REG_STATUS_RDY (1 << 0)
35
36#define RNG_REG_INTACK_RDY_MASK (1 << 0)
37#define RNG_REG_INTACK_SHUTDOWN_OFLO_MASK (1 << 1)
38#define RNG_SHUTDOWN_OFLO_MASK (1 << 1)
39
40#define RNG_CONTROL_STARTUP_CYCLES_SHIFT 16
41#define RNG_CONTROL_STARTUP_CYCLES_MASK (0xffff << 16)
42#define RNG_CONTROL_ENABLE_TRNG_SHIFT 10
43#define RNG_CONTROL_ENABLE_TRNG_MASK (1 << 10)
44
45#define RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT 16
46#define RNG_CONFIG_MAX_REFIL_CYCLES_MASK (0xffff << 16)
47#define RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT 0
48#define RNG_CONFIG_MIN_REFIL_CYCLES_MASK (0xff << 0)
49
50#define RNG_CONTROL_STARTUP_CYCLES 0xff
51#define RNG_CONFIG_MIN_REFIL_CYCLES 0x21
52#define RNG_CONFIG_MAX_REFIL_CYCLES 0x22
53
54#define RNG_ALARMCNT_ALARM_TH_SHIFT 0x0
55#define RNG_ALARMCNT_ALARM_TH_MASK (0xff << 0)
56#define RNG_ALARMCNT_SHUTDOWN_TH_SHIFT 16
57#define RNG_ALARMCNT_SHUTDOWN_TH_MASK (0x1f << 16)
58#define RNG_ALARM_THRESHOLD 0xff
59#define RNG_SHUTDOWN_THRESHOLD 0x4
60
61#define RNG_REG_FROENABLE_MASK 0xffffff
62#define RNG_REG_FRODETUNE_MASK 0xffffff
63
64#define OMAP2_RNG_OUTPUT_SIZE 0x4
65#define OMAP4_RNG_OUTPUT_SIZE 0x8
66
67enum {
68 RNG_OUTPUT_L_REG = 0,
69 RNG_OUTPUT_H_REG,
70 RNG_STATUS_REG,
71 RNG_INTMASK_REG,
72 RNG_INTACK_REG,
73 RNG_CONTROL_REG,
74 RNG_CONFIG_REG,
75 RNG_ALARMCNT_REG,
76 RNG_FROENABLE_REG,
77 RNG_FRODETUNE_REG,
78 RNG_ALARMMASK_REG,
79 RNG_ALARMSTOP_REG,
80 RNG_REV_REG,
81 RNG_SYSCONFIG_REG,
82};
83
84static const u16 reg_map_omap2[] = {
85 [RNG_OUTPUT_L_REG] = 0x0,
86 [RNG_STATUS_REG] = 0x4,
87 [RNG_CONFIG_REG] = 0x28,
88 [RNG_REV_REG] = 0x3c,
89 [RNG_SYSCONFIG_REG] = 0x40,
90};
91
92static const u16 reg_map_omap4[] = {
93 [RNG_OUTPUT_L_REG] = 0x0,
94 [RNG_OUTPUT_H_REG] = 0x4,
95 [RNG_STATUS_REG] = 0x8,
96 [RNG_INTMASK_REG] = 0xc,
97 [RNG_INTACK_REG] = 0x10,
98 [RNG_CONTROL_REG] = 0x14,
99 [RNG_CONFIG_REG] = 0x18,
100 [RNG_ALARMCNT_REG] = 0x1c,
101 [RNG_FROENABLE_REG] = 0x20,
102 [RNG_FRODETUNE_REG] = 0x24,
103 [RNG_ALARMMASK_REG] = 0x28,
104 [RNG_ALARMSTOP_REG] = 0x2c,
105 [RNG_REV_REG] = 0x1FE0,
106 [RNG_SYSCONFIG_REG] = 0x1FE4,
107};
108
109struct omap_rng_dev;
110/**
111 * struct omap_rng_pdata - RNG IP block-specific data
112 * @regs: Pointer to the register offsets structure.
113 * @data_size: No. of bytes in RNG output.
114 * @data_present: Callback to determine if data is available.
115 * @init: Callback for IP specific initialization sequence.
116 * @cleanup: Callback for IP specific cleanup sequence.
117 */
118struct omap_rng_pdata {
119 u16 *regs;
120 u32 data_size;
121 u32 (*data_present)(struct omap_rng_dev *priv);
122 int (*init)(struct omap_rng_dev *priv);
123 void (*cleanup)(struct omap_rng_dev *priv);
124};
125
126struct omap_rng_dev {
127 void __iomem *base;
128 struct device *dev;
129 const struct omap_rng_pdata *pdata;
130};
131
132static inline u32 omap_rng_read(struct omap_rng_dev *priv, u16 reg)
133{
134 return __raw_readl(priv->base + priv->pdata->regs[reg]);
135}
136
137static inline void omap_rng_write(struct omap_rng_dev *priv, u16 reg,
138 u32 val)
139{
140 __raw_writel(val, priv->base + priv->pdata->regs[reg]);
141}
142
143static int omap_rng_data_present(struct hwrng *rng, int wait)
144{
145 struct omap_rng_dev *priv;
146 int data, i;
147
148 priv = (struct omap_rng_dev *)rng->priv;
149
150 for (i = 0; i < 20; i++) {
151 data = priv->pdata->data_present(priv);
152 if (data || !wait)
153 break;
154 /* RNG produces data fast enough (2+ MBit/sec, even
155 * during "rngtest" loads, that these delays don't
156 * seem to trigger. We *could* use the RNG IRQ, but
157 * that'd be higher overhead ... so why bother?
158 */
159 udelay(10);
160 }
161 return data;
162}
163
164static int omap_rng_data_read(struct hwrng *rng, u32 *data)
165{
166 struct omap_rng_dev *priv;
167 u32 data_size, i;
168
169 priv = (struct omap_rng_dev *)rng->priv;
170 data_size = priv->pdata->data_size;
171
172 for (i = 0; i < data_size / sizeof(u32); i++)
173 data[i] = omap_rng_read(priv, RNG_OUTPUT_L_REG + i);
174
175 if (priv->pdata->regs[RNG_INTACK_REG])
176 omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_RDY_MASK);
177 return data_size;
178}
179
180static int omap_rng_init(struct hwrng *rng)
181{
182 struct omap_rng_dev *priv;
183
184 priv = (struct omap_rng_dev *)rng->priv;
185 return priv->pdata->init(priv);
186}
187
188static void omap_rng_cleanup(struct hwrng *rng)
189{
190 struct omap_rng_dev *priv;
191
192 priv = (struct omap_rng_dev *)rng->priv;
193 priv->pdata->cleanup(priv);
194}
195
196static struct hwrng omap_rng_ops = {
197 .name = "omap",
198 .data_present = omap_rng_data_present,
199 .data_read = omap_rng_data_read,
200 .init = omap_rng_init,
201 .cleanup = omap_rng_cleanup,
202};
203
204static inline u32 omap2_rng_data_present(struct omap_rng_dev *priv)
205{
206 return omap_rng_read(priv, RNG_STATUS_REG) ? 0 : 1;
207}
208
209static int omap2_rng_init(struct omap_rng_dev *priv)
210{
211 omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x1);
212 return 0;
213}
214
215static void omap2_rng_cleanup(struct omap_rng_dev *priv)
216{
217 omap_rng_write(priv, RNG_SYSCONFIG_REG, 0x0);
218}
219
220static struct omap_rng_pdata omap2_rng_pdata = {
221 .regs = (u16 *)reg_map_omap2,
222 .data_size = OMAP2_RNG_OUTPUT_SIZE,
223 .data_present = omap2_rng_data_present,
224 .init = omap2_rng_init,
225 .cleanup = omap2_rng_cleanup,
226};
227
228#if defined(CONFIG_OF)
229static inline u32 omap4_rng_data_present(struct omap_rng_dev *priv)
230{
231 return omap_rng_read(priv, RNG_STATUS_REG) & RNG_REG_STATUS_RDY;
232}
233
234static int omap4_rng_init(struct omap_rng_dev *priv)
235{
236 u32 val;
237
238 /* Return if RNG is already running. */
239 if (omap_rng_read(priv, RNG_CONFIG_REG) & RNG_CONTROL_ENABLE_TRNG_MASK)
240 return 0;
241
242 val = RNG_CONFIG_MIN_REFIL_CYCLES << RNG_CONFIG_MIN_REFIL_CYCLES_SHIFT;
243 val |= RNG_CONFIG_MAX_REFIL_CYCLES << RNG_CONFIG_MAX_REFIL_CYCLES_SHIFT;
244 omap_rng_write(priv, RNG_CONFIG_REG, val);
245
246 omap_rng_write(priv, RNG_FRODETUNE_REG, 0x0);
247 omap_rng_write(priv, RNG_FROENABLE_REG, RNG_REG_FROENABLE_MASK);
248 val = RNG_ALARM_THRESHOLD << RNG_ALARMCNT_ALARM_TH_SHIFT;
249 val |= RNG_SHUTDOWN_THRESHOLD << RNG_ALARMCNT_SHUTDOWN_TH_SHIFT;
250 omap_rng_write(priv, RNG_ALARMCNT_REG, val);
251
252 val = RNG_CONTROL_STARTUP_CYCLES << RNG_CONTROL_STARTUP_CYCLES_SHIFT;
253 val |= RNG_CONTROL_ENABLE_TRNG_MASK;
254 omap_rng_write(priv, RNG_CONTROL_REG, val);
255
256 return 0;
257}
258
259static void omap4_rng_cleanup(struct omap_rng_dev *priv)
260{
261 int val;
262
263 val = omap_rng_read(priv, RNG_CONTROL_REG);
264 val &= ~RNG_CONTROL_ENABLE_TRNG_MASK;
265 omap_rng_write(priv, RNG_CONFIG_REG, val);
266}
267
268static irqreturn_t omap4_rng_irq(int irq, void *dev_id)
269{
270 struct omap_rng_dev *priv = dev_id;
271 u32 fro_detune, fro_enable;
272
273 /*
274 * Interrupt raised by a fro shutdown threshold, do the following:
275 * 1. Clear the alarm events.
276 * 2. De tune the FROs which are shutdown.
277 * 3. Re enable the shutdown FROs.
278 */
279 omap_rng_write(priv, RNG_ALARMMASK_REG, 0x0);
280 omap_rng_write(priv, RNG_ALARMSTOP_REG, 0x0);
281
282 fro_enable = omap_rng_read(priv, RNG_FROENABLE_REG);
283 fro_detune = ~fro_enable & RNG_REG_FRODETUNE_MASK;
284 fro_detune = fro_detune | omap_rng_read(priv, RNG_FRODETUNE_REG);
285 fro_enable = RNG_REG_FROENABLE_MASK;
286
287 omap_rng_write(priv, RNG_FRODETUNE_REG, fro_detune);
288 omap_rng_write(priv, RNG_FROENABLE_REG, fro_enable);
289
290 omap_rng_write(priv, RNG_INTACK_REG, RNG_REG_INTACK_SHUTDOWN_OFLO_MASK);
291
292 return IRQ_HANDLED;
293}
294
295static struct omap_rng_pdata omap4_rng_pdata = {
296 .regs = (u16 *)reg_map_omap4,
297 .data_size = OMAP4_RNG_OUTPUT_SIZE,
298 .data_present = omap4_rng_data_present,
299 .init = omap4_rng_init,
300 .cleanup = omap4_rng_cleanup,
301};
302
303static const struct of_device_id omap_rng_of_match[] = {
304 {
305 .compatible = "ti,omap2-rng",
306 .data = &omap2_rng_pdata,
307 },
308 {
309 .compatible = "ti,omap4-rng",
310 .data = &omap4_rng_pdata,
311 },
312 {},
313};
314MODULE_DEVICE_TABLE(of, omap_rng_of_match);
315
316static int of_get_omap_rng_device_details(struct omap_rng_dev *priv,
317 struct platform_device *pdev)
318{
319 const struct of_device_id *match;
320 struct device *dev = &pdev->dev;
321 int irq, err;
322
323 match = of_match_device(of_match_ptr(omap_rng_of_match), dev);
324 if (!match) {
325 dev_err(dev, "no compatible OF match\n");
326 return -EINVAL;
327 }
328 priv->pdata = match->data;
329
330 if (of_device_is_compatible(dev->of_node, "ti,omap4-rng")) {
331 irq = platform_get_irq(pdev, 0);
332 if (irq < 0) {
333 dev_err(dev, "%s: error getting IRQ resource - %d\n",
334 __func__, irq);
335 return irq;
336 }
337
338 err = devm_request_irq(dev, irq, omap4_rng_irq,
339 IRQF_TRIGGER_NONE, dev_name(dev), priv);
340 if (err) {
341 dev_err(dev, "unable to request irq %d, err = %d\n",
342 irq, err);
343 return err;
344 }
345 omap_rng_write(priv, RNG_INTMASK_REG, RNG_SHUTDOWN_OFLO_MASK);
346 }
347 return 0;
348}
349#else
350static int of_get_omap_rng_device_details(struct omap_rng_dev *omap_rng,
351 struct platform_device *pdev)
352{
353 return -EINVAL;
354}
355#endif
356
357static int get_omap_rng_device_details(struct omap_rng_dev *omap_rng)
358{
359 /* Only OMAP2/3 can be non-DT */
360 omap_rng->pdata = &omap2_rng_pdata;
361 return 0;
362}
363
364static int omap_rng_probe(struct platform_device *pdev)
365{
366 struct omap_rng_dev *priv;
367 struct resource *res;
368 struct device *dev = &pdev->dev;
369 int ret;
370
371 priv = devm_kzalloc(dev, sizeof(struct omap_rng_dev), GFP_KERNEL);
372 if (!priv) {
373 dev_err(&pdev->dev, "could not allocate memory\n");
374 return -ENOMEM;
375 };
376
377 omap_rng_ops.priv = (unsigned long)priv;
378 platform_set_drvdata(pdev, priv);
379 priv->dev = dev;
380
381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
382 priv->base = devm_ioremap_resource(dev, res);
383 if (IS_ERR(priv->base)) {
384 ret = PTR_ERR(priv->base);
385 goto err_ioremap;
386 }
387
388 pm_runtime_enable(&pdev->dev);
389 pm_runtime_get_sync(&pdev->dev);
390
391 ret = (dev->of_node) ? of_get_omap_rng_device_details(priv, pdev) :
392 get_omap_rng_device_details(priv);
393 if (ret)
394 goto err_ioremap;
395
396 ret = hwrng_register(&omap_rng_ops);
397 if (ret)
398 goto err_register;
399
400 dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
401 omap_rng_read(priv, RNG_REV_REG));
402
403 return 0;
404
405err_register:
406 priv->base = NULL;
407 pm_runtime_disable(&pdev->dev);
408err_ioremap:
409 dev_err(dev, "initialization failed.\n");
410 return ret;
411}
412
413static int __exit omap_rng_remove(struct platform_device *pdev)
414{
415 struct omap_rng_dev *priv = platform_get_drvdata(pdev);
416
417 hwrng_unregister(&omap_rng_ops);
418
419 priv->pdata->cleanup(priv);
420
421 pm_runtime_put_sync(&pdev->dev);
422 pm_runtime_disable(&pdev->dev);
423
424 return 0;
425}
426
427#ifdef CONFIG_PM_SLEEP
428
429static int omap_rng_suspend(struct device *dev)
430{
431 struct omap_rng_dev *priv = dev_get_drvdata(dev);
432
433 priv->pdata->cleanup(priv);
434 pm_runtime_put_sync(dev);
435
436 return 0;
437}
438
439static int omap_rng_resume(struct device *dev)
440{
441 struct omap_rng_dev *priv = dev_get_drvdata(dev);
442
443 pm_runtime_get_sync(dev);
444 priv->pdata->init(priv);
445
446 return 0;
447}
448
449static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
450#define OMAP_RNG_PM (&omap_rng_pm)
451
452#else
453
454#define OMAP_RNG_PM NULL
455
456#endif
457
458static struct platform_driver omap_rng_driver = {
459 .driver = {
460 .name = "omap_rng",
461 .owner = THIS_MODULE,
462 .pm = OMAP_RNG_PM,
463 .of_match_table = of_match_ptr(omap_rng_of_match),
464 },
465 .probe = omap_rng_probe,
466 .remove = __exit_p(omap_rng_remove),
467};
468
469module_platform_driver(omap_rng_driver);
470MODULE_ALIAS("platform:omap_rng");
471MODULE_AUTHOR("Deepak Saxena (and others)");
472MODULE_LICENSE("GPL");