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1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12
13#include <asm/apic.h>
14#include <asm/io_apic.h>
15#include <asm/irq.h>
16#include <asm/idle.h>
17#include <asm/mce.h>
18#include <asm/hw_irq.h>
19
20atomic_t irq_err_count;
21
22/* Function pointer for generic interrupt vector handling */
23void (*x86_platform_ipi_callback)(void) = NULL;
24
25/*
26 * 'what should we do if we get a hw irq event on an illegal vector'.
27 * each architecture has to answer this themselves.
28 */
29void ack_bad_irq(unsigned int irq)
30{
31 if (printk_ratelimit())
32 pr_err("unexpected IRQ trap at vector %02x\n", irq);
33
34 /*
35 * Currently unexpected vectors happen only on SMP and APIC.
36 * We _must_ ack these because every local APIC has only N
37 * irq slots per priority level, and a 'hanging, unacked' IRQ
38 * holds up an irq slot - in excessive cases (when multiple
39 * unexpected vectors occur) that might lock up the APIC
40 * completely.
41 * But only ack when the APIC is enabled -AK
42 */
43 ack_APIC_irq();
44}
45
46#define irq_stats(x) (&per_cpu(irq_stat, x))
47/*
48 * /proc/interrupts printing for arch specific interrupts
49 */
50int arch_show_interrupts(struct seq_file *p, int prec)
51{
52 int j;
53
54 seq_printf(p, "%*s: ", prec, "NMI");
55 for_each_online_cpu(j)
56 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
57 seq_printf(p, " Non-maskable interrupts\n");
58#ifdef CONFIG_X86_LOCAL_APIC
59 seq_printf(p, "%*s: ", prec, "LOC");
60 for_each_online_cpu(j)
61 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
62 seq_printf(p, " Local timer interrupts\n");
63
64 seq_printf(p, "%*s: ", prec, "SPU");
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
67 seq_printf(p, " Spurious interrupts\n");
68 seq_printf(p, "%*s: ", prec, "PMI");
69 for_each_online_cpu(j)
70 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
71 seq_printf(p, " Performance monitoring interrupts\n");
72 seq_printf(p, "%*s: ", prec, "IWI");
73 for_each_online_cpu(j)
74 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
75 seq_printf(p, " IRQ work interrupts\n");
76#endif
77 if (x86_platform_ipi_callback) {
78 seq_printf(p, "%*s: ", prec, "PLT");
79 for_each_online_cpu(j)
80 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
81 seq_printf(p, " Platform interrupts\n");
82 }
83#ifdef CONFIG_SMP
84 seq_printf(p, "%*s: ", prec, "RES");
85 for_each_online_cpu(j)
86 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
87 seq_printf(p, " Rescheduling interrupts\n");
88 seq_printf(p, "%*s: ", prec, "CAL");
89 for_each_online_cpu(j)
90 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count);
91 seq_printf(p, " Function call interrupts\n");
92 seq_printf(p, "%*s: ", prec, "TLB");
93 for_each_online_cpu(j)
94 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
95 seq_printf(p, " TLB shootdowns\n");
96#endif
97#ifdef CONFIG_X86_THERMAL_VECTOR
98 seq_printf(p, "%*s: ", prec, "TRM");
99 for_each_online_cpu(j)
100 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
101 seq_printf(p, " Thermal event interrupts\n");
102#endif
103#ifdef CONFIG_X86_MCE_THRESHOLD
104 seq_printf(p, "%*s: ", prec, "THR");
105 for_each_online_cpu(j)
106 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
107 seq_printf(p, " Threshold APIC interrupts\n");
108#endif
109#ifdef CONFIG_X86_MCE
110 seq_printf(p, "%*s: ", prec, "MCE");
111 for_each_online_cpu(j)
112 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
113 seq_printf(p, " Machine check exceptions\n");
114 seq_printf(p, "%*s: ", prec, "MCP");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
117 seq_printf(p, " Machine check polls\n");
118#endif
119 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
120#if defined(CONFIG_X86_IO_APIC)
121 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
122#endif
123 return 0;
124}
125
126/*
127 * /proc/stat helpers
128 */
129u64 arch_irq_stat_cpu(unsigned int cpu)
130{
131 u64 sum = irq_stats(cpu)->__nmi_count;
132
133#ifdef CONFIG_X86_LOCAL_APIC
134 sum += irq_stats(cpu)->apic_timer_irqs;
135 sum += irq_stats(cpu)->irq_spurious_count;
136 sum += irq_stats(cpu)->apic_perf_irqs;
137 sum += irq_stats(cpu)->apic_irq_work_irqs;
138#endif
139 if (x86_platform_ipi_callback)
140 sum += irq_stats(cpu)->x86_platform_ipis;
141#ifdef CONFIG_SMP
142 sum += irq_stats(cpu)->irq_resched_count;
143 sum += irq_stats(cpu)->irq_call_count;
144 sum += irq_stats(cpu)->irq_tlb_count;
145#endif
146#ifdef CONFIG_X86_THERMAL_VECTOR
147 sum += irq_stats(cpu)->irq_thermal_count;
148#endif
149#ifdef CONFIG_X86_MCE_THRESHOLD
150 sum += irq_stats(cpu)->irq_threshold_count;
151#endif
152#ifdef CONFIG_X86_MCE
153 sum += per_cpu(mce_exception_count, cpu);
154 sum += per_cpu(mce_poll_count, cpu);
155#endif
156 return sum;
157}
158
159u64 arch_irq_stat(void)
160{
161 u64 sum = atomic_read(&irq_err_count);
162
163#ifdef CONFIG_X86_IO_APIC
164 sum += atomic_read(&irq_mis_count);
165#endif
166 return sum;
167}
168
169
170/*
171 * do_IRQ handles all normal device IRQ's (the special
172 * SMP cross-CPU interrupts have their own specific
173 * handlers).
174 */
175unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
176{
177 struct pt_regs *old_regs = set_irq_regs(regs);
178
179 /* high bit used in ret_from_ code */
180 unsigned vector = ~regs->orig_ax;
181 unsigned irq;
182
183 exit_idle();
184 irq_enter();
185
186 irq = __this_cpu_read(vector_irq[vector]);
187
188 if (!handle_irq(irq, regs)) {
189 ack_APIC_irq();
190
191 if (printk_ratelimit())
192 pr_emerg("%s: %d.%d No irq handler for vector (irq %d)\n",
193 __func__, smp_processor_id(), vector, irq);
194 }
195
196 irq_exit();
197
198 set_irq_regs(old_regs);
199 return 1;
200}
201
202/*
203 * Handler for X86_PLATFORM_IPI_VECTOR.
204 */
205void smp_x86_platform_ipi(struct pt_regs *regs)
206{
207 struct pt_regs *old_regs = set_irq_regs(regs);
208
209 ack_APIC_irq();
210
211 exit_idle();
212
213 irq_enter();
214
215 inc_irq_stat(x86_platform_ipis);
216
217 if (x86_platform_ipi_callback)
218 x86_platform_ipi_callback();
219
220 irq_exit();
221
222 set_irq_regs(old_regs);
223}
224
225EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
226
227#ifdef CONFIG_HOTPLUG_CPU
228/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
229void fixup_irqs(void)
230{
231 unsigned int irq, vector;
232 static int warned;
233 struct irq_desc *desc;
234 struct irq_data *data;
235 struct irq_chip *chip;
236
237 for_each_irq_desc(irq, desc) {
238 int break_affinity = 0;
239 int set_affinity = 1;
240 const struct cpumask *affinity;
241
242 if (!desc)
243 continue;
244 if (irq == 2)
245 continue;
246
247 /* interrupt's are disabled at this point */
248 raw_spin_lock(&desc->lock);
249
250 data = irq_desc_get_irq_data(desc);
251 affinity = data->affinity;
252 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
253 cpumask_subset(affinity, cpu_online_mask)) {
254 raw_spin_unlock(&desc->lock);
255 continue;
256 }
257
258 /*
259 * Complete the irq move. This cpu is going down and for
260 * non intr-remapping case, we can't wait till this interrupt
261 * arrives at this cpu before completing the irq move.
262 */
263 irq_force_complete_move(irq);
264
265 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
266 break_affinity = 1;
267 affinity = cpu_all_mask;
268 }
269
270 chip = irq_data_get_irq_chip(data);
271 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
272 chip->irq_mask(data);
273
274 if (chip->irq_set_affinity)
275 chip->irq_set_affinity(data, affinity, true);
276 else if (!(warned++))
277 set_affinity = 0;
278
279 if (!irqd_can_move_in_process_context(data) &&
280 !irqd_irq_disabled(data) && chip->irq_unmask)
281 chip->irq_unmask(data);
282
283 raw_spin_unlock(&desc->lock);
284
285 if (break_affinity && set_affinity)
286 printk("Broke affinity for irq %i\n", irq);
287 else if (!set_affinity)
288 printk("Cannot set affinity for irq %i\n", irq);
289 }
290
291 /*
292 * We can remove mdelay() and then send spuriuous interrupts to
293 * new cpu targets for all the irqs that were handled previously by
294 * this cpu. While it works, I have seen spurious interrupt messages
295 * (nothing wrong but still...).
296 *
297 * So for now, retain mdelay(1) and check the IRR and then send those
298 * interrupts to new targets as this cpu is already offlined...
299 */
300 mdelay(1);
301
302 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
303 unsigned int irr;
304
305 if (__this_cpu_read(vector_irq[vector]) < 0)
306 continue;
307
308 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
309 if (irr & (1 << (vector % 32))) {
310 irq = __this_cpu_read(vector_irq[vector]);
311
312 desc = irq_to_desc(irq);
313 data = irq_desc_get_irq_data(desc);
314 chip = irq_data_get_irq_chip(data);
315 raw_spin_lock(&desc->lock);
316 if (chip->irq_retrigger)
317 chip->irq_retrigger(data);
318 raw_spin_unlock(&desc->lock);
319 }
320 }
321}
322#endif
1/*
2 * Common interrupt code for 32 and 64 bit
3 */
4#include <linux/cpu.h>
5#include <linux/interrupt.h>
6#include <linux/kernel_stat.h>
7#include <linux/of.h>
8#include <linux/seq_file.h>
9#include <linux/smp.h>
10#include <linux/ftrace.h>
11#include <linux/delay.h>
12#include <linux/export.h>
13
14#include <asm/apic.h>
15#include <asm/io_apic.h>
16#include <asm/irq.h>
17#include <asm/idle.h>
18#include <asm/mce.h>
19#include <asm/hw_irq.h>
20#include <asm/desc.h>
21
22#define CREATE_TRACE_POINTS
23#include <asm/trace/irq_vectors.h>
24
25atomic_t irq_err_count;
26
27/* Function pointer for generic interrupt vector handling */
28void (*x86_platform_ipi_callback)(void) = NULL;
29
30/*
31 * 'what should we do if we get a hw irq event on an illegal vector'.
32 * each architecture has to answer this themselves.
33 */
34void ack_bad_irq(unsigned int irq)
35{
36 if (printk_ratelimit())
37 pr_err("unexpected IRQ trap at vector %02x\n", irq);
38
39 /*
40 * Currently unexpected vectors happen only on SMP and APIC.
41 * We _must_ ack these because every local APIC has only N
42 * irq slots per priority level, and a 'hanging, unacked' IRQ
43 * holds up an irq slot - in excessive cases (when multiple
44 * unexpected vectors occur) that might lock up the APIC
45 * completely.
46 * But only ack when the APIC is enabled -AK
47 */
48 ack_APIC_irq();
49}
50
51#define irq_stats(x) (&per_cpu(irq_stat, x))
52/*
53 * /proc/interrupts printing for arch specific interrupts
54 */
55int arch_show_interrupts(struct seq_file *p, int prec)
56{
57 int j;
58
59 seq_printf(p, "%*s: ", prec, "NMI");
60 for_each_online_cpu(j)
61 seq_printf(p, "%10u ", irq_stats(j)->__nmi_count);
62 seq_printf(p, " Non-maskable interrupts\n");
63#ifdef CONFIG_X86_LOCAL_APIC
64 seq_printf(p, "%*s: ", prec, "LOC");
65 for_each_online_cpu(j)
66 seq_printf(p, "%10u ", irq_stats(j)->apic_timer_irqs);
67 seq_printf(p, " Local timer interrupts\n");
68
69 seq_printf(p, "%*s: ", prec, "SPU");
70 for_each_online_cpu(j)
71 seq_printf(p, "%10u ", irq_stats(j)->irq_spurious_count);
72 seq_printf(p, " Spurious interrupts\n");
73 seq_printf(p, "%*s: ", prec, "PMI");
74 for_each_online_cpu(j)
75 seq_printf(p, "%10u ", irq_stats(j)->apic_perf_irqs);
76 seq_printf(p, " Performance monitoring interrupts\n");
77 seq_printf(p, "%*s: ", prec, "IWI");
78 for_each_online_cpu(j)
79 seq_printf(p, "%10u ", irq_stats(j)->apic_irq_work_irqs);
80 seq_printf(p, " IRQ work interrupts\n");
81 seq_printf(p, "%*s: ", prec, "RTR");
82 for_each_online_cpu(j)
83 seq_printf(p, "%10u ", irq_stats(j)->icr_read_retry_count);
84 seq_printf(p, " APIC ICR read retries\n");
85#endif
86 if (x86_platform_ipi_callback) {
87 seq_printf(p, "%*s: ", prec, "PLT");
88 for_each_online_cpu(j)
89 seq_printf(p, "%10u ", irq_stats(j)->x86_platform_ipis);
90 seq_printf(p, " Platform interrupts\n");
91 }
92#ifdef CONFIG_SMP
93 seq_printf(p, "%*s: ", prec, "RES");
94 for_each_online_cpu(j)
95 seq_printf(p, "%10u ", irq_stats(j)->irq_resched_count);
96 seq_printf(p, " Rescheduling interrupts\n");
97 seq_printf(p, "%*s: ", prec, "CAL");
98 for_each_online_cpu(j)
99 seq_printf(p, "%10u ", irq_stats(j)->irq_call_count -
100 irq_stats(j)->irq_tlb_count);
101 seq_printf(p, " Function call interrupts\n");
102 seq_printf(p, "%*s: ", prec, "TLB");
103 for_each_online_cpu(j)
104 seq_printf(p, "%10u ", irq_stats(j)->irq_tlb_count);
105 seq_printf(p, " TLB shootdowns\n");
106#endif
107#ifdef CONFIG_X86_THERMAL_VECTOR
108 seq_printf(p, "%*s: ", prec, "TRM");
109 for_each_online_cpu(j)
110 seq_printf(p, "%10u ", irq_stats(j)->irq_thermal_count);
111 seq_printf(p, " Thermal event interrupts\n");
112#endif
113#ifdef CONFIG_X86_MCE_THRESHOLD
114 seq_printf(p, "%*s: ", prec, "THR");
115 for_each_online_cpu(j)
116 seq_printf(p, "%10u ", irq_stats(j)->irq_threshold_count);
117 seq_printf(p, " Threshold APIC interrupts\n");
118#endif
119#ifdef CONFIG_X86_MCE
120 seq_printf(p, "%*s: ", prec, "MCE");
121 for_each_online_cpu(j)
122 seq_printf(p, "%10u ", per_cpu(mce_exception_count, j));
123 seq_printf(p, " Machine check exceptions\n");
124 seq_printf(p, "%*s: ", prec, "MCP");
125 for_each_online_cpu(j)
126 seq_printf(p, "%10u ", per_cpu(mce_poll_count, j));
127 seq_printf(p, " Machine check polls\n");
128#endif
129#if IS_ENABLED(CONFIG_HYPERV) || defined(CONFIG_XEN)
130 seq_printf(p, "%*s: ", prec, "THR");
131 for_each_online_cpu(j)
132 seq_printf(p, "%10u ", irq_stats(j)->irq_hv_callback_count);
133 seq_printf(p, " Hypervisor callback interrupts\n");
134#endif
135 seq_printf(p, "%*s: %10u\n", prec, "ERR", atomic_read(&irq_err_count));
136#if defined(CONFIG_X86_IO_APIC)
137 seq_printf(p, "%*s: %10u\n", prec, "MIS", atomic_read(&irq_mis_count));
138#endif
139 return 0;
140}
141
142/*
143 * /proc/stat helpers
144 */
145u64 arch_irq_stat_cpu(unsigned int cpu)
146{
147 u64 sum = irq_stats(cpu)->__nmi_count;
148
149#ifdef CONFIG_X86_LOCAL_APIC
150 sum += irq_stats(cpu)->apic_timer_irqs;
151 sum += irq_stats(cpu)->irq_spurious_count;
152 sum += irq_stats(cpu)->apic_perf_irqs;
153 sum += irq_stats(cpu)->apic_irq_work_irqs;
154 sum += irq_stats(cpu)->icr_read_retry_count;
155#endif
156 if (x86_platform_ipi_callback)
157 sum += irq_stats(cpu)->x86_platform_ipis;
158#ifdef CONFIG_SMP
159 sum += irq_stats(cpu)->irq_resched_count;
160 sum += irq_stats(cpu)->irq_call_count;
161#endif
162#ifdef CONFIG_X86_THERMAL_VECTOR
163 sum += irq_stats(cpu)->irq_thermal_count;
164#endif
165#ifdef CONFIG_X86_MCE_THRESHOLD
166 sum += irq_stats(cpu)->irq_threshold_count;
167#endif
168#ifdef CONFIG_X86_MCE
169 sum += per_cpu(mce_exception_count, cpu);
170 sum += per_cpu(mce_poll_count, cpu);
171#endif
172 return sum;
173}
174
175u64 arch_irq_stat(void)
176{
177 u64 sum = atomic_read(&irq_err_count);
178 return sum;
179}
180
181
182/*
183 * do_IRQ handles all normal device IRQ's (the special
184 * SMP cross-CPU interrupts have their own specific
185 * handlers).
186 */
187__visible unsigned int __irq_entry do_IRQ(struct pt_regs *regs)
188{
189 struct pt_regs *old_regs = set_irq_regs(regs);
190
191 /* high bit used in ret_from_ code */
192 unsigned vector = ~regs->orig_ax;
193 unsigned irq;
194
195 irq_enter();
196 exit_idle();
197
198 irq = __this_cpu_read(vector_irq[vector]);
199
200 if (!handle_irq(irq, regs)) {
201 ack_APIC_irq();
202
203 if (irq != VECTOR_RETRIGGERED) {
204 pr_emerg_ratelimited("%s: %d.%d No irq handler for vector (irq %d)\n",
205 __func__, smp_processor_id(),
206 vector, irq);
207 } else {
208 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
209 }
210 }
211
212 irq_exit();
213
214 set_irq_regs(old_regs);
215 return 1;
216}
217
218/*
219 * Handler for X86_PLATFORM_IPI_VECTOR.
220 */
221void __smp_x86_platform_ipi(void)
222{
223 inc_irq_stat(x86_platform_ipis);
224
225 if (x86_platform_ipi_callback)
226 x86_platform_ipi_callback();
227}
228
229__visible void smp_x86_platform_ipi(struct pt_regs *regs)
230{
231 struct pt_regs *old_regs = set_irq_regs(regs);
232
233 entering_ack_irq();
234 __smp_x86_platform_ipi();
235 exiting_irq();
236 set_irq_regs(old_regs);
237}
238
239#ifdef CONFIG_HAVE_KVM
240/*
241 * Handler for POSTED_INTERRUPT_VECTOR.
242 */
243__visible void smp_kvm_posted_intr_ipi(struct pt_regs *regs)
244{
245 struct pt_regs *old_regs = set_irq_regs(regs);
246
247 ack_APIC_irq();
248
249 irq_enter();
250
251 exit_idle();
252
253 inc_irq_stat(kvm_posted_intr_ipis);
254
255 irq_exit();
256
257 set_irq_regs(old_regs);
258}
259#endif
260
261__visible void smp_trace_x86_platform_ipi(struct pt_regs *regs)
262{
263 struct pt_regs *old_regs = set_irq_regs(regs);
264
265 entering_ack_irq();
266 trace_x86_platform_ipi_entry(X86_PLATFORM_IPI_VECTOR);
267 __smp_x86_platform_ipi();
268 trace_x86_platform_ipi_exit(X86_PLATFORM_IPI_VECTOR);
269 exiting_irq();
270 set_irq_regs(old_regs);
271}
272
273EXPORT_SYMBOL_GPL(vector_used_by_percpu_irq);
274
275#ifdef CONFIG_HOTPLUG_CPU
276
277/* These two declarations are only used in check_irq_vectors_for_cpu_disable()
278 * below, which is protected by stop_machine(). Putting them on the stack
279 * results in a stack frame overflow. Dynamically allocating could result in a
280 * failure so declare these two cpumasks as global.
281 */
282static struct cpumask affinity_new, online_new;
283
284/*
285 * This cpu is going to be removed and its vectors migrated to the remaining
286 * online cpus. Check to see if there are enough vectors in the remaining cpus.
287 * This function is protected by stop_machine().
288 */
289int check_irq_vectors_for_cpu_disable(void)
290{
291 int irq, cpu;
292 unsigned int this_cpu, vector, this_count, count;
293 struct irq_desc *desc;
294 struct irq_data *data;
295
296 this_cpu = smp_processor_id();
297 cpumask_copy(&online_new, cpu_online_mask);
298 cpu_clear(this_cpu, online_new);
299
300 this_count = 0;
301 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
302 irq = __this_cpu_read(vector_irq[vector]);
303 if (irq >= 0) {
304 desc = irq_to_desc(irq);
305 data = irq_desc_get_irq_data(desc);
306 cpumask_copy(&affinity_new, data->affinity);
307 cpu_clear(this_cpu, affinity_new);
308
309 /* Do not count inactive or per-cpu irqs. */
310 if (!irq_has_action(irq) || irqd_is_per_cpu(data))
311 continue;
312
313 /*
314 * A single irq may be mapped to multiple
315 * cpu's vector_irq[] (for example IOAPIC cluster
316 * mode). In this case we have two
317 * possibilities:
318 *
319 * 1) the resulting affinity mask is empty; that is
320 * this the down'd cpu is the last cpu in the irq's
321 * affinity mask, or
322 *
323 * 2) the resulting affinity mask is no longer
324 * a subset of the online cpus but the affinity
325 * mask is not zero; that is the down'd cpu is the
326 * last online cpu in a user set affinity mask.
327 */
328 if (cpumask_empty(&affinity_new) ||
329 !cpumask_subset(&affinity_new, &online_new))
330 this_count++;
331 }
332 }
333
334 count = 0;
335 for_each_online_cpu(cpu) {
336 if (cpu == this_cpu)
337 continue;
338 /*
339 * We scan from FIRST_EXTERNAL_VECTOR to first system
340 * vector. If the vector is marked in the used vectors
341 * bitmap or an irq is assigned to it, we don't count
342 * it as available.
343 */
344 for (vector = FIRST_EXTERNAL_VECTOR;
345 vector < first_system_vector; vector++) {
346 if (!test_bit(vector, used_vectors) &&
347 per_cpu(vector_irq, cpu)[vector] < 0)
348 count++;
349 }
350 }
351
352 if (count < this_count) {
353 pr_warn("CPU %d disable failed: CPU has %u vectors assigned and there are only %u available.\n",
354 this_cpu, this_count, count);
355 return -ERANGE;
356 }
357 return 0;
358}
359
360/* A cpu has been removed from cpu_online_mask. Reset irq affinities. */
361void fixup_irqs(void)
362{
363 unsigned int irq, vector;
364 static int warned;
365 struct irq_desc *desc;
366 struct irq_data *data;
367 struct irq_chip *chip;
368
369 for_each_irq_desc(irq, desc) {
370 int break_affinity = 0;
371 int set_affinity = 1;
372 const struct cpumask *affinity;
373
374 if (!desc)
375 continue;
376 if (irq == 2)
377 continue;
378
379 /* interrupt's are disabled at this point */
380 raw_spin_lock(&desc->lock);
381
382 data = irq_desc_get_irq_data(desc);
383 affinity = data->affinity;
384 if (!irq_has_action(irq) || irqd_is_per_cpu(data) ||
385 cpumask_subset(affinity, cpu_online_mask)) {
386 raw_spin_unlock(&desc->lock);
387 continue;
388 }
389
390 /*
391 * Complete the irq move. This cpu is going down and for
392 * non intr-remapping case, we can't wait till this interrupt
393 * arrives at this cpu before completing the irq move.
394 */
395 irq_force_complete_move(irq);
396
397 if (cpumask_any_and(affinity, cpu_online_mask) >= nr_cpu_ids) {
398 break_affinity = 1;
399 affinity = cpu_online_mask;
400 }
401
402 chip = irq_data_get_irq_chip(data);
403 if (!irqd_can_move_in_process_context(data) && chip->irq_mask)
404 chip->irq_mask(data);
405
406 if (chip->irq_set_affinity)
407 chip->irq_set_affinity(data, affinity, true);
408 else if (!(warned++))
409 set_affinity = 0;
410
411 /*
412 * We unmask if the irq was not marked masked by the
413 * core code. That respects the lazy irq disable
414 * behaviour.
415 */
416 if (!irqd_can_move_in_process_context(data) &&
417 !irqd_irq_masked(data) && chip->irq_unmask)
418 chip->irq_unmask(data);
419
420 raw_spin_unlock(&desc->lock);
421
422 if (break_affinity && set_affinity)
423 pr_notice("Broke affinity for irq %i\n", irq);
424 else if (!set_affinity)
425 pr_notice("Cannot set affinity for irq %i\n", irq);
426 }
427
428 /*
429 * We can remove mdelay() and then send spuriuous interrupts to
430 * new cpu targets for all the irqs that were handled previously by
431 * this cpu. While it works, I have seen spurious interrupt messages
432 * (nothing wrong but still...).
433 *
434 * So for now, retain mdelay(1) and check the IRR and then send those
435 * interrupts to new targets as this cpu is already offlined...
436 */
437 mdelay(1);
438
439 for (vector = FIRST_EXTERNAL_VECTOR; vector < NR_VECTORS; vector++) {
440 unsigned int irr;
441
442 if (__this_cpu_read(vector_irq[vector]) <= VECTOR_UNDEFINED)
443 continue;
444
445 irr = apic_read(APIC_IRR + (vector / 32 * 0x10));
446 if (irr & (1 << (vector % 32))) {
447 irq = __this_cpu_read(vector_irq[vector]);
448
449 desc = irq_to_desc(irq);
450 data = irq_desc_get_irq_data(desc);
451 chip = irq_data_get_irq_chip(data);
452 raw_spin_lock(&desc->lock);
453 if (chip->irq_retrigger) {
454 chip->irq_retrigger(data);
455 __this_cpu_write(vector_irq[vector], VECTOR_RETRIGGERED);
456 }
457 raw_spin_unlock(&desc->lock);
458 }
459 if (__this_cpu_read(vector_irq[vector]) != VECTOR_RETRIGGERED)
460 __this_cpu_write(vector_irq[vector], VECTOR_UNDEFINED);
461 }
462}
463#endif