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1/* Performance event support for sparc64.
2 *
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 *
5 * This code is based almost entirely upon the x86 perf event
6 * code, which is:
7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
13 */
14
15#include <linux/perf_event.h>
16#include <linux/kprobes.h>
17#include <linux/ftrace.h>
18#include <linux/kernel.h>
19#include <linux/kdebug.h>
20#include <linux/mutex.h>
21
22#include <asm/stacktrace.h>
23#include <asm/cpudata.h>
24#include <asm/uaccess.h>
25#include <linux/atomic.h>
26#include <asm/nmi.h>
27#include <asm/pcr.h>
28
29#include "kernel.h"
30#include "kstack.h"
31
32/* Sparc64 chips have two performance counters, 32-bits each, with
33 * overflow interrupts generated on transition from 0xffffffff to 0.
34 * The counters are accessed in one go using a 64-bit register.
35 *
36 * Both counters are controlled using a single control register. The
37 * only way to stop all sampling is to clear all of the context (user,
38 * supervisor, hypervisor) sampling enable bits. But these bits apply
39 * to both counters, thus the two counters can't be enabled/disabled
40 * individually.
41 *
42 * The control register has two event fields, one for each of the two
43 * counters. It's thus nearly impossible to have one counter going
44 * while keeping the other one stopped. Therefore it is possible to
45 * get overflow interrupts for counters not currently "in use" and
46 * that condition must be checked in the overflow interrupt handler.
47 *
48 * So we use a hack, in that we program inactive counters with the
49 * "sw_count0" and "sw_count1" events. These count how many times
50 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
51 * unusual way to encode a NOP and therefore will not trigger in
52 * normal code.
53 */
54
55#define MAX_HWEVENTS 2
56#define MAX_PERIOD ((1UL << 32) - 1)
57
58#define PIC_UPPER_INDEX 0
59#define PIC_LOWER_INDEX 1
60#define PIC_NO_INDEX -1
61
62struct cpu_hw_events {
63 /* Number of events currently scheduled onto this cpu.
64 * This tells how many entries in the arrays below
65 * are valid.
66 */
67 int n_events;
68
69 /* Number of new events added since the last hw_perf_disable().
70 * This works because the perf event layer always adds new
71 * events inside of a perf_{disable,enable}() sequence.
72 */
73 int n_added;
74
75 /* Array of events current scheduled on this cpu. */
76 struct perf_event *event[MAX_HWEVENTS];
77
78 /* Array of encoded longs, specifying the %pcr register
79 * encoding and the mask of PIC counters this even can
80 * be scheduled on. See perf_event_encode() et al.
81 */
82 unsigned long events[MAX_HWEVENTS];
83
84 /* The current counter index assigned to an event. When the
85 * event hasn't been programmed into the cpu yet, this will
86 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
87 * we ought to schedule the event.
88 */
89 int current_idx[MAX_HWEVENTS];
90
91 /* Software copy of %pcr register on this cpu. */
92 u64 pcr;
93
94 /* Enabled/disable state. */
95 int enabled;
96
97 unsigned int group_flag;
98};
99DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
100
101/* An event map describes the characteristics of a performance
102 * counter event. In particular it gives the encoding as well as
103 * a mask telling which counters the event can be measured on.
104 */
105struct perf_event_map {
106 u16 encoding;
107 u8 pic_mask;
108#define PIC_NONE 0x00
109#define PIC_UPPER 0x01
110#define PIC_LOWER 0x02
111};
112
113/* Encode a perf_event_map entry into a long. */
114static unsigned long perf_event_encode(const struct perf_event_map *pmap)
115{
116 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
117}
118
119static u8 perf_event_get_msk(unsigned long val)
120{
121 return val & 0xff;
122}
123
124static u64 perf_event_get_enc(unsigned long val)
125{
126 return val >> 16;
127}
128
129#define C(x) PERF_COUNT_HW_CACHE_##x
130
131#define CACHE_OP_UNSUPPORTED 0xfffe
132#define CACHE_OP_NONSENSE 0xffff
133
134typedef struct perf_event_map cache_map_t
135 [PERF_COUNT_HW_CACHE_MAX]
136 [PERF_COUNT_HW_CACHE_OP_MAX]
137 [PERF_COUNT_HW_CACHE_RESULT_MAX];
138
139struct sparc_pmu {
140 const struct perf_event_map *(*event_map)(int);
141 const cache_map_t *cache_map;
142 int max_events;
143 int upper_shift;
144 int lower_shift;
145 int event_mask;
146 int hv_bit;
147 int irq_bit;
148 int upper_nop;
149 int lower_nop;
150};
151
152static const struct perf_event_map ultra3_perfmon_event_map[] = {
153 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
154 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
155 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
156 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
157};
158
159static const struct perf_event_map *ultra3_event_map(int event_id)
160{
161 return &ultra3_perfmon_event_map[event_id];
162}
163
164static const cache_map_t ultra3_cache_map = {
165[C(L1D)] = {
166 [C(OP_READ)] = {
167 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
168 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
169 },
170 [C(OP_WRITE)] = {
171 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
172 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
173 },
174 [C(OP_PREFETCH)] = {
175 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
176 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
177 },
178},
179[C(L1I)] = {
180 [C(OP_READ)] = {
181 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
182 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
183 },
184 [ C(OP_WRITE) ] = {
185 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
186 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
187 },
188 [ C(OP_PREFETCH) ] = {
189 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
190 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
191 },
192},
193[C(LL)] = {
194 [C(OP_READ)] = {
195 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
196 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
197 },
198 [C(OP_WRITE)] = {
199 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
200 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
201 },
202 [C(OP_PREFETCH)] = {
203 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
204 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
205 },
206},
207[C(DTLB)] = {
208 [C(OP_READ)] = {
209 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
210 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
211 },
212 [ C(OP_WRITE) ] = {
213 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
214 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
215 },
216 [ C(OP_PREFETCH) ] = {
217 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
218 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
219 },
220},
221[C(ITLB)] = {
222 [C(OP_READ)] = {
223 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
224 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
225 },
226 [ C(OP_WRITE) ] = {
227 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
228 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
229 },
230 [ C(OP_PREFETCH) ] = {
231 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
232 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
233 },
234},
235[C(BPU)] = {
236 [C(OP_READ)] = {
237 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
238 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
239 },
240 [ C(OP_WRITE) ] = {
241 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
242 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
243 },
244 [ C(OP_PREFETCH) ] = {
245 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
246 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
247 },
248},
249[C(NODE)] = {
250 [C(OP_READ)] = {
251 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
252 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
253 },
254 [ C(OP_WRITE) ] = {
255 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
256 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
257 },
258 [ C(OP_PREFETCH) ] = {
259 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
260 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
261 },
262},
263};
264
265static const struct sparc_pmu ultra3_pmu = {
266 .event_map = ultra3_event_map,
267 .cache_map = &ultra3_cache_map,
268 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
269 .upper_shift = 11,
270 .lower_shift = 4,
271 .event_mask = 0x3f,
272 .upper_nop = 0x1c,
273 .lower_nop = 0x14,
274};
275
276/* Niagara1 is very limited. The upper PIC is hard-locked to count
277 * only instructions, so it is free running which creates all kinds of
278 * problems. Some hardware designs make one wonder if the creator
279 * even looked at how this stuff gets used by software.
280 */
281static const struct perf_event_map niagara1_perfmon_event_map[] = {
282 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
283 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
284 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
285 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
286};
287
288static const struct perf_event_map *niagara1_event_map(int event_id)
289{
290 return &niagara1_perfmon_event_map[event_id];
291}
292
293static const cache_map_t niagara1_cache_map = {
294[C(L1D)] = {
295 [C(OP_READ)] = {
296 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
297 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
298 },
299 [C(OP_WRITE)] = {
300 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
301 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
302 },
303 [C(OP_PREFETCH)] = {
304 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
305 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
306 },
307},
308[C(L1I)] = {
309 [C(OP_READ)] = {
310 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
311 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
312 },
313 [ C(OP_WRITE) ] = {
314 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
315 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
316 },
317 [ C(OP_PREFETCH) ] = {
318 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
319 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
320 },
321},
322[C(LL)] = {
323 [C(OP_READ)] = {
324 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
325 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
326 },
327 [C(OP_WRITE)] = {
328 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
329 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
330 },
331 [C(OP_PREFETCH)] = {
332 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
333 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
334 },
335},
336[C(DTLB)] = {
337 [C(OP_READ)] = {
338 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
339 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
340 },
341 [ C(OP_WRITE) ] = {
342 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
343 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
344 },
345 [ C(OP_PREFETCH) ] = {
346 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
347 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
348 },
349},
350[C(ITLB)] = {
351 [C(OP_READ)] = {
352 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
353 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
354 },
355 [ C(OP_WRITE) ] = {
356 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
357 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
358 },
359 [ C(OP_PREFETCH) ] = {
360 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
361 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
362 },
363},
364[C(BPU)] = {
365 [C(OP_READ)] = {
366 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
367 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
368 },
369 [ C(OP_WRITE) ] = {
370 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
371 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
372 },
373 [ C(OP_PREFETCH) ] = {
374 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
375 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
376 },
377},
378[C(NODE)] = {
379 [C(OP_READ)] = {
380 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
381 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
382 },
383 [ C(OP_WRITE) ] = {
384 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
385 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
386 },
387 [ C(OP_PREFETCH) ] = {
388 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
389 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
390 },
391},
392};
393
394static const struct sparc_pmu niagara1_pmu = {
395 .event_map = niagara1_event_map,
396 .cache_map = &niagara1_cache_map,
397 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
398 .upper_shift = 0,
399 .lower_shift = 4,
400 .event_mask = 0x7,
401 .upper_nop = 0x0,
402 .lower_nop = 0x0,
403};
404
405static const struct perf_event_map niagara2_perfmon_event_map[] = {
406 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
407 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
408 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
409 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
410 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
411 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
412};
413
414static const struct perf_event_map *niagara2_event_map(int event_id)
415{
416 return &niagara2_perfmon_event_map[event_id];
417}
418
419static const cache_map_t niagara2_cache_map = {
420[C(L1D)] = {
421 [C(OP_READ)] = {
422 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
423 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
424 },
425 [C(OP_WRITE)] = {
426 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
427 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
428 },
429 [C(OP_PREFETCH)] = {
430 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
431 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
432 },
433},
434[C(L1I)] = {
435 [C(OP_READ)] = {
436 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
437 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
438 },
439 [ C(OP_WRITE) ] = {
440 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
441 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
442 },
443 [ C(OP_PREFETCH) ] = {
444 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
445 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
446 },
447},
448[C(LL)] = {
449 [C(OP_READ)] = {
450 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
451 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
452 },
453 [C(OP_WRITE)] = {
454 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
455 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
456 },
457 [C(OP_PREFETCH)] = {
458 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
459 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
460 },
461},
462[C(DTLB)] = {
463 [C(OP_READ)] = {
464 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
465 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
466 },
467 [ C(OP_WRITE) ] = {
468 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
469 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
470 },
471 [ C(OP_PREFETCH) ] = {
472 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
473 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
474 },
475},
476[C(ITLB)] = {
477 [C(OP_READ)] = {
478 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
479 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
480 },
481 [ C(OP_WRITE) ] = {
482 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
483 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
484 },
485 [ C(OP_PREFETCH) ] = {
486 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
487 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
488 },
489},
490[C(BPU)] = {
491 [C(OP_READ)] = {
492 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
493 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
494 },
495 [ C(OP_WRITE) ] = {
496 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
497 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
498 },
499 [ C(OP_PREFETCH) ] = {
500 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
501 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
502 },
503},
504[C(NODE)] = {
505 [C(OP_READ)] = {
506 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
507 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
508 },
509 [ C(OP_WRITE) ] = {
510 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
511 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
512 },
513 [ C(OP_PREFETCH) ] = {
514 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
515 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
516 },
517},
518};
519
520static const struct sparc_pmu niagara2_pmu = {
521 .event_map = niagara2_event_map,
522 .cache_map = &niagara2_cache_map,
523 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
524 .upper_shift = 19,
525 .lower_shift = 6,
526 .event_mask = 0xfff,
527 .hv_bit = 0x8,
528 .irq_bit = 0x30,
529 .upper_nop = 0x220,
530 .lower_nop = 0x220,
531};
532
533static const struct sparc_pmu *sparc_pmu __read_mostly;
534
535static u64 event_encoding(u64 event_id, int idx)
536{
537 if (idx == PIC_UPPER_INDEX)
538 event_id <<= sparc_pmu->upper_shift;
539 else
540 event_id <<= sparc_pmu->lower_shift;
541 return event_id;
542}
543
544static u64 mask_for_index(int idx)
545{
546 return event_encoding(sparc_pmu->event_mask, idx);
547}
548
549static u64 nop_for_index(int idx)
550{
551 return event_encoding(idx == PIC_UPPER_INDEX ?
552 sparc_pmu->upper_nop :
553 sparc_pmu->lower_nop, idx);
554}
555
556static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
557{
558 u64 val, mask = mask_for_index(idx);
559
560 val = cpuc->pcr;
561 val &= ~mask;
562 val |= hwc->config;
563 cpuc->pcr = val;
564
565 pcr_ops->write(cpuc->pcr);
566}
567
568static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
569{
570 u64 mask = mask_for_index(idx);
571 u64 nop = nop_for_index(idx);
572 u64 val;
573
574 val = cpuc->pcr;
575 val &= ~mask;
576 val |= nop;
577 cpuc->pcr = val;
578
579 pcr_ops->write(cpuc->pcr);
580}
581
582static u32 read_pmc(int idx)
583{
584 u64 val;
585
586 read_pic(val);
587 if (idx == PIC_UPPER_INDEX)
588 val >>= 32;
589
590 return val & 0xffffffff;
591}
592
593static void write_pmc(int idx, u64 val)
594{
595 u64 shift, mask, pic;
596
597 shift = 0;
598 if (idx == PIC_UPPER_INDEX)
599 shift = 32;
600
601 mask = ((u64) 0xffffffff) << shift;
602 val <<= shift;
603
604 read_pic(pic);
605 pic &= ~mask;
606 pic |= val;
607 write_pic(pic);
608}
609
610static u64 sparc_perf_event_update(struct perf_event *event,
611 struct hw_perf_event *hwc, int idx)
612{
613 int shift = 64 - 32;
614 u64 prev_raw_count, new_raw_count;
615 s64 delta;
616
617again:
618 prev_raw_count = local64_read(&hwc->prev_count);
619 new_raw_count = read_pmc(idx);
620
621 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
622 new_raw_count) != prev_raw_count)
623 goto again;
624
625 delta = (new_raw_count << shift) - (prev_raw_count << shift);
626 delta >>= shift;
627
628 local64_add(delta, &event->count);
629 local64_sub(delta, &hwc->period_left);
630
631 return new_raw_count;
632}
633
634static int sparc_perf_event_set_period(struct perf_event *event,
635 struct hw_perf_event *hwc, int idx)
636{
637 s64 left = local64_read(&hwc->period_left);
638 s64 period = hwc->sample_period;
639 int ret = 0;
640
641 if (unlikely(left <= -period)) {
642 left = period;
643 local64_set(&hwc->period_left, left);
644 hwc->last_period = period;
645 ret = 1;
646 }
647
648 if (unlikely(left <= 0)) {
649 left += period;
650 local64_set(&hwc->period_left, left);
651 hwc->last_period = period;
652 ret = 1;
653 }
654 if (left > MAX_PERIOD)
655 left = MAX_PERIOD;
656
657 local64_set(&hwc->prev_count, (u64)-left);
658
659 write_pmc(idx, (u64)(-left) & 0xffffffff);
660
661 perf_event_update_userpage(event);
662
663 return ret;
664}
665
666/* If performance event entries have been added, move existing
667 * events around (if necessary) and then assign new entries to
668 * counters.
669 */
670static u64 maybe_change_configuration(struct cpu_hw_events *cpuc, u64 pcr)
671{
672 int i;
673
674 if (!cpuc->n_added)
675 goto out;
676
677 /* Read in the counters which are moving. */
678 for (i = 0; i < cpuc->n_events; i++) {
679 struct perf_event *cp = cpuc->event[i];
680
681 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
682 cpuc->current_idx[i] != cp->hw.idx) {
683 sparc_perf_event_update(cp, &cp->hw,
684 cpuc->current_idx[i]);
685 cpuc->current_idx[i] = PIC_NO_INDEX;
686 }
687 }
688
689 /* Assign to counters all unassigned events. */
690 for (i = 0; i < cpuc->n_events; i++) {
691 struct perf_event *cp = cpuc->event[i];
692 struct hw_perf_event *hwc = &cp->hw;
693 int idx = hwc->idx;
694 u64 enc;
695
696 if (cpuc->current_idx[i] != PIC_NO_INDEX)
697 continue;
698
699 sparc_perf_event_set_period(cp, hwc, idx);
700 cpuc->current_idx[i] = idx;
701
702 enc = perf_event_get_enc(cpuc->events[i]);
703 pcr &= ~mask_for_index(idx);
704 if (hwc->state & PERF_HES_STOPPED)
705 pcr |= nop_for_index(idx);
706 else
707 pcr |= event_encoding(enc, idx);
708 }
709out:
710 return pcr;
711}
712
713static void sparc_pmu_enable(struct pmu *pmu)
714{
715 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
716 u64 pcr;
717
718 if (cpuc->enabled)
719 return;
720
721 cpuc->enabled = 1;
722 barrier();
723
724 pcr = cpuc->pcr;
725 if (!cpuc->n_events) {
726 pcr = 0;
727 } else {
728 pcr = maybe_change_configuration(cpuc, pcr);
729
730 /* We require that all of the events have the same
731 * configuration, so just fetch the settings from the
732 * first entry.
733 */
734 cpuc->pcr = pcr | cpuc->event[0]->hw.config_base;
735 }
736
737 pcr_ops->write(cpuc->pcr);
738}
739
740static void sparc_pmu_disable(struct pmu *pmu)
741{
742 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
743 u64 val;
744
745 if (!cpuc->enabled)
746 return;
747
748 cpuc->enabled = 0;
749 cpuc->n_added = 0;
750
751 val = cpuc->pcr;
752 val &= ~(PCR_UTRACE | PCR_STRACE |
753 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
754 cpuc->pcr = val;
755
756 pcr_ops->write(cpuc->pcr);
757}
758
759static int active_event_index(struct cpu_hw_events *cpuc,
760 struct perf_event *event)
761{
762 int i;
763
764 for (i = 0; i < cpuc->n_events; i++) {
765 if (cpuc->event[i] == event)
766 break;
767 }
768 BUG_ON(i == cpuc->n_events);
769 return cpuc->current_idx[i];
770}
771
772static void sparc_pmu_start(struct perf_event *event, int flags)
773{
774 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
775 int idx = active_event_index(cpuc, event);
776
777 if (flags & PERF_EF_RELOAD) {
778 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
779 sparc_perf_event_set_period(event, &event->hw, idx);
780 }
781
782 event->hw.state = 0;
783
784 sparc_pmu_enable_event(cpuc, &event->hw, idx);
785}
786
787static void sparc_pmu_stop(struct perf_event *event, int flags)
788{
789 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
790 int idx = active_event_index(cpuc, event);
791
792 if (!(event->hw.state & PERF_HES_STOPPED)) {
793 sparc_pmu_disable_event(cpuc, &event->hw, idx);
794 event->hw.state |= PERF_HES_STOPPED;
795 }
796
797 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
798 sparc_perf_event_update(event, &event->hw, idx);
799 event->hw.state |= PERF_HES_UPTODATE;
800 }
801}
802
803static void sparc_pmu_del(struct perf_event *event, int _flags)
804{
805 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
806 unsigned long flags;
807 int i;
808
809 local_irq_save(flags);
810 perf_pmu_disable(event->pmu);
811
812 for (i = 0; i < cpuc->n_events; i++) {
813 if (event == cpuc->event[i]) {
814 /* Absorb the final count and turn off the
815 * event.
816 */
817 sparc_pmu_stop(event, PERF_EF_UPDATE);
818
819 /* Shift remaining entries down into
820 * the existing slot.
821 */
822 while (++i < cpuc->n_events) {
823 cpuc->event[i - 1] = cpuc->event[i];
824 cpuc->events[i - 1] = cpuc->events[i];
825 cpuc->current_idx[i - 1] =
826 cpuc->current_idx[i];
827 }
828
829 perf_event_update_userpage(event);
830
831 cpuc->n_events--;
832 break;
833 }
834 }
835
836 perf_pmu_enable(event->pmu);
837 local_irq_restore(flags);
838}
839
840static void sparc_pmu_read(struct perf_event *event)
841{
842 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
843 int idx = active_event_index(cpuc, event);
844 struct hw_perf_event *hwc = &event->hw;
845
846 sparc_perf_event_update(event, hwc, idx);
847}
848
849static atomic_t active_events = ATOMIC_INIT(0);
850static DEFINE_MUTEX(pmc_grab_mutex);
851
852static void perf_stop_nmi_watchdog(void *unused)
853{
854 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
855
856 stop_nmi_watchdog(NULL);
857 cpuc->pcr = pcr_ops->read();
858}
859
860void perf_event_grab_pmc(void)
861{
862 if (atomic_inc_not_zero(&active_events))
863 return;
864
865 mutex_lock(&pmc_grab_mutex);
866 if (atomic_read(&active_events) == 0) {
867 if (atomic_read(&nmi_active) > 0) {
868 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
869 BUG_ON(atomic_read(&nmi_active) != 0);
870 }
871 atomic_inc(&active_events);
872 }
873 mutex_unlock(&pmc_grab_mutex);
874}
875
876void perf_event_release_pmc(void)
877{
878 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
879 if (atomic_read(&nmi_active) == 0)
880 on_each_cpu(start_nmi_watchdog, NULL, 1);
881 mutex_unlock(&pmc_grab_mutex);
882 }
883}
884
885static const struct perf_event_map *sparc_map_cache_event(u64 config)
886{
887 unsigned int cache_type, cache_op, cache_result;
888 const struct perf_event_map *pmap;
889
890 if (!sparc_pmu->cache_map)
891 return ERR_PTR(-ENOENT);
892
893 cache_type = (config >> 0) & 0xff;
894 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
895 return ERR_PTR(-EINVAL);
896
897 cache_op = (config >> 8) & 0xff;
898 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
899 return ERR_PTR(-EINVAL);
900
901 cache_result = (config >> 16) & 0xff;
902 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
903 return ERR_PTR(-EINVAL);
904
905 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
906
907 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
908 return ERR_PTR(-ENOENT);
909
910 if (pmap->encoding == CACHE_OP_NONSENSE)
911 return ERR_PTR(-EINVAL);
912
913 return pmap;
914}
915
916static void hw_perf_event_destroy(struct perf_event *event)
917{
918 perf_event_release_pmc();
919}
920
921/* Make sure all events can be scheduled into the hardware at
922 * the same time. This is simplified by the fact that we only
923 * need to support 2 simultaneous HW events.
924 *
925 * As a side effect, the evts[]->hw.idx values will be assigned
926 * on success. These are pending indexes. When the events are
927 * actually programmed into the chip, these values will propagate
928 * to the per-cpu cpuc->current_idx[] slots, see the code in
929 * maybe_change_configuration() for details.
930 */
931static int sparc_check_constraints(struct perf_event **evts,
932 unsigned long *events, int n_ev)
933{
934 u8 msk0 = 0, msk1 = 0;
935 int idx0 = 0;
936
937 /* This case is possible when we are invoked from
938 * hw_perf_group_sched_in().
939 */
940 if (!n_ev)
941 return 0;
942
943 if (n_ev > MAX_HWEVENTS)
944 return -1;
945
946 msk0 = perf_event_get_msk(events[0]);
947 if (n_ev == 1) {
948 if (msk0 & PIC_LOWER)
949 idx0 = 1;
950 goto success;
951 }
952 BUG_ON(n_ev != 2);
953 msk1 = perf_event_get_msk(events[1]);
954
955 /* If both events can go on any counter, OK. */
956 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
957 msk1 == (PIC_UPPER | PIC_LOWER))
958 goto success;
959
960 /* If one event is limited to a specific counter,
961 * and the other can go on both, OK.
962 */
963 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
964 msk1 == (PIC_UPPER | PIC_LOWER)) {
965 if (msk0 & PIC_LOWER)
966 idx0 = 1;
967 goto success;
968 }
969
970 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
971 msk0 == (PIC_UPPER | PIC_LOWER)) {
972 if (msk1 & PIC_UPPER)
973 idx0 = 1;
974 goto success;
975 }
976
977 /* If the events are fixed to different counters, OK. */
978 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
979 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
980 if (msk0 & PIC_LOWER)
981 idx0 = 1;
982 goto success;
983 }
984
985 /* Otherwise, there is a conflict. */
986 return -1;
987
988success:
989 evts[0]->hw.idx = idx0;
990 if (n_ev == 2)
991 evts[1]->hw.idx = idx0 ^ 1;
992 return 0;
993}
994
995static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
996{
997 int eu = 0, ek = 0, eh = 0;
998 struct perf_event *event;
999 int i, n, first;
1000
1001 n = n_prev + n_new;
1002 if (n <= 1)
1003 return 0;
1004
1005 first = 1;
1006 for (i = 0; i < n; i++) {
1007 event = evts[i];
1008 if (first) {
1009 eu = event->attr.exclude_user;
1010 ek = event->attr.exclude_kernel;
1011 eh = event->attr.exclude_hv;
1012 first = 0;
1013 } else if (event->attr.exclude_user != eu ||
1014 event->attr.exclude_kernel != ek ||
1015 event->attr.exclude_hv != eh) {
1016 return -EAGAIN;
1017 }
1018 }
1019
1020 return 0;
1021}
1022
1023static int collect_events(struct perf_event *group, int max_count,
1024 struct perf_event *evts[], unsigned long *events,
1025 int *current_idx)
1026{
1027 struct perf_event *event;
1028 int n = 0;
1029
1030 if (!is_software_event(group)) {
1031 if (n >= max_count)
1032 return -1;
1033 evts[n] = group;
1034 events[n] = group->hw.event_base;
1035 current_idx[n++] = PIC_NO_INDEX;
1036 }
1037 list_for_each_entry(event, &group->sibling_list, group_entry) {
1038 if (!is_software_event(event) &&
1039 event->state != PERF_EVENT_STATE_OFF) {
1040 if (n >= max_count)
1041 return -1;
1042 evts[n] = event;
1043 events[n] = event->hw.event_base;
1044 current_idx[n++] = PIC_NO_INDEX;
1045 }
1046 }
1047 return n;
1048}
1049
1050static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1051{
1052 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1053 int n0, ret = -EAGAIN;
1054 unsigned long flags;
1055
1056 local_irq_save(flags);
1057 perf_pmu_disable(event->pmu);
1058
1059 n0 = cpuc->n_events;
1060 if (n0 >= MAX_HWEVENTS)
1061 goto out;
1062
1063 cpuc->event[n0] = event;
1064 cpuc->events[n0] = event->hw.event_base;
1065 cpuc->current_idx[n0] = PIC_NO_INDEX;
1066
1067 event->hw.state = PERF_HES_UPTODATE;
1068 if (!(ef_flags & PERF_EF_START))
1069 event->hw.state |= PERF_HES_STOPPED;
1070
1071 /*
1072 * If group events scheduling transaction was started,
1073 * skip the schedulability test here, it will be performed
1074 * at commit time(->commit_txn) as a whole
1075 */
1076 if (cpuc->group_flag & PERF_EVENT_TXN)
1077 goto nocheck;
1078
1079 if (check_excludes(cpuc->event, n0, 1))
1080 goto out;
1081 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1082 goto out;
1083
1084nocheck:
1085 cpuc->n_events++;
1086 cpuc->n_added++;
1087
1088 ret = 0;
1089out:
1090 perf_pmu_enable(event->pmu);
1091 local_irq_restore(flags);
1092 return ret;
1093}
1094
1095static int sparc_pmu_event_init(struct perf_event *event)
1096{
1097 struct perf_event_attr *attr = &event->attr;
1098 struct perf_event *evts[MAX_HWEVENTS];
1099 struct hw_perf_event *hwc = &event->hw;
1100 unsigned long events[MAX_HWEVENTS];
1101 int current_idx_dmy[MAX_HWEVENTS];
1102 const struct perf_event_map *pmap;
1103 int n;
1104
1105 if (atomic_read(&nmi_active) < 0)
1106 return -ENODEV;
1107
1108 switch (attr->type) {
1109 case PERF_TYPE_HARDWARE:
1110 if (attr->config >= sparc_pmu->max_events)
1111 return -EINVAL;
1112 pmap = sparc_pmu->event_map(attr->config);
1113 break;
1114
1115 case PERF_TYPE_HW_CACHE:
1116 pmap = sparc_map_cache_event(attr->config);
1117 if (IS_ERR(pmap))
1118 return PTR_ERR(pmap);
1119 break;
1120
1121 case PERF_TYPE_RAW:
1122 pmap = NULL;
1123 break;
1124
1125 default:
1126 return -ENOENT;
1127
1128 }
1129
1130 if (pmap) {
1131 hwc->event_base = perf_event_encode(pmap);
1132 } else {
1133 /*
1134 * User gives us "(encoding << 16) | pic_mask" for
1135 * PERF_TYPE_RAW events.
1136 */
1137 hwc->event_base = attr->config;
1138 }
1139
1140 /* We save the enable bits in the config_base. */
1141 hwc->config_base = sparc_pmu->irq_bit;
1142 if (!attr->exclude_user)
1143 hwc->config_base |= PCR_UTRACE;
1144 if (!attr->exclude_kernel)
1145 hwc->config_base |= PCR_STRACE;
1146 if (!attr->exclude_hv)
1147 hwc->config_base |= sparc_pmu->hv_bit;
1148
1149 n = 0;
1150 if (event->group_leader != event) {
1151 n = collect_events(event->group_leader,
1152 MAX_HWEVENTS - 1,
1153 evts, events, current_idx_dmy);
1154 if (n < 0)
1155 return -EINVAL;
1156 }
1157 events[n] = hwc->event_base;
1158 evts[n] = event;
1159
1160 if (check_excludes(evts, n, 1))
1161 return -EINVAL;
1162
1163 if (sparc_check_constraints(evts, events, n + 1))
1164 return -EINVAL;
1165
1166 hwc->idx = PIC_NO_INDEX;
1167
1168 /* Try to do all error checking before this point, as unwinding
1169 * state after grabbing the PMC is difficult.
1170 */
1171 perf_event_grab_pmc();
1172 event->destroy = hw_perf_event_destroy;
1173
1174 if (!hwc->sample_period) {
1175 hwc->sample_period = MAX_PERIOD;
1176 hwc->last_period = hwc->sample_period;
1177 local64_set(&hwc->period_left, hwc->sample_period);
1178 }
1179
1180 return 0;
1181}
1182
1183/*
1184 * Start group events scheduling transaction
1185 * Set the flag to make pmu::enable() not perform the
1186 * schedulability test, it will be performed at commit time
1187 */
1188static void sparc_pmu_start_txn(struct pmu *pmu)
1189{
1190 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1191
1192 perf_pmu_disable(pmu);
1193 cpuhw->group_flag |= PERF_EVENT_TXN;
1194}
1195
1196/*
1197 * Stop group events scheduling transaction
1198 * Clear the flag and pmu::enable() will perform the
1199 * schedulability test.
1200 */
1201static void sparc_pmu_cancel_txn(struct pmu *pmu)
1202{
1203 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1204
1205 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1206 perf_pmu_enable(pmu);
1207}
1208
1209/*
1210 * Commit group events scheduling transaction
1211 * Perform the group schedulability test as a whole
1212 * Return 0 if success
1213 */
1214static int sparc_pmu_commit_txn(struct pmu *pmu)
1215{
1216 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1217 int n;
1218
1219 if (!sparc_pmu)
1220 return -EINVAL;
1221
1222 cpuc = &__get_cpu_var(cpu_hw_events);
1223 n = cpuc->n_events;
1224 if (check_excludes(cpuc->event, 0, n))
1225 return -EINVAL;
1226 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1227 return -EAGAIN;
1228
1229 cpuc->group_flag &= ~PERF_EVENT_TXN;
1230 perf_pmu_enable(pmu);
1231 return 0;
1232}
1233
1234static struct pmu pmu = {
1235 .pmu_enable = sparc_pmu_enable,
1236 .pmu_disable = sparc_pmu_disable,
1237 .event_init = sparc_pmu_event_init,
1238 .add = sparc_pmu_add,
1239 .del = sparc_pmu_del,
1240 .start = sparc_pmu_start,
1241 .stop = sparc_pmu_stop,
1242 .read = sparc_pmu_read,
1243 .start_txn = sparc_pmu_start_txn,
1244 .cancel_txn = sparc_pmu_cancel_txn,
1245 .commit_txn = sparc_pmu_commit_txn,
1246};
1247
1248void perf_event_print_debug(void)
1249{
1250 unsigned long flags;
1251 u64 pcr, pic;
1252 int cpu;
1253
1254 if (!sparc_pmu)
1255 return;
1256
1257 local_irq_save(flags);
1258
1259 cpu = smp_processor_id();
1260
1261 pcr = pcr_ops->read();
1262 read_pic(pic);
1263
1264 pr_info("\n");
1265 pr_info("CPU#%d: PCR[%016llx] PIC[%016llx]\n",
1266 cpu, pcr, pic);
1267
1268 local_irq_restore(flags);
1269}
1270
1271static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1272 unsigned long cmd, void *__args)
1273{
1274 struct die_args *args = __args;
1275 struct perf_sample_data data;
1276 struct cpu_hw_events *cpuc;
1277 struct pt_regs *regs;
1278 int i;
1279
1280 if (!atomic_read(&active_events))
1281 return NOTIFY_DONE;
1282
1283 switch (cmd) {
1284 case DIE_NMI:
1285 break;
1286
1287 default:
1288 return NOTIFY_DONE;
1289 }
1290
1291 regs = args->regs;
1292
1293 perf_sample_data_init(&data, 0);
1294
1295 cpuc = &__get_cpu_var(cpu_hw_events);
1296
1297 /* If the PMU has the TOE IRQ enable bits, we need to do a
1298 * dummy write to the %pcr to clear the overflow bits and thus
1299 * the interrupt.
1300 *
1301 * Do this before we peek at the counters to determine
1302 * overflow so we don't lose any events.
1303 */
1304 if (sparc_pmu->irq_bit)
1305 pcr_ops->write(cpuc->pcr);
1306
1307 for (i = 0; i < cpuc->n_events; i++) {
1308 struct perf_event *event = cpuc->event[i];
1309 int idx = cpuc->current_idx[i];
1310 struct hw_perf_event *hwc;
1311 u64 val;
1312
1313 hwc = &event->hw;
1314 val = sparc_perf_event_update(event, hwc, idx);
1315 if (val & (1ULL << 31))
1316 continue;
1317
1318 data.period = event->hw.last_period;
1319 if (!sparc_perf_event_set_period(event, hwc, idx))
1320 continue;
1321
1322 if (perf_event_overflow(event, &data, regs))
1323 sparc_pmu_stop(event, 0);
1324 }
1325
1326 return NOTIFY_STOP;
1327}
1328
1329static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1330 .notifier_call = perf_event_nmi_handler,
1331};
1332
1333static bool __init supported_pmu(void)
1334{
1335 if (!strcmp(sparc_pmu_type, "ultra3") ||
1336 !strcmp(sparc_pmu_type, "ultra3+") ||
1337 !strcmp(sparc_pmu_type, "ultra3i") ||
1338 !strcmp(sparc_pmu_type, "ultra4+")) {
1339 sparc_pmu = &ultra3_pmu;
1340 return true;
1341 }
1342 if (!strcmp(sparc_pmu_type, "niagara")) {
1343 sparc_pmu = &niagara1_pmu;
1344 return true;
1345 }
1346 if (!strcmp(sparc_pmu_type, "niagara2") ||
1347 !strcmp(sparc_pmu_type, "niagara3")) {
1348 sparc_pmu = &niagara2_pmu;
1349 return true;
1350 }
1351 return false;
1352}
1353
1354int __init init_hw_perf_events(void)
1355{
1356 pr_info("Performance events: ");
1357
1358 if (!supported_pmu()) {
1359 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1360 return 0;
1361 }
1362
1363 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1364
1365 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1366 register_die_notifier(&perf_event_nmi_notifier);
1367
1368 return 0;
1369}
1370early_initcall(init_hw_perf_events);
1371
1372void perf_callchain_kernel(struct perf_callchain_entry *entry,
1373 struct pt_regs *regs)
1374{
1375 unsigned long ksp, fp;
1376#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1377 int graph = 0;
1378#endif
1379
1380 stack_trace_flush();
1381
1382 perf_callchain_store(entry, regs->tpc);
1383
1384 ksp = regs->u_regs[UREG_I6];
1385 fp = ksp + STACK_BIAS;
1386 do {
1387 struct sparc_stackf *sf;
1388 struct pt_regs *regs;
1389 unsigned long pc;
1390
1391 if (!kstack_valid(current_thread_info(), fp))
1392 break;
1393
1394 sf = (struct sparc_stackf *) fp;
1395 regs = (struct pt_regs *) (sf + 1);
1396
1397 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1398 if (user_mode(regs))
1399 break;
1400 pc = regs->tpc;
1401 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1402 } else {
1403 pc = sf->callers_pc;
1404 fp = (unsigned long)sf->fp + STACK_BIAS;
1405 }
1406 perf_callchain_store(entry, pc);
1407#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1408 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1409 int index = current->curr_ret_stack;
1410 if (current->ret_stack && index >= graph) {
1411 pc = current->ret_stack[index - graph].ret;
1412 perf_callchain_store(entry, pc);
1413 graph++;
1414 }
1415 }
1416#endif
1417 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1418}
1419
1420static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1421 struct pt_regs *regs)
1422{
1423 unsigned long ufp;
1424
1425 perf_callchain_store(entry, regs->tpc);
1426
1427 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1428 do {
1429 struct sparc_stackf *usf, sf;
1430 unsigned long pc;
1431
1432 usf = (struct sparc_stackf *) ufp;
1433 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1434 break;
1435
1436 pc = sf.callers_pc;
1437 ufp = (unsigned long)sf.fp + STACK_BIAS;
1438 perf_callchain_store(entry, pc);
1439 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1440}
1441
1442static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1443 struct pt_regs *regs)
1444{
1445 unsigned long ufp;
1446
1447 perf_callchain_store(entry, regs->tpc);
1448
1449 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1450 do {
1451 struct sparc_stackf32 *usf, sf;
1452 unsigned long pc;
1453
1454 usf = (struct sparc_stackf32 *) ufp;
1455 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1456 break;
1457
1458 pc = sf.callers_pc;
1459 ufp = (unsigned long)sf.fp;
1460 perf_callchain_store(entry, pc);
1461 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1462}
1463
1464void
1465perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1466{
1467 flushw_user();
1468 if (test_thread_flag(TIF_32BIT))
1469 perf_callchain_user_32(entry, regs);
1470 else
1471 perf_callchain_user_64(entry, regs);
1472}
1/* Performance event support for sparc64.
2 *
3 * Copyright (C) 2009, 2010 David S. Miller <davem@davemloft.net>
4 *
5 * This code is based almost entirely upon the x86 perf event
6 * code, which is:
7 *
8 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
9 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
10 * Copyright (C) 2009 Jaswinder Singh Rajput
11 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
12 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
13 */
14
15#include <linux/perf_event.h>
16#include <linux/kprobes.h>
17#include <linux/ftrace.h>
18#include <linux/kernel.h>
19#include <linux/kdebug.h>
20#include <linux/mutex.h>
21
22#include <asm/stacktrace.h>
23#include <asm/cpudata.h>
24#include <asm/uaccess.h>
25#include <linux/atomic.h>
26#include <asm/nmi.h>
27#include <asm/pcr.h>
28#include <asm/cacheflush.h>
29
30#include "kernel.h"
31#include "kstack.h"
32
33/* Two classes of sparc64 chips currently exist. All of which have
34 * 32-bit counters which can generate overflow interrupts on the
35 * transition from 0xffffffff to 0.
36 *
37 * All chips upto and including SPARC-T3 have two performance
38 * counters. The two 32-bit counters are accessed in one go using a
39 * single 64-bit register.
40 *
41 * On these older chips both counters are controlled using a single
42 * control register. The only way to stop all sampling is to clear
43 * all of the context (user, supervisor, hypervisor) sampling enable
44 * bits. But these bits apply to both counters, thus the two counters
45 * can't be enabled/disabled individually.
46 *
47 * Furthermore, the control register on these older chips have two
48 * event fields, one for each of the two counters. It's thus nearly
49 * impossible to have one counter going while keeping the other one
50 * stopped. Therefore it is possible to get overflow interrupts for
51 * counters not currently "in use" and that condition must be checked
52 * in the overflow interrupt handler.
53 *
54 * So we use a hack, in that we program inactive counters with the
55 * "sw_count0" and "sw_count1" events. These count how many times
56 * the instruction "sethi %hi(0xfc000), %g0" is executed. It's an
57 * unusual way to encode a NOP and therefore will not trigger in
58 * normal code.
59 *
60 * Starting with SPARC-T4 we have one control register per counter.
61 * And the counters are stored in individual registers. The registers
62 * for the counters are 64-bit but only a 32-bit counter is
63 * implemented. The event selections on SPARC-T4 lack any
64 * restrictions, therefore we can elide all of the complicated
65 * conflict resolution code we have for SPARC-T3 and earlier chips.
66 */
67
68#define MAX_HWEVENTS 4
69#define MAX_PCRS 4
70#define MAX_PERIOD ((1UL << 32) - 1)
71
72#define PIC_UPPER_INDEX 0
73#define PIC_LOWER_INDEX 1
74#define PIC_NO_INDEX -1
75
76struct cpu_hw_events {
77 /* Number of events currently scheduled onto this cpu.
78 * This tells how many entries in the arrays below
79 * are valid.
80 */
81 int n_events;
82
83 /* Number of new events added since the last hw_perf_disable().
84 * This works because the perf event layer always adds new
85 * events inside of a perf_{disable,enable}() sequence.
86 */
87 int n_added;
88
89 /* Array of events current scheduled on this cpu. */
90 struct perf_event *event[MAX_HWEVENTS];
91
92 /* Array of encoded longs, specifying the %pcr register
93 * encoding and the mask of PIC counters this even can
94 * be scheduled on. See perf_event_encode() et al.
95 */
96 unsigned long events[MAX_HWEVENTS];
97
98 /* The current counter index assigned to an event. When the
99 * event hasn't been programmed into the cpu yet, this will
100 * hold PIC_NO_INDEX. The event->hw.idx value tells us where
101 * we ought to schedule the event.
102 */
103 int current_idx[MAX_HWEVENTS];
104
105 /* Software copy of %pcr register(s) on this cpu. */
106 u64 pcr[MAX_HWEVENTS];
107
108 /* Enabled/disable state. */
109 int enabled;
110
111 unsigned int group_flag;
112};
113DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = { .enabled = 1, };
114
115/* An event map describes the characteristics of a performance
116 * counter event. In particular it gives the encoding as well as
117 * a mask telling which counters the event can be measured on.
118 *
119 * The mask is unused on SPARC-T4 and later.
120 */
121struct perf_event_map {
122 u16 encoding;
123 u8 pic_mask;
124#define PIC_NONE 0x00
125#define PIC_UPPER 0x01
126#define PIC_LOWER 0x02
127};
128
129/* Encode a perf_event_map entry into a long. */
130static unsigned long perf_event_encode(const struct perf_event_map *pmap)
131{
132 return ((unsigned long) pmap->encoding << 16) | pmap->pic_mask;
133}
134
135static u8 perf_event_get_msk(unsigned long val)
136{
137 return val & 0xff;
138}
139
140static u64 perf_event_get_enc(unsigned long val)
141{
142 return val >> 16;
143}
144
145#define C(x) PERF_COUNT_HW_CACHE_##x
146
147#define CACHE_OP_UNSUPPORTED 0xfffe
148#define CACHE_OP_NONSENSE 0xffff
149
150typedef struct perf_event_map cache_map_t
151 [PERF_COUNT_HW_CACHE_MAX]
152 [PERF_COUNT_HW_CACHE_OP_MAX]
153 [PERF_COUNT_HW_CACHE_RESULT_MAX];
154
155struct sparc_pmu {
156 const struct perf_event_map *(*event_map)(int);
157 const cache_map_t *cache_map;
158 int max_events;
159 u32 (*read_pmc)(int);
160 void (*write_pmc)(int, u64);
161 int upper_shift;
162 int lower_shift;
163 int event_mask;
164 int user_bit;
165 int priv_bit;
166 int hv_bit;
167 int irq_bit;
168 int upper_nop;
169 int lower_nop;
170 unsigned int flags;
171#define SPARC_PMU_ALL_EXCLUDES_SAME 0x00000001
172#define SPARC_PMU_HAS_CONFLICTS 0x00000002
173 int max_hw_events;
174 int num_pcrs;
175 int num_pic_regs;
176};
177
178static u32 sparc_default_read_pmc(int idx)
179{
180 u64 val;
181
182 val = pcr_ops->read_pic(0);
183 if (idx == PIC_UPPER_INDEX)
184 val >>= 32;
185
186 return val & 0xffffffff;
187}
188
189static void sparc_default_write_pmc(int idx, u64 val)
190{
191 u64 shift, mask, pic;
192
193 shift = 0;
194 if (idx == PIC_UPPER_INDEX)
195 shift = 32;
196
197 mask = ((u64) 0xffffffff) << shift;
198 val <<= shift;
199
200 pic = pcr_ops->read_pic(0);
201 pic &= ~mask;
202 pic |= val;
203 pcr_ops->write_pic(0, pic);
204}
205
206static const struct perf_event_map ultra3_perfmon_event_map[] = {
207 [PERF_COUNT_HW_CPU_CYCLES] = { 0x0000, PIC_UPPER | PIC_LOWER },
208 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x0001, PIC_UPPER | PIC_LOWER },
209 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0009, PIC_LOWER },
210 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0009, PIC_UPPER },
211};
212
213static const struct perf_event_map *ultra3_event_map(int event_id)
214{
215 return &ultra3_perfmon_event_map[event_id];
216}
217
218static const cache_map_t ultra3_cache_map = {
219[C(L1D)] = {
220 [C(OP_READ)] = {
221 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
222 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
223 },
224 [C(OP_WRITE)] = {
225 [C(RESULT_ACCESS)] = { 0x0a, PIC_LOWER },
226 [C(RESULT_MISS)] = { 0x0a, PIC_UPPER },
227 },
228 [C(OP_PREFETCH)] = {
229 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
230 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
231 },
232},
233[C(L1I)] = {
234 [C(OP_READ)] = {
235 [C(RESULT_ACCESS)] = { 0x09, PIC_LOWER, },
236 [C(RESULT_MISS)] = { 0x09, PIC_UPPER, },
237 },
238 [ C(OP_WRITE) ] = {
239 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
240 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
241 },
242 [ C(OP_PREFETCH) ] = {
243 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
244 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
245 },
246},
247[C(LL)] = {
248 [C(OP_READ)] = {
249 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER, },
250 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER, },
251 },
252 [C(OP_WRITE)] = {
253 [C(RESULT_ACCESS)] = { 0x0c, PIC_LOWER },
254 [C(RESULT_MISS)] = { 0x0c, PIC_UPPER },
255 },
256 [C(OP_PREFETCH)] = {
257 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
258 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
259 },
260},
261[C(DTLB)] = {
262 [C(OP_READ)] = {
263 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
264 [C(RESULT_MISS)] = { 0x12, PIC_UPPER, },
265 },
266 [ C(OP_WRITE) ] = {
267 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
268 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
269 },
270 [ C(OP_PREFETCH) ] = {
271 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
272 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
273 },
274},
275[C(ITLB)] = {
276 [C(OP_READ)] = {
277 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
278 [C(RESULT_MISS)] = { 0x11, PIC_UPPER, },
279 },
280 [ C(OP_WRITE) ] = {
281 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
282 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
283 },
284 [ C(OP_PREFETCH) ] = {
285 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
286 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
287 },
288},
289[C(BPU)] = {
290 [C(OP_READ)] = {
291 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
292 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
293 },
294 [ C(OP_WRITE) ] = {
295 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
296 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
297 },
298 [ C(OP_PREFETCH) ] = {
299 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
300 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
301 },
302},
303[C(NODE)] = {
304 [C(OP_READ)] = {
305 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
306 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
307 },
308 [ C(OP_WRITE) ] = {
309 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
310 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
311 },
312 [ C(OP_PREFETCH) ] = {
313 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
314 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
315 },
316},
317};
318
319static const struct sparc_pmu ultra3_pmu = {
320 .event_map = ultra3_event_map,
321 .cache_map = &ultra3_cache_map,
322 .max_events = ARRAY_SIZE(ultra3_perfmon_event_map),
323 .read_pmc = sparc_default_read_pmc,
324 .write_pmc = sparc_default_write_pmc,
325 .upper_shift = 11,
326 .lower_shift = 4,
327 .event_mask = 0x3f,
328 .user_bit = PCR_UTRACE,
329 .priv_bit = PCR_STRACE,
330 .upper_nop = 0x1c,
331 .lower_nop = 0x14,
332 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
333 SPARC_PMU_HAS_CONFLICTS),
334 .max_hw_events = 2,
335 .num_pcrs = 1,
336 .num_pic_regs = 1,
337};
338
339/* Niagara1 is very limited. The upper PIC is hard-locked to count
340 * only instructions, so it is free running which creates all kinds of
341 * problems. Some hardware designs make one wonder if the creator
342 * even looked at how this stuff gets used by software.
343 */
344static const struct perf_event_map niagara1_perfmon_event_map[] = {
345 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, PIC_UPPER },
346 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, PIC_UPPER },
347 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0, PIC_NONE },
348 [PERF_COUNT_HW_CACHE_MISSES] = { 0x03, PIC_LOWER },
349};
350
351static const struct perf_event_map *niagara1_event_map(int event_id)
352{
353 return &niagara1_perfmon_event_map[event_id];
354}
355
356static const cache_map_t niagara1_cache_map = {
357[C(L1D)] = {
358 [C(OP_READ)] = {
359 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
360 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
361 },
362 [C(OP_WRITE)] = {
363 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
364 [C(RESULT_MISS)] = { 0x03, PIC_LOWER, },
365 },
366 [C(OP_PREFETCH)] = {
367 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
368 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
369 },
370},
371[C(L1I)] = {
372 [C(OP_READ)] = {
373 [C(RESULT_ACCESS)] = { 0x00, PIC_UPPER },
374 [C(RESULT_MISS)] = { 0x02, PIC_LOWER, },
375 },
376 [ C(OP_WRITE) ] = {
377 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
378 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
379 },
380 [ C(OP_PREFETCH) ] = {
381 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
382 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
383 },
384},
385[C(LL)] = {
386 [C(OP_READ)] = {
387 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
388 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
389 },
390 [C(OP_WRITE)] = {
391 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
392 [C(RESULT_MISS)] = { 0x07, PIC_LOWER, },
393 },
394 [C(OP_PREFETCH)] = {
395 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
396 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
397 },
398},
399[C(DTLB)] = {
400 [C(OP_READ)] = {
401 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
402 [C(RESULT_MISS)] = { 0x05, PIC_LOWER, },
403 },
404 [ C(OP_WRITE) ] = {
405 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
406 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
407 },
408 [ C(OP_PREFETCH) ] = {
409 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
410 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
411 },
412},
413[C(ITLB)] = {
414 [C(OP_READ)] = {
415 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
416 [C(RESULT_MISS)] = { 0x04, PIC_LOWER, },
417 },
418 [ C(OP_WRITE) ] = {
419 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
420 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
421 },
422 [ C(OP_PREFETCH) ] = {
423 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
424 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
425 },
426},
427[C(BPU)] = {
428 [C(OP_READ)] = {
429 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
430 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
431 },
432 [ C(OP_WRITE) ] = {
433 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
434 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
435 },
436 [ C(OP_PREFETCH) ] = {
437 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
438 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
439 },
440},
441[C(NODE)] = {
442 [C(OP_READ)] = {
443 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
444 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
445 },
446 [ C(OP_WRITE) ] = {
447 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
448 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
449 },
450 [ C(OP_PREFETCH) ] = {
451 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
452 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
453 },
454},
455};
456
457static const struct sparc_pmu niagara1_pmu = {
458 .event_map = niagara1_event_map,
459 .cache_map = &niagara1_cache_map,
460 .max_events = ARRAY_SIZE(niagara1_perfmon_event_map),
461 .read_pmc = sparc_default_read_pmc,
462 .write_pmc = sparc_default_write_pmc,
463 .upper_shift = 0,
464 .lower_shift = 4,
465 .event_mask = 0x7,
466 .user_bit = PCR_UTRACE,
467 .priv_bit = PCR_STRACE,
468 .upper_nop = 0x0,
469 .lower_nop = 0x0,
470 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
471 SPARC_PMU_HAS_CONFLICTS),
472 .max_hw_events = 2,
473 .num_pcrs = 1,
474 .num_pic_regs = 1,
475};
476
477static const struct perf_event_map niagara2_perfmon_event_map[] = {
478 [PERF_COUNT_HW_CPU_CYCLES] = { 0x02ff, PIC_UPPER | PIC_LOWER },
479 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x02ff, PIC_UPPER | PIC_LOWER },
480 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x0208, PIC_UPPER | PIC_LOWER },
481 [PERF_COUNT_HW_CACHE_MISSES] = { 0x0302, PIC_UPPER | PIC_LOWER },
482 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x0201, PIC_UPPER | PIC_LOWER },
483 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x0202, PIC_UPPER | PIC_LOWER },
484};
485
486static const struct perf_event_map *niagara2_event_map(int event_id)
487{
488 return &niagara2_perfmon_event_map[event_id];
489}
490
491static const cache_map_t niagara2_cache_map = {
492[C(L1D)] = {
493 [C(OP_READ)] = {
494 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
495 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
496 },
497 [C(OP_WRITE)] = {
498 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
499 [C(RESULT_MISS)] = { 0x0302, PIC_UPPER | PIC_LOWER, },
500 },
501 [C(OP_PREFETCH)] = {
502 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
503 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
504 },
505},
506[C(L1I)] = {
507 [C(OP_READ)] = {
508 [C(RESULT_ACCESS)] = { 0x02ff, PIC_UPPER | PIC_LOWER, },
509 [C(RESULT_MISS)] = { 0x0301, PIC_UPPER | PIC_LOWER, },
510 },
511 [ C(OP_WRITE) ] = {
512 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
513 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
514 },
515 [ C(OP_PREFETCH) ] = {
516 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
517 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
518 },
519},
520[C(LL)] = {
521 [C(OP_READ)] = {
522 [C(RESULT_ACCESS)] = { 0x0208, PIC_UPPER | PIC_LOWER, },
523 [C(RESULT_MISS)] = { 0x0330, PIC_UPPER | PIC_LOWER, },
524 },
525 [C(OP_WRITE)] = {
526 [C(RESULT_ACCESS)] = { 0x0210, PIC_UPPER | PIC_LOWER, },
527 [C(RESULT_MISS)] = { 0x0320, PIC_UPPER | PIC_LOWER, },
528 },
529 [C(OP_PREFETCH)] = {
530 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
531 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
532 },
533},
534[C(DTLB)] = {
535 [C(OP_READ)] = {
536 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
537 [C(RESULT_MISS)] = { 0x0b08, PIC_UPPER | PIC_LOWER, },
538 },
539 [ C(OP_WRITE) ] = {
540 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
541 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
542 },
543 [ C(OP_PREFETCH) ] = {
544 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
545 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
546 },
547},
548[C(ITLB)] = {
549 [C(OP_READ)] = {
550 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
551 [C(RESULT_MISS)] = { 0xb04, PIC_UPPER | PIC_LOWER, },
552 },
553 [ C(OP_WRITE) ] = {
554 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
555 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
556 },
557 [ C(OP_PREFETCH) ] = {
558 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
559 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
560 },
561},
562[C(BPU)] = {
563 [C(OP_READ)] = {
564 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
565 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
566 },
567 [ C(OP_WRITE) ] = {
568 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
569 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
570 },
571 [ C(OP_PREFETCH) ] = {
572 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
573 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
574 },
575},
576[C(NODE)] = {
577 [C(OP_READ)] = {
578 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
579 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
580 },
581 [ C(OP_WRITE) ] = {
582 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
583 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
584 },
585 [ C(OP_PREFETCH) ] = {
586 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
587 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
588 },
589},
590};
591
592static const struct sparc_pmu niagara2_pmu = {
593 .event_map = niagara2_event_map,
594 .cache_map = &niagara2_cache_map,
595 .max_events = ARRAY_SIZE(niagara2_perfmon_event_map),
596 .read_pmc = sparc_default_read_pmc,
597 .write_pmc = sparc_default_write_pmc,
598 .upper_shift = 19,
599 .lower_shift = 6,
600 .event_mask = 0xfff,
601 .user_bit = PCR_UTRACE,
602 .priv_bit = PCR_STRACE,
603 .hv_bit = PCR_N2_HTRACE,
604 .irq_bit = 0x30,
605 .upper_nop = 0x220,
606 .lower_nop = 0x220,
607 .flags = (SPARC_PMU_ALL_EXCLUDES_SAME |
608 SPARC_PMU_HAS_CONFLICTS),
609 .max_hw_events = 2,
610 .num_pcrs = 1,
611 .num_pic_regs = 1,
612};
613
614static const struct perf_event_map niagara4_perfmon_event_map[] = {
615 [PERF_COUNT_HW_CPU_CYCLES] = { (26 << 6) },
616 [PERF_COUNT_HW_INSTRUCTIONS] = { (3 << 6) | 0x3f },
617 [PERF_COUNT_HW_CACHE_REFERENCES] = { (3 << 6) | 0x04 },
618 [PERF_COUNT_HW_CACHE_MISSES] = { (16 << 6) | 0x07 },
619 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { (4 << 6) | 0x01 },
620 [PERF_COUNT_HW_BRANCH_MISSES] = { (25 << 6) | 0x0f },
621};
622
623static const struct perf_event_map *niagara4_event_map(int event_id)
624{
625 return &niagara4_perfmon_event_map[event_id];
626}
627
628static const cache_map_t niagara4_cache_map = {
629[C(L1D)] = {
630 [C(OP_READ)] = {
631 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
632 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
633 },
634 [C(OP_WRITE)] = {
635 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
636 [C(RESULT_MISS)] = { (16 << 6) | 0x07 },
637 },
638 [C(OP_PREFETCH)] = {
639 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
640 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
641 },
642},
643[C(L1I)] = {
644 [C(OP_READ)] = {
645 [C(RESULT_ACCESS)] = { (3 << 6) | 0x3f },
646 [C(RESULT_MISS)] = { (11 << 6) | 0x03 },
647 },
648 [ C(OP_WRITE) ] = {
649 [ C(RESULT_ACCESS) ] = { CACHE_OP_NONSENSE },
650 [ C(RESULT_MISS) ] = { CACHE_OP_NONSENSE },
651 },
652 [ C(OP_PREFETCH) ] = {
653 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
654 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
655 },
656},
657[C(LL)] = {
658 [C(OP_READ)] = {
659 [C(RESULT_ACCESS)] = { (3 << 6) | 0x04 },
660 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
661 },
662 [C(OP_WRITE)] = {
663 [C(RESULT_ACCESS)] = { (3 << 6) | 0x08 },
664 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
665 },
666 [C(OP_PREFETCH)] = {
667 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
668 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
669 },
670},
671[C(DTLB)] = {
672 [C(OP_READ)] = {
673 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
674 [C(RESULT_MISS)] = { (17 << 6) | 0x3f },
675 },
676 [ C(OP_WRITE) ] = {
677 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
678 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
679 },
680 [ C(OP_PREFETCH) ] = {
681 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
682 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
683 },
684},
685[C(ITLB)] = {
686 [C(OP_READ)] = {
687 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
688 [C(RESULT_MISS)] = { (6 << 6) | 0x3f },
689 },
690 [ C(OP_WRITE) ] = {
691 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
692 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
693 },
694 [ C(OP_PREFETCH) ] = {
695 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
696 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
697 },
698},
699[C(BPU)] = {
700 [C(OP_READ)] = {
701 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
702 [C(RESULT_MISS)] = { CACHE_OP_UNSUPPORTED },
703 },
704 [ C(OP_WRITE) ] = {
705 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
706 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
707 },
708 [ C(OP_PREFETCH) ] = {
709 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
710 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
711 },
712},
713[C(NODE)] = {
714 [C(OP_READ)] = {
715 [C(RESULT_ACCESS)] = { CACHE_OP_UNSUPPORTED },
716 [C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
717 },
718 [ C(OP_WRITE) ] = {
719 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
720 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
721 },
722 [ C(OP_PREFETCH) ] = {
723 [ C(RESULT_ACCESS) ] = { CACHE_OP_UNSUPPORTED },
724 [ C(RESULT_MISS) ] = { CACHE_OP_UNSUPPORTED },
725 },
726},
727};
728
729static u32 sparc_vt_read_pmc(int idx)
730{
731 u64 val = pcr_ops->read_pic(idx);
732
733 return val & 0xffffffff;
734}
735
736static void sparc_vt_write_pmc(int idx, u64 val)
737{
738 u64 pcr;
739
740 /* There seems to be an internal latch on the overflow event
741 * on SPARC-T4 that prevents it from triggering unless you
742 * update the PIC exactly as we do here. The requirement
743 * seems to be that you have to turn off event counting in the
744 * PCR around the PIC update.
745 *
746 * For example, after the following sequence:
747 *
748 * 1) set PIC to -1
749 * 2) enable event counting and overflow reporting in PCR
750 * 3) overflow triggers, softint 15 handler invoked
751 * 4) clear OV bit in PCR
752 * 5) write PIC to -1
753 *
754 * a subsequent overflow event will not trigger. This
755 * sequence works on SPARC-T3 and previous chips.
756 */
757 pcr = pcr_ops->read_pcr(idx);
758 pcr_ops->write_pcr(idx, PCR_N4_PICNPT);
759
760 pcr_ops->write_pic(idx, val & 0xffffffff);
761
762 pcr_ops->write_pcr(idx, pcr);
763}
764
765static const struct sparc_pmu niagara4_pmu = {
766 .event_map = niagara4_event_map,
767 .cache_map = &niagara4_cache_map,
768 .max_events = ARRAY_SIZE(niagara4_perfmon_event_map),
769 .read_pmc = sparc_vt_read_pmc,
770 .write_pmc = sparc_vt_write_pmc,
771 .upper_shift = 5,
772 .lower_shift = 5,
773 .event_mask = 0x7ff,
774 .user_bit = PCR_N4_UTRACE,
775 .priv_bit = PCR_N4_STRACE,
776
777 /* We explicitly don't support hypervisor tracing. The T4
778 * generates the overflow event for precise events via a trap
779 * which will not be generated (ie. it's completely lost) if
780 * we happen to be in the hypervisor when the event triggers.
781 * Essentially, the overflow event reporting is completely
782 * unusable when you have hypervisor mode tracing enabled.
783 */
784 .hv_bit = 0,
785
786 .irq_bit = PCR_N4_TOE,
787 .upper_nop = 0,
788 .lower_nop = 0,
789 .flags = 0,
790 .max_hw_events = 4,
791 .num_pcrs = 4,
792 .num_pic_regs = 4,
793};
794
795static const struct sparc_pmu *sparc_pmu __read_mostly;
796
797static u64 event_encoding(u64 event_id, int idx)
798{
799 if (idx == PIC_UPPER_INDEX)
800 event_id <<= sparc_pmu->upper_shift;
801 else
802 event_id <<= sparc_pmu->lower_shift;
803 return event_id;
804}
805
806static u64 mask_for_index(int idx)
807{
808 return event_encoding(sparc_pmu->event_mask, idx);
809}
810
811static u64 nop_for_index(int idx)
812{
813 return event_encoding(idx == PIC_UPPER_INDEX ?
814 sparc_pmu->upper_nop :
815 sparc_pmu->lower_nop, idx);
816}
817
818static inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
819{
820 u64 enc, val, mask = mask_for_index(idx);
821 int pcr_index = 0;
822
823 if (sparc_pmu->num_pcrs > 1)
824 pcr_index = idx;
825
826 enc = perf_event_get_enc(cpuc->events[idx]);
827
828 val = cpuc->pcr[pcr_index];
829 val &= ~mask;
830 val |= event_encoding(enc, idx);
831 cpuc->pcr[pcr_index] = val;
832
833 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
834}
835
836static inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx)
837{
838 u64 mask = mask_for_index(idx);
839 u64 nop = nop_for_index(idx);
840 int pcr_index = 0;
841 u64 val;
842
843 if (sparc_pmu->num_pcrs > 1)
844 pcr_index = idx;
845
846 val = cpuc->pcr[pcr_index];
847 val &= ~mask;
848 val |= nop;
849 cpuc->pcr[pcr_index] = val;
850
851 pcr_ops->write_pcr(pcr_index, cpuc->pcr[pcr_index]);
852}
853
854static u64 sparc_perf_event_update(struct perf_event *event,
855 struct hw_perf_event *hwc, int idx)
856{
857 int shift = 64 - 32;
858 u64 prev_raw_count, new_raw_count;
859 s64 delta;
860
861again:
862 prev_raw_count = local64_read(&hwc->prev_count);
863 new_raw_count = sparc_pmu->read_pmc(idx);
864
865 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
866 new_raw_count) != prev_raw_count)
867 goto again;
868
869 delta = (new_raw_count << shift) - (prev_raw_count << shift);
870 delta >>= shift;
871
872 local64_add(delta, &event->count);
873 local64_sub(delta, &hwc->period_left);
874
875 return new_raw_count;
876}
877
878static int sparc_perf_event_set_period(struct perf_event *event,
879 struct hw_perf_event *hwc, int idx)
880{
881 s64 left = local64_read(&hwc->period_left);
882 s64 period = hwc->sample_period;
883 int ret = 0;
884
885 if (unlikely(left <= -period)) {
886 left = period;
887 local64_set(&hwc->period_left, left);
888 hwc->last_period = period;
889 ret = 1;
890 }
891
892 if (unlikely(left <= 0)) {
893 left += period;
894 local64_set(&hwc->period_left, left);
895 hwc->last_period = period;
896 ret = 1;
897 }
898 if (left > MAX_PERIOD)
899 left = MAX_PERIOD;
900
901 local64_set(&hwc->prev_count, (u64)-left);
902
903 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff);
904
905 perf_event_update_userpage(event);
906
907 return ret;
908}
909
910static void read_in_all_counters(struct cpu_hw_events *cpuc)
911{
912 int i;
913
914 for (i = 0; i < cpuc->n_events; i++) {
915 struct perf_event *cp = cpuc->event[i];
916
917 if (cpuc->current_idx[i] != PIC_NO_INDEX &&
918 cpuc->current_idx[i] != cp->hw.idx) {
919 sparc_perf_event_update(cp, &cp->hw,
920 cpuc->current_idx[i]);
921 cpuc->current_idx[i] = PIC_NO_INDEX;
922 }
923 }
924}
925
926/* On this PMU all PICs are programmed using a single PCR. Calculate
927 * the combined control register value.
928 *
929 * For such chips we require that all of the events have the same
930 * configuration, so just fetch the settings from the first entry.
931 */
932static void calculate_single_pcr(struct cpu_hw_events *cpuc)
933{
934 int i;
935
936 if (!cpuc->n_added)
937 goto out;
938
939 /* Assign to counters all unassigned events. */
940 for (i = 0; i < cpuc->n_events; i++) {
941 struct perf_event *cp = cpuc->event[i];
942 struct hw_perf_event *hwc = &cp->hw;
943 int idx = hwc->idx;
944 u64 enc;
945
946 if (cpuc->current_idx[i] != PIC_NO_INDEX)
947 continue;
948
949 sparc_perf_event_set_period(cp, hwc, idx);
950 cpuc->current_idx[i] = idx;
951
952 enc = perf_event_get_enc(cpuc->events[i]);
953 cpuc->pcr[0] &= ~mask_for_index(idx);
954 if (hwc->state & PERF_HES_STOPPED)
955 cpuc->pcr[0] |= nop_for_index(idx);
956 else
957 cpuc->pcr[0] |= event_encoding(enc, idx);
958 }
959out:
960 cpuc->pcr[0] |= cpuc->event[0]->hw.config_base;
961}
962
963/* On this PMU each PIC has it's own PCR control register. */
964static void calculate_multiple_pcrs(struct cpu_hw_events *cpuc)
965{
966 int i;
967
968 if (!cpuc->n_added)
969 goto out;
970
971 for (i = 0; i < cpuc->n_events; i++) {
972 struct perf_event *cp = cpuc->event[i];
973 struct hw_perf_event *hwc = &cp->hw;
974 int idx = hwc->idx;
975 u64 enc;
976
977 if (cpuc->current_idx[i] != PIC_NO_INDEX)
978 continue;
979
980 sparc_perf_event_set_period(cp, hwc, idx);
981 cpuc->current_idx[i] = idx;
982
983 enc = perf_event_get_enc(cpuc->events[i]);
984 cpuc->pcr[idx] &= ~mask_for_index(idx);
985 if (hwc->state & PERF_HES_STOPPED)
986 cpuc->pcr[idx] |= nop_for_index(idx);
987 else
988 cpuc->pcr[idx] |= event_encoding(enc, idx);
989 }
990out:
991 for (i = 0; i < cpuc->n_events; i++) {
992 struct perf_event *cp = cpuc->event[i];
993 int idx = cp->hw.idx;
994
995 cpuc->pcr[idx] |= cp->hw.config_base;
996 }
997}
998
999/* If performance event entries have been added, move existing events
1000 * around (if necessary) and then assign new entries to counters.
1001 */
1002static void update_pcrs_for_enable(struct cpu_hw_events *cpuc)
1003{
1004 if (cpuc->n_added)
1005 read_in_all_counters(cpuc);
1006
1007 if (sparc_pmu->num_pcrs == 1) {
1008 calculate_single_pcr(cpuc);
1009 } else {
1010 calculate_multiple_pcrs(cpuc);
1011 }
1012}
1013
1014static void sparc_pmu_enable(struct pmu *pmu)
1015{
1016 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1017 int i;
1018
1019 if (cpuc->enabled)
1020 return;
1021
1022 cpuc->enabled = 1;
1023 barrier();
1024
1025 if (cpuc->n_events)
1026 update_pcrs_for_enable(cpuc);
1027
1028 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1029 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1030}
1031
1032static void sparc_pmu_disable(struct pmu *pmu)
1033{
1034 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1035 int i;
1036
1037 if (!cpuc->enabled)
1038 return;
1039
1040 cpuc->enabled = 0;
1041 cpuc->n_added = 0;
1042
1043 for (i = 0; i < sparc_pmu->num_pcrs; i++) {
1044 u64 val = cpuc->pcr[i];
1045
1046 val &= ~(sparc_pmu->user_bit | sparc_pmu->priv_bit |
1047 sparc_pmu->hv_bit | sparc_pmu->irq_bit);
1048 cpuc->pcr[i] = val;
1049 pcr_ops->write_pcr(i, cpuc->pcr[i]);
1050 }
1051}
1052
1053static int active_event_index(struct cpu_hw_events *cpuc,
1054 struct perf_event *event)
1055{
1056 int i;
1057
1058 for (i = 0; i < cpuc->n_events; i++) {
1059 if (cpuc->event[i] == event)
1060 break;
1061 }
1062 BUG_ON(i == cpuc->n_events);
1063 return cpuc->current_idx[i];
1064}
1065
1066static void sparc_pmu_start(struct perf_event *event, int flags)
1067{
1068 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1069 int idx = active_event_index(cpuc, event);
1070
1071 if (flags & PERF_EF_RELOAD) {
1072 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1073 sparc_perf_event_set_period(event, &event->hw, idx);
1074 }
1075
1076 event->hw.state = 0;
1077
1078 sparc_pmu_enable_event(cpuc, &event->hw, idx);
1079}
1080
1081static void sparc_pmu_stop(struct perf_event *event, int flags)
1082{
1083 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1084 int idx = active_event_index(cpuc, event);
1085
1086 if (!(event->hw.state & PERF_HES_STOPPED)) {
1087 sparc_pmu_disable_event(cpuc, &event->hw, idx);
1088 event->hw.state |= PERF_HES_STOPPED;
1089 }
1090
1091 if (!(event->hw.state & PERF_HES_UPTODATE) && (flags & PERF_EF_UPDATE)) {
1092 sparc_perf_event_update(event, &event->hw, idx);
1093 event->hw.state |= PERF_HES_UPTODATE;
1094 }
1095}
1096
1097static void sparc_pmu_del(struct perf_event *event, int _flags)
1098{
1099 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1100 unsigned long flags;
1101 int i;
1102
1103 local_irq_save(flags);
1104 perf_pmu_disable(event->pmu);
1105
1106 for (i = 0; i < cpuc->n_events; i++) {
1107 if (event == cpuc->event[i]) {
1108 /* Absorb the final count and turn off the
1109 * event.
1110 */
1111 sparc_pmu_stop(event, PERF_EF_UPDATE);
1112
1113 /* Shift remaining entries down into
1114 * the existing slot.
1115 */
1116 while (++i < cpuc->n_events) {
1117 cpuc->event[i - 1] = cpuc->event[i];
1118 cpuc->events[i - 1] = cpuc->events[i];
1119 cpuc->current_idx[i - 1] =
1120 cpuc->current_idx[i];
1121 }
1122
1123 perf_event_update_userpage(event);
1124
1125 cpuc->n_events--;
1126 break;
1127 }
1128 }
1129
1130 perf_pmu_enable(event->pmu);
1131 local_irq_restore(flags);
1132}
1133
1134static void sparc_pmu_read(struct perf_event *event)
1135{
1136 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1137 int idx = active_event_index(cpuc, event);
1138 struct hw_perf_event *hwc = &event->hw;
1139
1140 sparc_perf_event_update(event, hwc, idx);
1141}
1142
1143static atomic_t active_events = ATOMIC_INIT(0);
1144static DEFINE_MUTEX(pmc_grab_mutex);
1145
1146static void perf_stop_nmi_watchdog(void *unused)
1147{
1148 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1149 int i;
1150
1151 stop_nmi_watchdog(NULL);
1152 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1153 cpuc->pcr[i] = pcr_ops->read_pcr(i);
1154}
1155
1156void perf_event_grab_pmc(void)
1157{
1158 if (atomic_inc_not_zero(&active_events))
1159 return;
1160
1161 mutex_lock(&pmc_grab_mutex);
1162 if (atomic_read(&active_events) == 0) {
1163 if (atomic_read(&nmi_active) > 0) {
1164 on_each_cpu(perf_stop_nmi_watchdog, NULL, 1);
1165 BUG_ON(atomic_read(&nmi_active) != 0);
1166 }
1167 atomic_inc(&active_events);
1168 }
1169 mutex_unlock(&pmc_grab_mutex);
1170}
1171
1172void perf_event_release_pmc(void)
1173{
1174 if (atomic_dec_and_mutex_lock(&active_events, &pmc_grab_mutex)) {
1175 if (atomic_read(&nmi_active) == 0)
1176 on_each_cpu(start_nmi_watchdog, NULL, 1);
1177 mutex_unlock(&pmc_grab_mutex);
1178 }
1179}
1180
1181static const struct perf_event_map *sparc_map_cache_event(u64 config)
1182{
1183 unsigned int cache_type, cache_op, cache_result;
1184 const struct perf_event_map *pmap;
1185
1186 if (!sparc_pmu->cache_map)
1187 return ERR_PTR(-ENOENT);
1188
1189 cache_type = (config >> 0) & 0xff;
1190 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
1191 return ERR_PTR(-EINVAL);
1192
1193 cache_op = (config >> 8) & 0xff;
1194 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
1195 return ERR_PTR(-EINVAL);
1196
1197 cache_result = (config >> 16) & 0xff;
1198 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1199 return ERR_PTR(-EINVAL);
1200
1201 pmap = &((*sparc_pmu->cache_map)[cache_type][cache_op][cache_result]);
1202
1203 if (pmap->encoding == CACHE_OP_UNSUPPORTED)
1204 return ERR_PTR(-ENOENT);
1205
1206 if (pmap->encoding == CACHE_OP_NONSENSE)
1207 return ERR_PTR(-EINVAL);
1208
1209 return pmap;
1210}
1211
1212static void hw_perf_event_destroy(struct perf_event *event)
1213{
1214 perf_event_release_pmc();
1215}
1216
1217/* Make sure all events can be scheduled into the hardware at
1218 * the same time. This is simplified by the fact that we only
1219 * need to support 2 simultaneous HW events.
1220 *
1221 * As a side effect, the evts[]->hw.idx values will be assigned
1222 * on success. These are pending indexes. When the events are
1223 * actually programmed into the chip, these values will propagate
1224 * to the per-cpu cpuc->current_idx[] slots, see the code in
1225 * maybe_change_configuration() for details.
1226 */
1227static int sparc_check_constraints(struct perf_event **evts,
1228 unsigned long *events, int n_ev)
1229{
1230 u8 msk0 = 0, msk1 = 0;
1231 int idx0 = 0;
1232
1233 /* This case is possible when we are invoked from
1234 * hw_perf_group_sched_in().
1235 */
1236 if (!n_ev)
1237 return 0;
1238
1239 if (n_ev > sparc_pmu->max_hw_events)
1240 return -1;
1241
1242 if (!(sparc_pmu->flags & SPARC_PMU_HAS_CONFLICTS)) {
1243 int i;
1244
1245 for (i = 0; i < n_ev; i++)
1246 evts[i]->hw.idx = i;
1247 return 0;
1248 }
1249
1250 msk0 = perf_event_get_msk(events[0]);
1251 if (n_ev == 1) {
1252 if (msk0 & PIC_LOWER)
1253 idx0 = 1;
1254 goto success;
1255 }
1256 BUG_ON(n_ev != 2);
1257 msk1 = perf_event_get_msk(events[1]);
1258
1259 /* If both events can go on any counter, OK. */
1260 if (msk0 == (PIC_UPPER | PIC_LOWER) &&
1261 msk1 == (PIC_UPPER | PIC_LOWER))
1262 goto success;
1263
1264 /* If one event is limited to a specific counter,
1265 * and the other can go on both, OK.
1266 */
1267 if ((msk0 == PIC_UPPER || msk0 == PIC_LOWER) &&
1268 msk1 == (PIC_UPPER | PIC_LOWER)) {
1269 if (msk0 & PIC_LOWER)
1270 idx0 = 1;
1271 goto success;
1272 }
1273
1274 if ((msk1 == PIC_UPPER || msk1 == PIC_LOWER) &&
1275 msk0 == (PIC_UPPER | PIC_LOWER)) {
1276 if (msk1 & PIC_UPPER)
1277 idx0 = 1;
1278 goto success;
1279 }
1280
1281 /* If the events are fixed to different counters, OK. */
1282 if ((msk0 == PIC_UPPER && msk1 == PIC_LOWER) ||
1283 (msk0 == PIC_LOWER && msk1 == PIC_UPPER)) {
1284 if (msk0 & PIC_LOWER)
1285 idx0 = 1;
1286 goto success;
1287 }
1288
1289 /* Otherwise, there is a conflict. */
1290 return -1;
1291
1292success:
1293 evts[0]->hw.idx = idx0;
1294 if (n_ev == 2)
1295 evts[1]->hw.idx = idx0 ^ 1;
1296 return 0;
1297}
1298
1299static int check_excludes(struct perf_event **evts, int n_prev, int n_new)
1300{
1301 int eu = 0, ek = 0, eh = 0;
1302 struct perf_event *event;
1303 int i, n, first;
1304
1305 if (!(sparc_pmu->flags & SPARC_PMU_ALL_EXCLUDES_SAME))
1306 return 0;
1307
1308 n = n_prev + n_new;
1309 if (n <= 1)
1310 return 0;
1311
1312 first = 1;
1313 for (i = 0; i < n; i++) {
1314 event = evts[i];
1315 if (first) {
1316 eu = event->attr.exclude_user;
1317 ek = event->attr.exclude_kernel;
1318 eh = event->attr.exclude_hv;
1319 first = 0;
1320 } else if (event->attr.exclude_user != eu ||
1321 event->attr.exclude_kernel != ek ||
1322 event->attr.exclude_hv != eh) {
1323 return -EAGAIN;
1324 }
1325 }
1326
1327 return 0;
1328}
1329
1330static int collect_events(struct perf_event *group, int max_count,
1331 struct perf_event *evts[], unsigned long *events,
1332 int *current_idx)
1333{
1334 struct perf_event *event;
1335 int n = 0;
1336
1337 if (!is_software_event(group)) {
1338 if (n >= max_count)
1339 return -1;
1340 evts[n] = group;
1341 events[n] = group->hw.event_base;
1342 current_idx[n++] = PIC_NO_INDEX;
1343 }
1344 list_for_each_entry(event, &group->sibling_list, group_entry) {
1345 if (!is_software_event(event) &&
1346 event->state != PERF_EVENT_STATE_OFF) {
1347 if (n >= max_count)
1348 return -1;
1349 evts[n] = event;
1350 events[n] = event->hw.event_base;
1351 current_idx[n++] = PIC_NO_INDEX;
1352 }
1353 }
1354 return n;
1355}
1356
1357static int sparc_pmu_add(struct perf_event *event, int ef_flags)
1358{
1359 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1360 int n0, ret = -EAGAIN;
1361 unsigned long flags;
1362
1363 local_irq_save(flags);
1364 perf_pmu_disable(event->pmu);
1365
1366 n0 = cpuc->n_events;
1367 if (n0 >= sparc_pmu->max_hw_events)
1368 goto out;
1369
1370 cpuc->event[n0] = event;
1371 cpuc->events[n0] = event->hw.event_base;
1372 cpuc->current_idx[n0] = PIC_NO_INDEX;
1373
1374 event->hw.state = PERF_HES_UPTODATE;
1375 if (!(ef_flags & PERF_EF_START))
1376 event->hw.state |= PERF_HES_STOPPED;
1377
1378 /*
1379 * If group events scheduling transaction was started,
1380 * skip the schedulability test here, it will be performed
1381 * at commit time(->commit_txn) as a whole
1382 */
1383 if (cpuc->group_flag & PERF_EVENT_TXN)
1384 goto nocheck;
1385
1386 if (check_excludes(cpuc->event, n0, 1))
1387 goto out;
1388 if (sparc_check_constraints(cpuc->event, cpuc->events, n0 + 1))
1389 goto out;
1390
1391nocheck:
1392 cpuc->n_events++;
1393 cpuc->n_added++;
1394
1395 ret = 0;
1396out:
1397 perf_pmu_enable(event->pmu);
1398 local_irq_restore(flags);
1399 return ret;
1400}
1401
1402static int sparc_pmu_event_init(struct perf_event *event)
1403{
1404 struct perf_event_attr *attr = &event->attr;
1405 struct perf_event *evts[MAX_HWEVENTS];
1406 struct hw_perf_event *hwc = &event->hw;
1407 unsigned long events[MAX_HWEVENTS];
1408 int current_idx_dmy[MAX_HWEVENTS];
1409 const struct perf_event_map *pmap;
1410 int n;
1411
1412 if (atomic_read(&nmi_active) < 0)
1413 return -ENODEV;
1414
1415 /* does not support taken branch sampling */
1416 if (has_branch_stack(event))
1417 return -EOPNOTSUPP;
1418
1419 switch (attr->type) {
1420 case PERF_TYPE_HARDWARE:
1421 if (attr->config >= sparc_pmu->max_events)
1422 return -EINVAL;
1423 pmap = sparc_pmu->event_map(attr->config);
1424 break;
1425
1426 case PERF_TYPE_HW_CACHE:
1427 pmap = sparc_map_cache_event(attr->config);
1428 if (IS_ERR(pmap))
1429 return PTR_ERR(pmap);
1430 break;
1431
1432 case PERF_TYPE_RAW:
1433 pmap = NULL;
1434 break;
1435
1436 default:
1437 return -ENOENT;
1438
1439 }
1440
1441 if (pmap) {
1442 hwc->event_base = perf_event_encode(pmap);
1443 } else {
1444 /*
1445 * User gives us "(encoding << 16) | pic_mask" for
1446 * PERF_TYPE_RAW events.
1447 */
1448 hwc->event_base = attr->config;
1449 }
1450
1451 /* We save the enable bits in the config_base. */
1452 hwc->config_base = sparc_pmu->irq_bit;
1453 if (!attr->exclude_user)
1454 hwc->config_base |= sparc_pmu->user_bit;
1455 if (!attr->exclude_kernel)
1456 hwc->config_base |= sparc_pmu->priv_bit;
1457 if (!attr->exclude_hv)
1458 hwc->config_base |= sparc_pmu->hv_bit;
1459
1460 n = 0;
1461 if (event->group_leader != event) {
1462 n = collect_events(event->group_leader,
1463 sparc_pmu->max_hw_events - 1,
1464 evts, events, current_idx_dmy);
1465 if (n < 0)
1466 return -EINVAL;
1467 }
1468 events[n] = hwc->event_base;
1469 evts[n] = event;
1470
1471 if (check_excludes(evts, n, 1))
1472 return -EINVAL;
1473
1474 if (sparc_check_constraints(evts, events, n + 1))
1475 return -EINVAL;
1476
1477 hwc->idx = PIC_NO_INDEX;
1478
1479 /* Try to do all error checking before this point, as unwinding
1480 * state after grabbing the PMC is difficult.
1481 */
1482 perf_event_grab_pmc();
1483 event->destroy = hw_perf_event_destroy;
1484
1485 if (!hwc->sample_period) {
1486 hwc->sample_period = MAX_PERIOD;
1487 hwc->last_period = hwc->sample_period;
1488 local64_set(&hwc->period_left, hwc->sample_period);
1489 }
1490
1491 return 0;
1492}
1493
1494/*
1495 * Start group events scheduling transaction
1496 * Set the flag to make pmu::enable() not perform the
1497 * schedulability test, it will be performed at commit time
1498 */
1499static void sparc_pmu_start_txn(struct pmu *pmu)
1500{
1501 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1502
1503 perf_pmu_disable(pmu);
1504 cpuhw->group_flag |= PERF_EVENT_TXN;
1505}
1506
1507/*
1508 * Stop group events scheduling transaction
1509 * Clear the flag and pmu::enable() will perform the
1510 * schedulability test.
1511 */
1512static void sparc_pmu_cancel_txn(struct pmu *pmu)
1513{
1514 struct cpu_hw_events *cpuhw = &__get_cpu_var(cpu_hw_events);
1515
1516 cpuhw->group_flag &= ~PERF_EVENT_TXN;
1517 perf_pmu_enable(pmu);
1518}
1519
1520/*
1521 * Commit group events scheduling transaction
1522 * Perform the group schedulability test as a whole
1523 * Return 0 if success
1524 */
1525static int sparc_pmu_commit_txn(struct pmu *pmu)
1526{
1527 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
1528 int n;
1529
1530 if (!sparc_pmu)
1531 return -EINVAL;
1532
1533 cpuc = &__get_cpu_var(cpu_hw_events);
1534 n = cpuc->n_events;
1535 if (check_excludes(cpuc->event, 0, n))
1536 return -EINVAL;
1537 if (sparc_check_constraints(cpuc->event, cpuc->events, n))
1538 return -EAGAIN;
1539
1540 cpuc->group_flag &= ~PERF_EVENT_TXN;
1541 perf_pmu_enable(pmu);
1542 return 0;
1543}
1544
1545static struct pmu pmu = {
1546 .pmu_enable = sparc_pmu_enable,
1547 .pmu_disable = sparc_pmu_disable,
1548 .event_init = sparc_pmu_event_init,
1549 .add = sparc_pmu_add,
1550 .del = sparc_pmu_del,
1551 .start = sparc_pmu_start,
1552 .stop = sparc_pmu_stop,
1553 .read = sparc_pmu_read,
1554 .start_txn = sparc_pmu_start_txn,
1555 .cancel_txn = sparc_pmu_cancel_txn,
1556 .commit_txn = sparc_pmu_commit_txn,
1557};
1558
1559void perf_event_print_debug(void)
1560{
1561 unsigned long flags;
1562 int cpu, i;
1563
1564 if (!sparc_pmu)
1565 return;
1566
1567 local_irq_save(flags);
1568
1569 cpu = smp_processor_id();
1570
1571 pr_info("\n");
1572 for (i = 0; i < sparc_pmu->num_pcrs; i++)
1573 pr_info("CPU#%d: PCR%d[%016llx]\n",
1574 cpu, i, pcr_ops->read_pcr(i));
1575 for (i = 0; i < sparc_pmu->num_pic_regs; i++)
1576 pr_info("CPU#%d: PIC%d[%016llx]\n",
1577 cpu, i, pcr_ops->read_pic(i));
1578
1579 local_irq_restore(flags);
1580}
1581
1582static int __kprobes perf_event_nmi_handler(struct notifier_block *self,
1583 unsigned long cmd, void *__args)
1584{
1585 struct die_args *args = __args;
1586 struct perf_sample_data data;
1587 struct cpu_hw_events *cpuc;
1588 struct pt_regs *regs;
1589 int i;
1590
1591 if (!atomic_read(&active_events))
1592 return NOTIFY_DONE;
1593
1594 switch (cmd) {
1595 case DIE_NMI:
1596 break;
1597
1598 default:
1599 return NOTIFY_DONE;
1600 }
1601
1602 regs = args->regs;
1603
1604 cpuc = &__get_cpu_var(cpu_hw_events);
1605
1606 /* If the PMU has the TOE IRQ enable bits, we need to do a
1607 * dummy write to the %pcr to clear the overflow bits and thus
1608 * the interrupt.
1609 *
1610 * Do this before we peek at the counters to determine
1611 * overflow so we don't lose any events.
1612 */
1613 if (sparc_pmu->irq_bit &&
1614 sparc_pmu->num_pcrs == 1)
1615 pcr_ops->write_pcr(0, cpuc->pcr[0]);
1616
1617 for (i = 0; i < cpuc->n_events; i++) {
1618 struct perf_event *event = cpuc->event[i];
1619 int idx = cpuc->current_idx[i];
1620 struct hw_perf_event *hwc;
1621 u64 val;
1622
1623 if (sparc_pmu->irq_bit &&
1624 sparc_pmu->num_pcrs > 1)
1625 pcr_ops->write_pcr(idx, cpuc->pcr[idx]);
1626
1627 hwc = &event->hw;
1628 val = sparc_perf_event_update(event, hwc, idx);
1629 if (val & (1ULL << 31))
1630 continue;
1631
1632 perf_sample_data_init(&data, 0, hwc->last_period);
1633 if (!sparc_perf_event_set_period(event, hwc, idx))
1634 continue;
1635
1636 if (perf_event_overflow(event, &data, regs))
1637 sparc_pmu_stop(event, 0);
1638 }
1639
1640 return NOTIFY_STOP;
1641}
1642
1643static __read_mostly struct notifier_block perf_event_nmi_notifier = {
1644 .notifier_call = perf_event_nmi_handler,
1645};
1646
1647static bool __init supported_pmu(void)
1648{
1649 if (!strcmp(sparc_pmu_type, "ultra3") ||
1650 !strcmp(sparc_pmu_type, "ultra3+") ||
1651 !strcmp(sparc_pmu_type, "ultra3i") ||
1652 !strcmp(sparc_pmu_type, "ultra4+")) {
1653 sparc_pmu = &ultra3_pmu;
1654 return true;
1655 }
1656 if (!strcmp(sparc_pmu_type, "niagara")) {
1657 sparc_pmu = &niagara1_pmu;
1658 return true;
1659 }
1660 if (!strcmp(sparc_pmu_type, "niagara2") ||
1661 !strcmp(sparc_pmu_type, "niagara3")) {
1662 sparc_pmu = &niagara2_pmu;
1663 return true;
1664 }
1665 if (!strcmp(sparc_pmu_type, "niagara4")) {
1666 sparc_pmu = &niagara4_pmu;
1667 return true;
1668 }
1669 return false;
1670}
1671
1672int __init init_hw_perf_events(void)
1673{
1674 pr_info("Performance events: ");
1675
1676 if (!supported_pmu()) {
1677 pr_cont("No support for PMU type '%s'\n", sparc_pmu_type);
1678 return 0;
1679 }
1680
1681 pr_cont("Supported PMU type is '%s'\n", sparc_pmu_type);
1682
1683 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1684 register_die_notifier(&perf_event_nmi_notifier);
1685
1686 return 0;
1687}
1688early_initcall(init_hw_perf_events);
1689
1690void perf_callchain_kernel(struct perf_callchain_entry *entry,
1691 struct pt_regs *regs)
1692{
1693 unsigned long ksp, fp;
1694#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1695 int graph = 0;
1696#endif
1697
1698 stack_trace_flush();
1699
1700 perf_callchain_store(entry, regs->tpc);
1701
1702 ksp = regs->u_regs[UREG_I6];
1703 fp = ksp + STACK_BIAS;
1704 do {
1705 struct sparc_stackf *sf;
1706 struct pt_regs *regs;
1707 unsigned long pc;
1708
1709 if (!kstack_valid(current_thread_info(), fp))
1710 break;
1711
1712 sf = (struct sparc_stackf *) fp;
1713 regs = (struct pt_regs *) (sf + 1);
1714
1715 if (kstack_is_trap_frame(current_thread_info(), regs)) {
1716 if (user_mode(regs))
1717 break;
1718 pc = regs->tpc;
1719 fp = regs->u_regs[UREG_I6] + STACK_BIAS;
1720 } else {
1721 pc = sf->callers_pc;
1722 fp = (unsigned long)sf->fp + STACK_BIAS;
1723 }
1724 perf_callchain_store(entry, pc);
1725#ifdef CONFIG_FUNCTION_GRAPH_TRACER
1726 if ((pc + 8UL) == (unsigned long) &return_to_handler) {
1727 int index = current->curr_ret_stack;
1728 if (current->ret_stack && index >= graph) {
1729 pc = current->ret_stack[index - graph].ret;
1730 perf_callchain_store(entry, pc);
1731 graph++;
1732 }
1733 }
1734#endif
1735 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1736}
1737
1738static void perf_callchain_user_64(struct perf_callchain_entry *entry,
1739 struct pt_regs *regs)
1740{
1741 unsigned long ufp;
1742
1743 ufp = regs->u_regs[UREG_I6] + STACK_BIAS;
1744 do {
1745 struct sparc_stackf *usf, sf;
1746 unsigned long pc;
1747
1748 usf = (struct sparc_stackf *) ufp;
1749 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1750 break;
1751
1752 pc = sf.callers_pc;
1753 ufp = (unsigned long)sf.fp + STACK_BIAS;
1754 perf_callchain_store(entry, pc);
1755 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1756}
1757
1758static void perf_callchain_user_32(struct perf_callchain_entry *entry,
1759 struct pt_regs *regs)
1760{
1761 unsigned long ufp;
1762
1763 ufp = regs->u_regs[UREG_I6] & 0xffffffffUL;
1764 do {
1765 unsigned long pc;
1766
1767 if (thread32_stack_is_64bit(ufp)) {
1768 struct sparc_stackf *usf, sf;
1769
1770 ufp += STACK_BIAS;
1771 usf = (struct sparc_stackf *) ufp;
1772 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1773 break;
1774 pc = sf.callers_pc & 0xffffffff;
1775 ufp = ((unsigned long) sf.fp) & 0xffffffff;
1776 } else {
1777 struct sparc_stackf32 *usf, sf;
1778 usf = (struct sparc_stackf32 *) ufp;
1779 if (__copy_from_user_inatomic(&sf, usf, sizeof(sf)))
1780 break;
1781 pc = sf.callers_pc;
1782 ufp = (unsigned long)sf.fp;
1783 }
1784 perf_callchain_store(entry, pc);
1785 } while (entry->nr < PERF_MAX_STACK_DEPTH);
1786}
1787
1788void
1789perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
1790{
1791 perf_callchain_store(entry, regs->tpc);
1792
1793 if (!current->mm)
1794 return;
1795
1796 flushw_user();
1797 if (test_thread_flag(TIF_32BIT))
1798 perf_callchain_user_32(entry, regs);
1799 else
1800 perf_callchain_user_64(entry, regs);
1801}